CN108054211A - Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof - Google Patents
Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof Download PDFInfo
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- CN108054211A CN108054211A CN201711397404.9A CN201711397404A CN108054211A CN 108054211 A CN108054211 A CN 108054211A CN 201711397404 A CN201711397404 A CN 201711397404A CN 108054211 A CN108054211 A CN 108054211A
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 26
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title description 6
- 238000000407 epitaxy Methods 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010936 titanium Substances 0.000 claims description 48
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 235000007164 Oryza sativa Nutrition 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 235000009566 rice Nutrition 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
A kind of production method of trench vertical bilateral diffusion metal oxide transistor includes：N-type substrate is provided, being formed has first and second opening initial oxide layer, PXing Ti area；Silicon nitride spacer is formed in initial oxide layer side wall, the PXing Ti areas of the first opening are filled up by silicon nitride spacer, and the silicon nitride spacer of the second opening surrounds the 3rd opening；PXing Ti areas are performed etching using the 3rd opening, so as to form first groove in p-type body surface；Initial oxide layer is removed, so as to form the 4th opening surrounded by silicon nitride spacer in initial oxide layer position；PXing Ti areas are etched again using the 3rd opening and the 4th opening, so that first groove deepens and then extends to N-type epitaxy layer through PXing Ti areas, and form corresponding 4th opening, through PXing Ti areas and extend to the second groove in N-type epitaxy layer, first groove depth and width are all higher than second groove；Form gate oxide, polysilicon, N-type source region, contact hole, front metal and back metal.
Description
【Technical field】
The present invention relates to semiconductor fabrication process technical fields, particularly, are related to a kind of trench vertical double diffused metal
Oxide transistor and preparation method thereof.
【Background technology】
It is widely used in field of switch power in groove-shaped VDMOS (vertical bilateral diffusion metallic oxide transistor).Groove
Type vertical DMOS transistor is (referred to as：Groove-shaped VDMOS) it is by source ion and body ion implanting
Longitudinal diffusion range difference is formed afterwards and forms raceway groove, and is widely used in Switching Power Supply and synchronous rectification field.Compared to plane
VDMOS, groove-shaped VDMOS are due to eliminating JFET areas, so its internal resistance is very small.
However, there is the problems such as the process is more complicated, cost is higher in existing groove-shaped VDMOS, it is necessary to improve.In addition,
The manufacturing process flow and device architecture of existing groove-shaped VDMOS, there is still some places to optimize, and further reduces conducting
Resistance.
【The content of the invention】
One of purpose of the present invention is to provide for the above-mentioned at least one technical problem of solution a kind of groove-shaped vertical
Straight bilateral diffusion metal oxide transistor and preparation method thereof.
A kind of production method of trench vertical bilateral diffusion metal oxide transistor comprises the following steps：
N-type substrate is provided, N-type epitaxy layer, initial oxide layer are sequentially formed in the N-type substrate, carries out PXing Ti areas
It injects and drives in, so as to form PXing Ti areas adjacent to the one side of the initial oxide layer in the N-type epitaxy layer；
Photoetching and etching are carried out to the initial oxide layer, so as to formed the first opening through the initial oxide layer with
Second opening；
Silicon nitride spacer is formed in the side wall of neighbouring first and second opening of the initial oxide layer, wherein described
The PXing Ti areas of first opening are filled up by the silicon nitride spacer, and the silicon nitride spacer of second opening surrounds the 3rd and opens
Mouthful；
The PXing Ti areas are performed etching using the described 3rd opening, so as to form the first ditch in the p-type body surface
Slot；
The initial oxide layer is removed, so as to form the surrounded by silicon nitride spacer the 4th in the initial oxide layer position
Opening；
The PXing Ti areas are further etched using the described 3rd opening and the 4th opening, so that first groove is deepened
And then it extends to the N-type epitaxy layer through the PXing Ti areas and forms corresponding 4th opening, through the p-type body
Area simultaneously extends to the second groove in the N-type epitaxy layer, and the first groove depth and width are all higher than the second groove；
Remove the silicon nitride spacer；
Gate oxide and polysilicon are sequentially formed in the first groove and second groove；
N-type ion implanting is carried out to the p-type body surface, so as to form N-type source region in the p-type body surface；
The N-type source region, first and second groove gate oxide and polysilicon on form dielectric layer；
It is formed through the dielectric layer and the N-type source region and extends to the contact hole in the PXing Ti areas；
Front metal is formed on the dielectric layer and forms back metal away from N-type epitaxial surface in the N-type substrate,
The front metal connects the PXing Ti areas by the contact hole.
In one embodiment, the initial oxide layer is grown in the N-type epitaxy layer, the initial oxidation
Layer growth temperature is in the range of 900 degrees Celsius~1100 degrees Celsius, and thickness is in the range of 0.05um~0.3um.
In one embodiment, the injection ion in the PXing Ti areas includes boron, and the dosage of the injection is at every square li
In the range of 13 powers to every square centimeter 1 14 powers of rice 1, the energy of the injection is in the scope of 80KEV to 120KEV
It is interior；To carrying out temperature the step of driving in PXing Ti areas in the range of 1100 degrees Celsius to 1200 degrees Celsius, the time is at 50 points
Clock is in the range of 200 minutes.
In one embodiment, the silicon nitride grown temperature is thick in the range of 600 degrees Celsius~1100 degrees Celsius
Degree is in the range of 0.05um~0.3um.
In one embodiment, the step of removing the initial oxide layer includes：Using described in hydrofluoric acid erosion removal
Initial oxide layer.
In one embodiment, the step of removing the silicon nitride spacer includes：Using described in concentrated phosphoric acid erosion removal
Silicon nitride spacer.
In one embodiment, scope of the growth temperature of the gate oxide at 900 degrees Celsius~1100 degrees Celsius
Interior, thickness is in the range of 0.02um~0.2um, the model of the growth temperature of the polysilicon at 500 degrees Celsius~900 degrees Celsius
In enclosing, thickness is in the range of 0.1um~2um.
In one embodiment, the injection ion of the N-type source region includes phosphorus or arsenic, and the dosage of the injection is put down often
Square centimetre 1 of 15 powers are in the range of every square centimeter 1 16 powers, and the energy of the injection is in 80KEV to 300KEV's
In the range of.
In one embodiment, the material of the front metal includes aluminium alloy, silicon alloy or copper alloy, the back of the body
Face metal includes titanium, nickel, the composite bed of silver.
A kind of trench vertical bilateral diffusion metal oxide transistor including N-type substrate, is formed at the N-type substrate
On N-type epitaxy layer, be formed at the N-type epitaxy layer ShangPXing Ti areas, be formed at the p-type body surface N-type source region,
The dielectric layer that is formed in the N-type source region through the dielectric layer, the N-type source region and the PXing Ti areas and extends to institute
State first groove in N-type epitaxy layer with second groove, be formed at the gate oxide of first and second trench wall, be located at
The polysilicon on gate oxide in first and second described groove through the dielectric layer, the N-type source region and extends to institute
The contact hole in ShuPXing Ti areas, the front gold for being arranged on the dielectric layer and the PXing Ti areas being connected by the contact hole
Belong to and be arranged at the back metal on surface of the N-type substrate away from the N-type epitaxy layer, the first groove depth and width
Degree is all higher than the second groove.
Compared to the prior art, trench vertical bilateral diffusion metal oxide transistor of the present invention and preparation method thereof use
The mode of double grooves of different depth for deeper groove, there is lower conducting resistance on the access of source and drain electrode current.
Part shallow trench is also remained simultaneously, is unlikely to cause the source and drain breakdown voltage of device to reduce.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow chart of the production method of trench vertical bilateral diffusion metal oxide transistor of the present invention.
Fig. 2-Figure 13 is each step of the production method of trench vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure diagram.
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
- Figure 13 is please referred to Fig.1, Fig. 1 is the production method of trench vertical bilateral diffusion metal oxide transistor of the present invention
Flow chart, Fig. 2-Figure 13 be trench vertical bilateral diffusion metal oxide transistor shown in Fig. 1 production method each step
Structure diagram.The production method of the trench vertical bilateral diffusion metal oxide transistor comprises the following steps.
Step S1 referring to Fig. 2, providing N-type substrate, sequentially forms N-type epitaxy layer, initial oxygen in the N-type substrate
Change layer, carry out the injection in PXing Ti areas and drive in, so as to form P adjacent to the one side of the initial oxide layer in the N-type epitaxy layer
Xing Ti areas.Wherein, the initial oxide layer is grown in the N-type epitaxy layer, and the initial oxidation layer growth temperature exists
In the range of 900 degrees Celsius~1100 degrees Celsius, thickness is in the range of 0.05um~0.3um.The injection in the PXing Ti areas from
Attached bag includes boron, and the dosage of the injection is in the range of every square centimeter 1 14 powers of 13 powers to every square centimeter 1, institute
The energy of injection is stated in the range of 80KEV to 120KEV；It is Celsius 1100 to temperature the step of driving in progress PXing Ti areas
It spends in the range of 1200 degrees Celsius, the time is in the range of 50 minutes to 200 minutes.
Step S2, referring to Fig. 3, photoetching and etching are carried out to the initial oxide layer, so as to be formed through described initial
First opening of oxide layer and the second opening.
Step S3, referring to Fig. 4, the side wall in neighbouring first and second opening of the initial oxide layer forms nitrogen
SiClx side wall, wherein the PXing Ti areas of first opening are filled up by the silicon nitride spacer, the nitridation of second opening
Silicon side wall surrounds the 3rd opening.
Step S4, referring to Fig. 5, being performed etching using the described 3rd opening to the PXing Ti areas, so as in the p-type
Body surface forms first groove.
Step S5, referring to Fig. 6, the initial oxide layer is removed, so as to be formed in the initial oxide layer position by nitrogen
The 4th opening that SiClx side wall surrounds.The step of removal initial oxide layer, can include：It is gone using hydrofluoric acid corrosion
Except the initial oxide layer
Step S6, referring to Fig. 7, the PXing Ti areas are further etched using the described 3rd opening and the 4th opening, so as to
So that first groove deepens and then extends to the N-type epitaxy layer through the PXing Ti areas and form the corresponding described 4th to open
Mouthful, through the PXing Ti areas and extend to the second groove in the N-type epitaxy layer, the first groove depth and width are equal
More than the second groove.
Step S7, referring to Fig. 8, removing the silicon nitride spacer.The step S7 can include：Corroded using concentrated phosphoric acid
Remove the silicon nitride spacer.
Step S8, referring to Fig. 9, sequentially forming gate oxide and polysilicon in the first groove and second groove.
Wherein, the growth temperature of the gate oxide is in the range of 900 degrees Celsius~1100 degrees Celsius, thickness 0.02um~
In the range of 0.2um, the growth temperature of the polysilicon is in the range of 500 degrees Celsius~900 degrees Celsius, and thickness is in 0.1um
In the range of~2um.
Step S9, referring to Fig. 10, N-type ion implanting is carried out to the p-type body surface, so as in the PXing Ti areas
Surface forms N-type source region.Wherein, the injection ion of the N-type source region includes phosphorus or arsenic, and the dosage of the injection is at every square li
In the range of 15 powers to every square centimeter 1 16 powers of rice 1, the energy of the injection is in the scope of 80KEV to 300KEV
It is interior.
Step S10, please refers to Fig.1 1, in the N-type source region, the gate oxide and polysilicon of first and second groove
Upper formation dielectric layer.
Step S11 please refers to Fig.1 2, is formed through the dielectric layer and the N-type source region and extends to the PXing Ti areas
In contact hole.
Step S12, please refers to Fig.1 3, front metal is formed on the dielectric layer and outside the N-type substrate is away from N-type
Prolong surface and form back metal, the front metal connects the PXing Ti areas by the contact hole.The material of the front metal
Material includes aluminium alloy, silicon alloy or copper alloy, and the back metal includes titanium, nickel, the composite bed of silver.
Further, as shown in figure 13, the trench vertical bilateral diffusion metal oxide crystal that the production method obtains
Pipe include N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, be formed at the N-type epitaxy layer ShangPXing Ti areas,
It is formed at the N-type source region of the p-type body surface, the dielectric layer being formed in the N-type source region, through the dielectric layer, institute
The first groove stating N-type source region and the PXing Ti areas and extend in the N-type epitaxy layer and second groove, be formed at it is described
The gate oxide of first and second trench wall, the polysilicon on the gate oxide in first and second described groove pass through
It wears the dielectric layer, the N-type source region and extends to the contact hole in the PXing Ti areas, is arranged on the dielectric layer and passes through
The contact hole connects the front metal in the PXing Ti areas and is arranged at table of the N-type substrate away from the N-type epitaxy layer
The back metal in face, the first groove depth and width are all higher than the second groove.
Compared to the prior art, trench vertical bilateral diffusion metal oxide transistor of the present invention and preparation method thereof use
The mode of double grooves of different depth for deeper groove, there is lower conducting resistance on the access of source and drain electrode current.
Part shallow trench is also remained simultaneously, is unlikely to cause the source and drain breakdown voltage of device to reduce.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
- A kind of 1. production method of trench vertical bilateral diffusion metal oxide transistor, which is characterized in that the production method Comprise the following steps：N-type substrate is provided, N-type epitaxy layer, initial oxide layer are sequentially formed in the N-type substrate, carries out the injection in PXing Ti areas And drive in, so as to form PXing Ti areas adjacent to the one side of the initial oxide layer in the N-type epitaxy layer；Photoetching and etching are carried out to the initial oxide layer, so as to form the first opening and second through the initial oxide layer Opening；Silicon nitride spacer is formed in the side wall of neighbouring first and second opening of the initial oxide layer, wherein described first The PXing Ti areas of opening are filled up by the silicon nitride spacer, and the silicon nitride spacer of second opening surrounds the 3rd opening；The PXing Ti areas are performed etching using the described 3rd opening, so as to form first groove in the p-type body surface；The initial oxide layer is removed, is opened so as to form the surrounded by silicon nitride spacer the 4th in the initial oxide layer position Mouthful；Using the described 3rd opening and the 4th opening further etch the PXing Ti areas so that first groove deepen and then Extend to the N-type epitaxy layer through the PXing Ti areas and formed corresponding 4th opening, through the PXing Ti areas simultaneously The second groove in the N-type epitaxy layer is extended to, the first groove depth and width are all higher than the second groove；Remove the silicon nitride spacer；Gate oxide and polysilicon are sequentially formed in the first groove and second groove；N-type ion implanting is carried out to the p-type body surface, so as to form N-type source region in the p-type body surface；The N-type source region, first and second groove gate oxide and polysilicon on form dielectric layer；It is formed through the dielectric layer and the N-type source region and extends to the contact hole in the PXing Ti areas；Front metal is formed on the dielectric layer and forms back metal away from N-type epitaxial surface in the N-type substrate, it is described Front metal connects the PXing Ti areas by the contact hole.
- 2. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The initial oxide layer is grown in the N-type epitaxy layer, the initial oxidation layer growth temperature 900 degrees Celsius~ In the range of 1100 degrees Celsius, thickness is in the range of 0.05um~0.3um.
- 3. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The injection ion in the PXing Ti areas includes boron, the dosage of the injection every square centimeter 1 13 powers to every square centimeter 1 14 powers in the range of, the energy of the injection is in the range of 80KEV to 120KEV；To carrying out driving in for PXing Ti areas The temperature of step is in the range of 1100 degrees Celsius to 1200 degrees Celsius, and the time is in the range of 50 minutes to 200 minutes.
- 4. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The silicon nitride grown temperature is in the range of 600 degrees Celsius~1100 degrees Celsius, and thickness is in the scope of 0.05um~0.3um It is interior.
- 5. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The step of removing the initial oxide layer includes：Using initial oxide layer described in hydrofluoric acid erosion removal.
- 6. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The step of removing the silicon nitride spacer includes：Using silicon nitride spacer described in concentrated phosphoric acid erosion removal.
- 7. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The growth temperature of the gate oxide is in the range of 900 degrees Celsius~1100 degrees Celsius, and thickness is in the model of 0.02um~0.2um In enclosing, the growth temperature of the polysilicon is in the range of 500 degrees Celsius~900 degrees Celsius, and thickness is in the model of 0.1um~2um In enclosing.
- 8. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The injection ion of the N-type source region includes phosphorus or arsenic, the dosage of the injection every square centimeter 1 15 powers to every square li In the range of 16 powers of rice 1, the energy of the injection is in the range of 80KEV to 300KEV.
- 9. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, which is characterized in that The material of the front metal include aluminium alloy, silicon alloy or copper alloy, the back metal include titanium, nickel, silver it is compound Layer.
- A kind of 10. trench vertical bilateral diffusion metal oxide transistor, which is characterized in that the trench vertical double diffusion gold Belonging to oxide transistor includes N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, is formed at the N-type epitaxy layer ShangPXing Ti areas, the N-type source region for being formed at the p-type body surface, the dielectric layer being formed in the N-type source region, through institute State dielectric layer, the N-type source region and the PXing Ti areas and extend to the first groove in the N-type epitaxy layer and second groove, It is formed at the gate oxide of first and second trench wall, on the gate oxide in first and second described groove Polysilicon through the dielectric layer, the N-type source region and extends to the contact hole in the PXing Ti areas, is arranged at the dielectric layer It is upper and the front metal in the PXing Ti areas is connected by the contact hole and be arranged at the N-type substrate away from the N-type outside Prolong the back metal on the surface of layer, the first groove depth and width are all higher than the second groove.
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| CN111192829A (en) * | 2019-05-31 | 2020-05-22 | 深圳方正微电子有限公司 | Groove type VDMOS device and manufacturing method thereof |
| CN112133759A (en) * | 2020-11-25 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device having a shielded gate trench structure and method of manufacturing the same |
| CN115411101A (en) * | 2022-07-22 | 2022-11-29 | 上海林众电子科技有限公司 | Polysilicon emitter IGBT device, preparation method and application thereof |
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