CN103137689A - Semiconductor device with super junction ditch groove metal oxide semiconductor (MOS) structure and manufacture method thereof - Google Patents
Semiconductor device with super junction ditch groove metal oxide semiconductor (MOS) structure and manufacture method thereof Download PDFInfo
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- CN103137689A CN103137689A CN2011103877562A CN201110387756A CN103137689A CN 103137689 A CN103137689 A CN 103137689A CN 2011103877562 A CN2011103877562 A CN 2011103877562A CN 201110387756 A CN201110387756 A CN 201110387756A CN 103137689 A CN103137689 A CN 103137689A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000463 material Substances 0.000 claims description 25
- 230000003628 erosive effect Effects 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 abstract 1
- 238000005036 potential barrier Methods 0.000 abstract 1
- 239000002210 silicon-based material Substances 0.000 description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 125000004437 phosphorous atom Chemical group 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
The invention mainly relates to a semiconductor device with a super junction ditch groove metal oxide semiconductor (MOS) structure. The super junction structure is led in the semiconductor device through a grid electrode. The semiconductor device with the super junction ditch groove MOS structure is a basic structure of a super potential barrier rectifier and a power metal-oxide-semiconductor field effect transistor (MOSFET). The invention further relates to a manufacture technology of the semiconductor device with the super junction ditch groove MOS structure.
Description
Technical field
The present invention is mainly concerned with a kind of super knot trench MOS structure semiconductor device, and super-junction structure is incorporated in semiconductor device, trench MOS structure semiconductor device of the present invention is super barrier rectifier and power MOSFET foundation structure, the invention still further relates to the manufacturing process of super knot trench MOS structure semiconductor device.
Background technology
Semiconductor device with groove structure and super-junction structure has become the important trend that device develops.For power semiconductor, constantly reduce conducting resistance and become with the requirement that improves constantly current density the important trend that device develops.
Conventional groove MOS device has grid oxygen in the trench wall growth, is filled with polysilicon in groove, and groove avris semi-conducting material sets gradually active area, tagma and drain region.Conducting resistance under the device opening state mainly is subject to the drift layer Resistance Influence in drain region.
Summary of the invention
The invention provides a kind of novel trench MOS structure semiconductor device, super-junction structure is incorporated in device by grid, it has low conducting resistance.
A kind of super knot trench MOS structure semiconductor device is characterized in that: comprising:
Substrate layer is semi-conducting material; Drift layer is the semi-conducting material of the first conduction type, is positioned on substrate layer; The tagma is the semi-conducting material of the second conduction type, is positioned on drift layer; A plurality of grooves are arranged in drift layer and tagma, and there is insulating barrier on the trench wall surface, are filled with simultaneously the semi-conducting material of the second conduction type in groove, and the groove internal upper part faces the semi-conducting material that is filled with the first conduction type by insulating barrier; A plurality of source regions are the semi-conducting material of the first conduction type, face by groove and tagma.
The semi-conducting material of second conduction type of filling in wherein said groove, top can be polycrystalline semiconductor material, and is the high concentration impurities doping, lower area can be single-crystal semiconductor material, and is the low concentration impurity doping.The semi-conducting material of first conduction type of filling in wherein said groove can be polycrystalline semiconductor material.Wherein said trenched side-wall surface lower insulation layer thickness is greater than trenched side-wall upper surface thickness of insulating layer.The semi-conducting material of filling the second conduction type in the semi-conducting material of the first conduction type of drift layer and groove can form super-junction structure, when device connects reverse biased, form charge compensation, thereby realize that electric field relatively evenly distributes, namely can improve the drift layer impurity doping content in drain region, thereby realize reducing greatly the drift layer resistance in drain region.
The manufacture method of a kind of super knot trench MOS structure semiconductor device of the present invention is characterized in that: comprise the steps:
Form the semi-conducting material tagma of semi-conducting material drift layer and second conduction type of the first conduction type by epitaxial growth on substrate layer; Form passivation layer on the surface, at trench region surface removal passivation layer to be formed; Carry out the first conduction type Impurity Diffusion; Carry out the etching semiconductor material, form groove; Form insulating barrier at trench wall; Form the semi-conducting material of the second conduction type in groove, anti-carve the semi-conducting material of erosion the second conduction type, then etching insulating layer; Form the semi-conducting material of the first conduction type in groove, anti-carve the semi-conducting material of erosion the first conduction type; Form the semi-conducting material of the second conduction type in groove, anti-carve the semi-conducting material of erosion the second conduction type.
Trench MOS structure semiconductor device of the present invention is incorporated into super-junction structure in trench MOS structure by grid, compares with traditional groove MOS device, has reduced the conducting resistance of device.
Description of drawings
Fig. 1 is trench MOS structure semiconductor device the first execution mode generalized section of the present invention;
Fig. 2 is trench MOS structure semiconductor device the second execution mode generalized section of the present invention;
Fig. 3 is the generalized section that in the embodiment of the present invention 1, technique is made second step;
Fig. 4 is the generalized section that in the embodiment of the present invention 1, technique made for the 3rd step;
Fig. 5 is the generalized section that in the embodiment of the present invention 1, technique made for the 5th step;
Fig. 6 is the generalized section that in the embodiment of the present invention 1, technique made for the 6th step;
Fig. 7 is the generalized section that in the embodiment of the present invention 1, technique made for the 6th step;
Fig. 8 is the generalized section that in the embodiment of the present invention 1, technique made for the 7th step;
Fig. 9 is the generalized section that in the embodiment of the present invention 1, technique made for the 7th step.
Wherein, 1, substrate layer; 2, drift layer; 3, tagma; 4, source region; 5, oxide layer; 6, P type polycrystalline semiconductor material; 8, N-type polycrystalline semiconductor material; 9, P type single-crystal semiconductor material.
Embodiment
Fig. 1 shows the schematic cross sectional view of first case semiconductor device of the present invention, describes trench MOS structure semiconductor device of the present invention in detail below in conjunction with Fig. 1 and makes the MOSFET device.
A kind of trench MOS structure semiconductor device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the phosphorus atoms doping content is 1E19cm
-3Drift layer 2 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the phosphorus atoms doping content is 1E16cm
-3, thickness is 20um; Tagma 3 is positioned on drift layer 2, is the semiconductor silicon material of P conduction type, and the surface in tagma 3 has boron atom heavy doping contact zone, and tagma 3 thickness are 4um; Source region 4 is faced by groove and tagma 3, is the semiconductor silicon material of phosphorus atoms heavy doping N conduction type, and source region 4 thickness are 1.5um; Oxide layer 5, the oxide for silicon materials is positioned at trench wall; P type polycrystalline semiconductor material 6 for P type poly semiconductor silicon materials, is positioned at groove, and top is that high concentration boron is atom doped, and boron atom doped concentration in bottom is 2E16cm
-3The width of groove is 2um, and the spacing between groove is 4um, and groove runs through whole drift layer 2.
In the present embodiment, the technique manufacturing process of trench MOS structure semiconductor device is as follows:
The first step forms drift layer 2 and tagma 3 by epitaxial growth on substrate layer 1;
Second step forms oxide layer 5 in the surface heat oxidation, in trench region surface removal oxide layer 5 to be formed, as shown in Figure 3;
The 3rd step, carry out phosphorus diffusion, form source region 4, erosion removal trench region surface oxide layer 5 to be formed then, as shown in Figure 4;
The 4th step, carry out dry etching, remove semi-conducting material, form groove;
In the 5th step, form oxide layer 5 in the trench wall thermal oxidation, as shown in Figure 5;
In the 6th step, deposit P type polycrystalline semiconductor material 6, anti-carve erosion in groove, as shown in Figure 5, and erosion removal partial oxidation layer 5, as shown in Figure 7.
In the 7th step, deposit N-type polycrystalline semiconductor material 8, as shown in Figure 8, anti-carve erosion, as shown in Figure 9 in groove.
In the 8th step, deposit P type polycrystalline semiconductor material 6, anti-carve erosion in groove, erosion removal surface portion oxide layer 5, as shown in Figure 1.
Then on this basis, at the surface deposition passivation layer, then erosion removal surface portion passivation layer, then depositing metal aluminium anti-carve aluminium, for device is drawn source electrode and grid.Be that device is drawn drain electrode by back side metallization technology.
As mentioned above, when device adds reversed bias voltage, grid potential and source electrode are suitable, so drift layer 2 and P type polycrystalline semiconductor material 6 can form super-junction structure, produce charge compensation, electric field relatively evenly distributes, and namely can realize drift layer 2 impurity high-concentration dopants, thereby reduces greatly the conducting resistance of device.
Fig. 2 shows the schematic cross sectional view of second case semiconductor device of the present invention, describes trench MOS structure semiconductor device of the present invention in detail below in conjunction with Fig. 2 and makes the MOSFET device.
A kind of trench MOS structure semiconductor device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the phosphorus atoms doping content is 1E19cm
-3Drift layer 2 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the phosphorus atoms doping content is 1E16cm
-3, thickness is 20um; Tagma 3 is positioned on drift layer 2, is the semiconductor silicon material of P conduction type, and the surface in tagma 3 has boron atom heavy doping contact zone, and tagma 3 thickness are 4um; Source region 4 is faced by groove and tagma 3, is the semiconductor silicon material of phosphorus atoms heavy doping N conduction type, and source region 4 thickness are 1.5um; Oxide layer 5, the oxide for silicon materials is positioned at trench wall; P type polycrystalline semiconductor material 6 is P type poly semiconductor silicon materials, and being positioned at the groove internal upper part is that high concentration boron is atom doped; N-type polycrystalline semiconductor material 8 is N-type poly semiconductor silicon materials, and being positioned at the groove internal upper part is that high concentration phosphorus is atom doped; P type single-crystal semiconductor material 9 is P type single crystal semiconductor silicon materials, and the atom doped concentration of boron is 2E16cm
-3The width of groove is 2um, and the spacing between groove is 4um, and groove runs through whole drift layer 2.
In the present embodiment, the technique manufacturing process of trench MOS structure semiconductor device is as follows:
The first step forms drift layer 2 and tagma 3 by epitaxial growth on substrate layer 1;
Second step forms oxide layer 5 in the surface heat oxidation, in trench region surface removal oxide layer 5 to be formed;
The 3rd step, carry out the phosphorus diffusion, form source region 4, then erosion removal trench region surface oxide layer 5 to be formed;
The 4th step, carry out dry etching, remove semi-conducting material, form groove;
In the 5th step, form oxide layer 5 in the trench wall thermal oxidation, as shown in Figure 5;
In the 6th step, deposit P type single-crystal semiconductor material 9, anti-carve erosion in groove, erosion removal partial oxidation layer 5.
In the 7th step, deposit N-type polycrystalline semiconductor material 8, anti-carve erosion in groove.
In the 8th step, deposit P type polycrystalline semiconductor material 6, anti-carve erosion in groove, erosion removal surface portion oxide layer 5, as shown in Figure 2.
Then on this basis, at the surface deposition passivation layer, then erosion removal surface portion passivation layer, then depositing metal aluminium anti-carve aluminium, for device is drawn source electrode and grid.Be that device is drawn drain electrode by back side metallization technology.
As mentioned above, when device adds reversed bias voltage, grid potential and source electrode are suitable, so drift layer 2 and P type single-crystal semiconductor material 9 can form super-junction structure, produce charge compensation, electric field relatively evenly distributes, and namely can realize drift layer 2 impurity high-concentration dopants, thereby reduces greatly the conducting resistance of device.
Set forth the present invention by above-mentioned two examples, also can adopt other example to realize the present invention simultaneously.The present invention is not limited to above-mentioned instantiation, and for example the present invention also can be applicable to super barrier rectifier.Therefore the present invention is by the claims circumscription.
Claims (9)
1. one kind surpasses knot trench MOS structure semiconductor device, it is characterized in that: comprising:
Substrate layer is semi-conducting material;
Drift layer is the semi-conducting material of the first conduction type, is positioned on substrate layer;
The tagma is the semi-conducting material of the second conduction type, is positioned on drift layer; A plurality of
Groove is arranged in drift layer and tagma, and there is insulating barrier on the trench wall surface, is filled with simultaneously the semi-conducting material of the second conduction type in groove, and the groove internal upper part faces the semi-conducting material that is filled with the first conduction type by insulating barrier; A plurality of
The source region is the semi-conducting material of the first conduction type, faces by groove and tagma.
2. semiconductor device as claimed in claim 1 is characterized in that: the semi-conducting material of second conduction type of filling in described groove can be polycrystalline semiconductor material, and upper area is the high concentration impurities doping, and lower area is the low concentration impurity doping.
3. semiconductor device as claimed in claim 1 is characterized in that: the semi-conducting material of filling the second conduction type in described groove can be polycrystalline semiconductor material, and upper area is the high concentration impurities doping, and lower area is the low concentration impurity doping.
4. semiconductor device as claimed in claim 1, it is characterized in that: the semi-conducting material of second conduction type of filling in described groove, top can be polycrystalline semiconductor material, and is the high concentration impurities doping, lower area can be single-crystal semiconductor material, and is the low concentration impurity doping.
5. semiconductor device as claimed in claim 1, it is characterized in that: the semi-conducting material of filling the second conduction type in the semi-conducting material of the first conduction type of described drift layer and groove can form super-junction structure, when device connects reverse biased, form charge compensation, thereby realize that electric field relatively evenly distributes.
6. semiconductor device as claimed in claim 1 is characterized in that: the semi-conducting material of first conduction type of filling in described groove can be polycrystalline semiconductor material.
7. semiconductor device as claimed in claim 1, it is characterized in that: described trenched side-wall lower surface thickness of insulating layer is greater than trenched side-wall upper face thickness of insulating layer.
8. semiconductor device as claimed in claim 1, is characterized in that: the close MOS raceway groove of the semi-conducting material of the first conduction type in described groove.
9. the manufacture method of a super knot trench MOS structure semiconductor device, is characterized in that: comprise the steps:
1) form the semi-conducting material tagma of semi-conducting material drift layer and second conduction type of the first conduction type by epitaxial growth on substrate layer;
2) form passivation layer on the surface, at trench region surface removal passivation layer to be formed;
3) carry out the first conduction type Impurity Diffusion;
4) carry out the etching semiconductor material, form groove;
5) form insulating barrier at trench wall;
6) form the semi-conducting material of the second conduction type in groove, anti-carve the semi-conducting material of erosion the second conduction type, then etching insulating layer;
7) form the semi-conducting material of the first conduction type in groove, anti-carve the semi-conducting material of erosion the first conduction type;
8) form the semi-conducting material of the second conduction type in groove, anti-carve the semi-conducting material of erosion the second conduction type.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367433A (en) * | 2012-04-02 | 2013-10-23 | 朱江 | Groove super junction MOS (Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN105826360A (en) * | 2015-01-07 | 2016-08-03 | 北大方正集团有限公司 | Trench-type semi super junction power device and manufacturing method thereof |
| CN105826375A (en) * | 2015-01-07 | 2016-08-03 | 北大方正集团有限公司 | Trench-type semi super junction power device and manufacturing method thereof |
| CN112802903A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Groove gate VDMOS device with improved gate structure |
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| US20080061364A1 (en) * | 2006-09-12 | 2008-03-13 | Dongbu Hitek Co., Ltd. | Trench type MOS transistor and method for manufacturing the same |
| CN101719495A (en) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | Semiconductor device and manufacturing method thereof |
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- 2011-11-25 CN CN201110387756.2A patent/CN103137689B/en active Active
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| CN101019235A (en) * | 2004-09-03 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | Vertical semiconductor devices and methods of manufacturing such devices |
| US20080061364A1 (en) * | 2006-09-12 | 2008-03-13 | Dongbu Hitek Co., Ltd. | Trench type MOS transistor and method for manufacturing the same |
| CN101719495A (en) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367433A (en) * | 2012-04-02 | 2013-10-23 | 朱江 | Groove super junction MOS (Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN103367433B (en) * | 2012-04-02 | 2017-08-08 | 朱江 | A kind of groove super junction MOS device and its manufacture method |
| CN105826360A (en) * | 2015-01-07 | 2016-08-03 | 北大方正集团有限公司 | Trench-type semi super junction power device and manufacturing method thereof |
| CN105826375A (en) * | 2015-01-07 | 2016-08-03 | 北大方正集团有限公司 | Trench-type semi super junction power device and manufacturing method thereof |
| CN105826375B (en) * | 2015-01-07 | 2018-12-04 | 北大方正集团有限公司 | Groove-shaped half super junction power device of one kind and preparation method thereof |
| CN105826360B (en) * | 2015-01-07 | 2019-10-15 | 北大方正集团有限公司 | Groove-shaped half super junction power device and preparation method thereof |
| CN112802903A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Groove gate VDMOS device with improved gate structure |
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