CN102751314A - Groove mean opinion score (MOS) structure semiconductor device and preparation method thereof - Google Patents
Groove mean opinion score (MOS) structure semiconductor device and preparation method thereof Download PDFInfo
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- CN102751314A CN102751314A CN2011100982247A CN201110098224A CN102751314A CN 102751314 A CN102751314 A CN 102751314A CN 2011100982247 A CN2011100982247 A CN 2011100982247A CN 201110098224 A CN201110098224 A CN 201110098224A CN 102751314 A CN102751314 A CN 102751314A
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Abstract
The invention discloses a groove mean opinion score (MOS) structure semiconductor device. Gate oxide grows on the inner walls of grooves and grid electrode mesons are filled in the grooves. The whole upper portions of semiconductor materials between the grooves are provided with first conducting semiconductor material body areas, and the lower portions of the first conducting semiconductor material body areas are provided with second conducting semiconductor material leaking areas. The upper portions inside groove side lateral body areas are provided with second conducting semiconductor material source areas, and in the groove side lateral body areas, second conducting semiconductor material passive areas are arranged on the lower portions of the source areas and the upper portions of the leaking areas. The invention further provides a preparation method of the groove MOS structure semiconductor device. Super barrier rectifiers manufactured by means of the preparation method of the groove MOS structure semiconductor device have the advantage that the electrical parameters can be optimized.
Description
Technical field
The present invention relates to a kind of trench MOS structure semiconductor device, it is the foundation structure of super barrier rectifier, can be used for making semiconductor device such as super barrier rectifier, the invention still further relates to a kind of preparation method of trench MOS structure semiconductor device.
Background technology
Semiconductor device with trench MOS structure has become the important trend that device develops, and the requirement that requirement that constantly reduces cost and power device improve constantly the current density electrical property becomes the important trend of device development.
The super potential barrier rectifier diode profile of tradition is as shown in Figure 3; The whole inwall growth of vertical trench has grid oxygen 5; Be filled with grid polycrystalline silicon 6 in the groove; Be provided with source region 4, tagma 3 and drain region 2 in the silicon body of groove avris from top to bottom, upper surface metal 10 is with the anode of grid polycrystalline silicon 6, source region 4 and tagma 3 parallel connection formation devices, and the substrate layer 1 of lower surface metal layer 11 interface units constitutes the negative electrode of device.The length in tagma is determining the size of the reverse breakdown voltage of device between tradition super potential barrier rectifier diode source region 4 and the drain region 2.Along with the increase of tagma length between source region 4 and the drain region 2, the reverse breakdown voltage of device also will raise, the conducting resistance when also having increased the device forward conduction widely simultaneously.
Summary of the invention
The present invention develops according to this problem, and when purpose was to improve the reverse breakdown voltage of device, traditional relatively super potential barrier rectifier diode can reduce the forward conduction resistance of device.
The present invention provides a kind of trench MOS structure semiconductor device and preparation method thereof, and this semiconductor device is a foundation structure of making a kind of novel super potential barrier rectifier diode.
A kind of trench MOS structure semiconductor device comprises: the trench wall growth has grid oxygen, is filled with the grid meson in the groove; The whole top of semi-conducting material is provided with P type semiconductor material tagma between the groove; In bottom, P type semiconductor material tagma is N type semiconductor material drain region; Groove avris tagma internal upper part is provided with N type semiconductor material source region; In groove avris tagma, top, drain region, bottom, source region is provided with N type semiconductor material passive region.Wherein said in groove avris tagma the passive region on top, drain region, bottom, source region can be a plurality of passive regions that are separated from each other, be vertically set in the groove avris tagma, be P type semiconductor material tagma between passive region and the passive region; Being P type semiconductor material tagma between wherein said source region and the passive region, is P type semiconductor material tagma between drain region and the passive region, and filling the grid meson in the groove is polysilicon.
The preparation method of MOS structural semiconductor device of the present invention is characterized in that: comprise the steps: 1) there is the silicon chip of epitaxial loayer to carry out the tagma diffusion of impurities to long on substrate, and spread propelling, above epitaxial loayer, form the tagma; 2) form hard mask at silicon chip surface, at the hard mask of trench area surface removal to be formed; 3) carry out N type diffusion of impurities at formation window region; 4) form groove at etching semiconductor material of formation window region; 5) inject N type impurity, annealing then; 6) through the secondarily etched semi-conducting material of row, form darker groove; 7) at the semiconductor material surface of trench wall growth grid oxygen; 8) carry out the polysilicon deposit, polysilicon is returned etching; 9) carry out the corrosion of source region and tagma surface passivation layer; 10) surface deposition metal forms the device anode with source electrode, tagma and grid parallel connection.Wherein the tagma diffusion of impurities uses method for implanting to realize, injection is divided into twice to be carried out, and once injects to advance to forming the tagma, and secondary is injected to the ohmic contact regions on surface, formation tagma.The degree of depth of an etching semiconductor material is less than the junction depth in tagma simultaneously.
Using trench MOS structure semiconductor device of the present invention and preparation method thereof is example to make super potential barrier rectifier diode; In the source region of device and the tagma between the drain region, add N type semiconductor material passive region; Thereby increase length between source region and the drain region; Can improve the reverse breakdown voltage of device, also can reduce the length in P type semiconductor material tagma 3 between source region and the drain region simultaneously, therefore when device adds forward bias; Actual transoid semi-conducting material length in the P type semiconductor material tagma of groove avris also will reduce; Thereby reduced the forward conduction resistance of device, thereby reduced the forward voltage drop of device under certain current density, realized the optimization of device electrical parameter.Compare with the super potential barrier rectifier diode of tradition; Under the situation of identical reverse breakdown voltage; Can reduce the conducting resistance of device greatly; Perhaps also can be regarded as when under certain current density condition, having identical forward voltage drop, trench MOS structure semiconductor device of the present invention has higher reverse breakdown pressure drop.
Description of drawings
Fig. 1 is that trench MOS structure semiconductor device applications of the present invention is in the generalized section of making a kind of super potential barrier rectifier diode;
Fig. 2 is the generalized section of conventional trench MOS structure power rectification diode;
Fig. 3 is one embodiment of the present invention technology generalized section in the 7th step;
Fig. 4 is one embodiment of the present invention technology generalized section in the 8th step.
Wherein, 1, substrate layer; 2, drain region; 3, tagma; 4, source region; 5, grid oxygen; 6, grid polycrystalline silicon; 7, passive region; 8, thermal oxidation oxide layer; 9, silicon nitride layer; 10, upper surface metal level; 11, lower surface metal layer.
Embodiment
Fig. 1 specifies semiconductor device of the present invention and preparation method thereof for the generalized section that trench MOS structure semiconductor device of the present invention and preparation method are applied to make a kind of super potential barrier rectifier diode below in conjunction with Fig. 1.
A kind of super potential barrier rectifier diode comprises: substrate layer 1 is N conductive type semiconductor material, at substrate layer 1 lower surface, through lower surface metal layer 11 extraction electrodes; Drain region 2 is positioned on the substrate layer 1, is the semi-conducting material of N conduction type; Tagma 3 is positioned on the drain region 2, and tagma 3 is the semi-conducting material of P conduction type; Source region 4 is positioned among 3 upper surfaces of tagma, is the semi-conducting material of N conduction type; Passive region 7 is positioned at the semi-conducting material tagma 3 of groove avris, and passive region 7 is the semi-conducting material of N conduction type; Vertical trench is positioned at the silicon body, and its inwall growth has grid oxygen 5, is filled with grid polycrystalline silicon 6 in the groove, is provided with source region 4, tagma 3, passive region 7 and drain region 2 in the silicon body of groove avris from top to bottom; The device upper surface is drawn another electrode anode with source region 4, tagma 3 and grid parallel connection for device with upper surface metal level 10.
Its manufacture craft comprises the steps: the first step, to having silicon chip epitaxial growth one deck N type silicon layer of high concentration N type doping impurity substrate layer 1; Second step, once inject the p type impurity diffusion and advance formation tagma 3, original epitaxial loayer carries out secondary p type impurity implantation annealing again as drain region 2; The 3rd step, deposit one deck silicon nitride layer 9 on silicon chip surface thermal oxidation oxide layer 8; In the 4th step, photoetching corrosion is removed photoresist in trench area surface removal silicon nitride layer 9 to be formed and thermal oxidation oxide layer 8; The 5th step, carry out phosphorous diffusion, form N type electric conducting material district in the silicon body under window; The 6th step, to carry out the silicon dry etching with silicon nitride layer 9 as protective layer and form groove, the degree of depth of the groove of etching is less than the junction depth in tagma 3; The 7th step, carry out the phosphorus impurities implantation annealing, in channel bottom tagma 3, form N type electric conducting material passive region 7, as shown in Figure 3; In the 8th step, erosion grooves inner wall oxide layer is proceeded the silicon dry etching with silicon nitride layer 9 as protective layer and is formed darker groove, and the degree of depth of the groove of etching is greater than 3 the junction depth in the tagma, and is as shown in Figure 4; The 9th step, carry out grid oxygen oxidation technology, at groove cell wall growth one deck grid oxygen 5, carry out the polysilicon deposit, anti-carve polysilicon, form grid polycrystalline silicon 6; In the tenth step, wet etching removes silicon nitride layer 9; Wet etching is removed surface oxide layer 8 then; In the 11 step, deposit one deck electrode metal forms the upper surface metal level 10 that source region 3, grid polycrystalline silicon 6 and tagma 2 provide current potential, and this metal level is as the anode of device; The 12 step, carry out back face metalization, form the lower surface metal layer 11 that drain region 2 and substrate layer 1 provide current potential, this metal level is as the negative electrode of device, and is as shown in Figure 1.
As stated; The super potential barrier rectifier diode examples of implementation that adopt trench MOS structure semiconductor device of the present invention and preparation method to make, when device added reverse biased, tagma 3 formed the PN junction depletion layer with drain region 2 and in tagma 3, expands; When expanding to passive region 7; This moment, passive region 7 was equivalent to the potential dividing ring of device terminal structure, and depletion layer can be walked around passive region 7 and continue to source region 4 expansions, and passive region 7 can improve the reverse breakdown voltage of device; When device adds forward bias; Because of grid polycrystalline silicon has added forward voltage; Thereby make near the P-type conduction material transoid in the tagma 3 of groove avris, form N type electric conducting material, because of between drain region 2 and source region 4, having added N type electric conducting material passive region 7; Therefore reduced the length of transoid electric conducting material in the tagma 3, thus the conducting resistance when having reduced the device forward conduction.Compare with the super potential barrier rectifier diode of tradition; Under the condition of identical reverse breakdown voltage; Can reduce the conducting resistance of device greatly; Perhaps also can be regarded as when under certain current density condition, having identical forward voltage drop, the super barrier rectifier of trench MOS structure semiconductor device of the present invention manufacturing has higher reverse breakdown pressure drop.
Set forth the present invention through above-mentioned instance, also can adopt other instance to realize the present invention simultaneously.The present invention is not limited to above-mentioned instantiation; For example the present invention also can be applicable to combine the MOSFET power device of groove; The present invention adds the passive region of difference tagma electric conducting material between source region and drain region structure also can be applicable in the MOS device of planar structure, so the present invention is limited the accompanying claims scope.
Claims (10)
1. trench MOS structure semiconductor device comprises:
The trench wall growth has passivation layer, is filled with the grid meson in the groove; The whole top of semi-conducting material is provided with the first conductive type semiconductor material tagma between the groove; In bottom, the first conductive type semiconductor material tagma is the second conductive type semiconductor material drain region; Groove avris tagma internal upper part is provided with the second conductive type semiconductor material source region; In groove avris tagma, top, drain region, bottom, source region is provided with the second conductive type semiconductor material passive region.
2. semiconductor device as claimed in claim 1; It is characterized in that: described in groove avris tagma the passive region on top, drain region, bottom, source region can be a plurality of passive regions that are separated from each other; Being vertically set in the groove avris tagma, is the first conductive type semiconductor material tagma between passive region and the passive region.
3. semiconductor device as claimed in claim 1 is characterized in that: be the first conductive type semiconductor material tagma between described source region and the passive region.
4. semiconductor device as claimed in claim 1 is characterized in that: be the first conductive type semiconductor material tagma between described drain region and the passive region.
5. semiconductor device as claimed in claim 1 is characterized in that: filling the grid meson in the described groove is polysilicon.
6. the preparation method of trench MOS structure semiconductor device as claimed in claim 1 is characterized in that: comprise the steps:
1) long on substrate have the semi-conducting material of epitaxial loayer to carry out the tagma diffusion of impurities, and spread propelling, above epitaxial loayer, forms the tagma;
2) form hard mask at silicon chip surface, at the hard mask of trench area surface removal to be formed;
3) carry out the diffusion of second conductive type impurity at formation window;
4) form groove at etching semiconductor material of formation window;
5) inject second conductive type impurity, then annealing;
6) carry out secondarily etched semi-conducting material, form darker groove;
7) at the semiconductor material surface growth of passivation layer of trench wall;
8) carry out the deposit of grid meson polysilicon, polysilicon is returned etching;
9) carry out the corrosion of source region and tagma surface passivation layer;
10) surface deposition metal forms the device anode with source electrode, tagma and grid parallel connection.
7. preparation method as claimed in claim 6 is characterized in that: described tagma diffusion of impurities uses method for implanting to realize.
8. preparation method as claimed in claim 7 is characterized in that: described injection is divided into twice to be carried out, and once injects to advance to forming the tagma, and secondary is injected to the ohmic contact regions that forms the surface, tagma.
9. preparation method as claimed in claim 6 is characterized in that: the etching of described semi-conducting material is a dry etching.
10. preparation method as claimed in claim 6 is characterized in that: the degree of depth of a described etching semiconductor material is less than the junction depth in tagma.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100982247A CN102751314A (en) | 2011-04-19 | 2011-04-19 | Groove mean opinion score (MOS) structure semiconductor device and preparation method thereof |
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| CN2011100982247A CN102751314A (en) | 2011-04-19 | 2011-04-19 | Groove mean opinion score (MOS) structure semiconductor device and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517961A (en) * | 2013-09-29 | 2015-04-15 | 无锡华润上华半导体有限公司 | Rectifier and manufacturing method thereof |
| CN106684134A (en) * | 2015-11-10 | 2017-05-17 | 株洲南车时代电气股份有限公司 | Power semiconductor device and manufacturing method thereof |
-
2011
- 2011-04-19 CN CN2011100982247A patent/CN102751314A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517961A (en) * | 2013-09-29 | 2015-04-15 | 无锡华润上华半导体有限公司 | Rectifier and manufacturing method thereof |
| CN106684134A (en) * | 2015-11-10 | 2017-05-17 | 株洲南车时代电气股份有限公司 | Power semiconductor device and manufacturing method thereof |
| CN106684134B (en) * | 2015-11-10 | 2019-12-27 | 株洲南车时代电气股份有限公司 | Power semiconductor device and manufacturing method thereof |
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Application publication date: 20121024 |