CN103383953A - Passive super-junction groove MOS device and manufacturing method for same - Google Patents
Passive super-junction groove MOS device and manufacturing method for same Download PDFInfo
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- CN103383953A CN103383953A CN 201210148320 CN201210148320A CN103383953A CN 103383953 A CN103383953 A CN 103383953A CN 201210148320 CN201210148320 CN 201210148320 CN 201210148320 A CN201210148320 A CN 201210148320A CN 103383953 A CN103383953 A CN 103383953A
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Abstract
The invention provides a passive super-junction groove MOS device. Through a second passive conduction type semiconductor material area on the lower portion inside a groove, a super-junction structure is guided into a groove MOS structure. The passive super-junction groove MOS device is a base structure for manufacturing a super barrier rectifier and a power MOSFET device, and the invention further provides a manufacturing method for the passive super-junction groove MOS device.
Description
Technical field
The present invention is mainly concerned with a kind of passive super knot groove MOS semiconductor device, semiconductor device of the present invention is the foundation structure of super barrier rectifier and power MOSFET device, the invention still further relates to a kind of manufacturing process of passive super knot groove MOS semiconductor device.
Background technology
Semiconductor device with groove structure and super-junction structure has become the important trend that device develops.For power semiconductor, constantly reduce conducting resistance and become with the requirement that improves constantly current density the important trend that device develops.
Conventional groove MOS device has grid oxygen in the trench wall growth, is filled with polysilicon in groove, and groove avris semi-conducting material sets gradually active area, tagma and drain region.Conducting resistance under the device opening state mainly is subject to the impact of drain region drift layer resistance.
Summary of the invention
The present invention is directed to the problems referred to above and propose, propose a kind of passive super knot groove MOS semiconductor device, it has lower conducting resistance.
A kind of passive super knot groove MOS semiconductor device, it is characterized in that: comprising: substrate layer is semi-conducting material; Drift layer is the semi-conducting material of the first conduction type, is positioned on substrate layer; The tagma is the semi-conducting material of the second conduction type, is positioned on drift layer; A plurality of grooves are arranged in drift layer and tagma; A plurality of passive the second conduction type semiconductor material regions are the semi-conducting material of strip the second conduction type, are positioned at the groove lower inner wall, and are not connected with the tagma; A plurality of MOS structures, insulating barrier are positioned at groove internal upper part inner wall surface, are filled with polycrystalline semiconductor material in groove, and polycrystalline semiconductor material is not connected with passive the second conduction type semiconductor material region, are insulating barrier between it; A plurality of source regions are the semi-conducting material of the first conduction type, face by groove and tagma.
A kind of preparation method of passive super knot groove MOS semiconductor device is characterized in that: the semi-conducting material drift layer that comprises the steps: to form by epitaxial growth the first conduction type on substrate layer; Form passivation layer on the surface, at trench region surface removal passivation layer to be formed; Carry out the second conduction type Impurity Diffusion, then carry out the first conduction type Impurity Diffusion; Carry out the etching semiconductor material, form groove; Form the semi-conducting material of the second conduction type in groove; The semi-conducting material that carries out the second conduction type anti-carves erosion, forms insulating barrier in groove, forms polycrystalline semiconductor material in groove; Form passivation layer, then removal devices surface portion passivation layer at device surface.
A kind of passive super knot groove MOS semiconductor device of the present invention, passive the second conduction type semiconductor material region by bottom in groove is incorporated into super-junction structure in trench MOS structure, compares with traditional groove MOS device, has reduced the conducting resistance of device; When the relative source electrode of device (N-channel MOS) grid connects malleation, tagma groove transoid, break-over of device; When the relative source electrode of device grids connect negative pressure, the groove in drain region can transoid, is of value to the reverse blocking pressure drop that improves device; During the relative source electrode connecting to neutral point of device grids position, passive the second conduction type semiconductor material region and drift layer still can form charge compensation, keep device and have higher reverse blocking pressure drop.
Description of drawings
Fig. 1 is a kind of passive super knot groove MOS semiconductor device generalized section of the present invention;
Fig. 2 is the passive super knot groove MOS semiconductor device generalized section of the second of the present invention.
Wherein,
1, substrate layer;
2, drift layer;
3, tagma;
4, source region;
5, oxide layer;
6, passive P type semiconductor material sections;
7, N-type polycrystalline semiconductor material;
8, silicon nitride.
Embodiment
Fig. 1 shows the schematic cross sectional view of a kind of passive super knot groove MOS semiconductor device of the present invention, describes in detail by semiconductor device of the present invention below in conjunction with Fig. 1 and makes power MOSFET device.
A kind of passive super knot groove MOS semiconductor device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the phosphorus atoms doping content is 1E19cm
-3Drift layer 2 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the phosphorus atoms doping content is 1E16cm
-3, thickness is 38um; Tagma 3 is positioned on drift layer 2, is the semi-conducting material of P conduction type, and the surface in tagma 3 has boron atom heavy doping contact zone, and tagma 3 thickness are 4um; Source region 4 is faced by groove and tagma 3, is the semi-conducting material of phosphorus atoms heavy doping N conduction type, and source region 4 thickness are 1.5um; Oxide layer 5 is the oxide of silicon materials, is positioned at the groove upper inside wall; Passive P type semiconductor material sections 6 is P type single crystal semiconductor silicon materials, is positioned at the groove bottom, and the atom doped concentration of boron is 2E16cm
-3The width of groove is 2um, and the spacing between groove is 4um, and groove runs through whole drift layer 2; N-type polycrystalline semiconductor material 7 is positioned at the groove internal upper part, is the polycrystalline semiconductor material of high concentration impurities doping.
The technique manufacturing process of the present embodiment is as follows:
The first step forms drift layer 2 by epitaxial growth on substrate layer 1;
Second step forms oxide layer 5 in the surface heat oxidation, in trench region surface removal oxide layer 5 to be formed;
The 3rd step, carry out the boron diffusion, form tagma 3, then carry out the phosphorus diffusion, form source region 4;
The 4th step, carry out dry etching, remove semi-conducting material, form groove;
In the 5th step, deposit P type single-crystal semiconductor material, form passive P type semiconductor material sections 6 in groove;
In the 6th step, dry etching is removed part P type single-crystal semiconductor material, forms oxide layer 5 at the groove internal heating oxidation, and deposit forms N-type polycrystalline semiconductor material 7 in groove, carries out N-type polycrystalline semiconductor material 7 and anti-carves erosion;
The 7th step formed passivation layer at device surface, removal devices surface portion passivation layer then, as shown in Figure 1.
Then on this basis, then depositing metal aluminium anti-carve aluminium, for device is drawn source electrode and grid.Be that device is drawn drain electrode by back side metallization technology.
Fig. 2 shows the schematic cross sectional view of the passive super knot groove MOS semiconductor device of the second of the present invention, describes in detail by semiconductor device of the present invention below in conjunction with Fig. 2 and makes power MOSFET device.
A kind of passive super knot groove MOS semiconductor device comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the phosphorus atoms doping content is 1E19cm
-3Drift layer 2 is positioned on substrate layer 1, is the semiconductor silicon material of N conduction type, and the phosphorus atoms doping content is 1E16cm
-3, thickness is 38um; Tagma 3 is positioned on drift layer 2, is the semi-conducting material of P conduction type, and the surface in tagma 3 has boron atom heavy doping contact zone, and tagma 3 thickness are 4um; Source region 4 is faced by groove and tagma 3, is the semi-conducting material of phosphorus atoms heavy doping N conduction type, and source region 4 thickness are 1.5um; Oxide layer 5 is the oxide of silicon materials, is positioned at the groove upper inside wall; Passive P type semiconductor material sections 6 for P type single crystal semiconductor silicon materials, is positioned at the groove lower inner wall, and the atom doped concentration of boron is 2E16cm
-3Silicon nitride 8 is positioned at passive P type semiconductor material sections 6; The width of groove is 2um, and the spacing between groove is 4um, and groove runs through whole drift layer 2; N-type polycrystalline semiconductor material 7 is positioned at the groove internal upper part, is the polycrystalline semiconductor material of high concentration impurities doping.
The technique manufacturing process of the present embodiment is as follows:
The first step forms drift layer 2 by epitaxial growth on substrate layer 1;
Second step forms oxide layer 5 in the surface heat oxidation, in trench region surface removal oxide layer 5 to be formed;
The 3rd step, carry out the boron diffusion, form tagma 3, then carry out the phosphorus diffusion, form source region 4;
The 4th step, carry out dry etching, remove semi-conducting material, form groove;
In the 5th step, deposit P type single-crystal semiconductor material, form passive P type semiconductor material sections 6 in groove, and deposit silicon nitride 8 in groove;
In the 6th step, dry etching is removed part silicon nitride 8 and P type single-crystal semiconductor material, forms oxide layer 5 at the groove internal heating oxidation, and deposit forms N-type polycrystalline semiconductor material 7 in groove, carries out N-type polycrystalline semiconductor material 7 and anti-carves erosion;
The 7th step formed passivation layer at device surface, removal devices surface portion passivation layer then, as shown in Figure 2.
Then on this basis, then depositing metal aluminium anti-carve aluminium, for device is drawn source electrode and grid.Be that device is drawn drain electrode by back side metallization technology.
Set forth the present invention by above-mentioned example, also can adopt other example to realize the present invention simultaneously.The present invention is not limited to above-mentioned instantiation, and for example the present invention also can be applicable to make super barrier rectifier device, so the present invention is by the claims circumscription.
Claims (10)
1. passive super knot groove MOS semiconductor device is characterized in that: comprising:
Substrate layer is semi-conducting material;
Drift layer is the semi-conducting material of the first conduction type, is positioned on substrate layer;
The tagma is the semi-conducting material of the second conduction type, is positioned on drift layer; A plurality of
Groove is arranged in drift layer and tagma; A plurality of
Passive the second conduction type semiconductor material region is the semi-conducting material of strip the second conduction type, is positioned at the groove lower inner wall, and is not connected with the tagma; A plurality of
MOS structure, insulating barrier are positioned at groove internal upper part inner wall surface, are filled with polycrystalline semiconductor material in groove, and polycrystalline semiconductor material is not connected with passive the second conduction type semiconductor material region, are insulating material between it; A plurality of
The source region is the semi-conducting material of the first conduction type, faces by groove and tagma.
2. semiconductor device as claimed in claim 1 is characterized in that: the polycrystalline semiconductor material of filling in described groove, and adulterate for high concentration impurities.
3. semiconductor device as claimed in claim 1 is characterized in that: described passive the second conduction type semiconductor material region is floating dummy status, does not have electrode directly to be connected with it.
4. semiconductor device as claimed in claim 1, it is characterized in that: the semi-conducting material of the second conduction type of the semi-conducting material of the first conduction type of described drift layer and passive the second conduction type semiconductor material region can form super-junction structure, when device connects reverse biased, form charge compensation.
5. semiconductor device as claimed in claim 1 is characterized in that: the polycrystalline semiconductor material of filling in described groove is as the gate electrode of device.
6. semiconductor device as claimed in claim 1 is characterized in that: in described groove, the bottom can be filled the second conduction type semi-conducting material fully.
7. semiconductor device as claimed in claim 1 is characterized in that: in described groove, the bottom can be provided with the second conduction type semi-conducting material by inwall, simultaneously fill insulant in the second conduction type semi-conducting material of bottom in groove.
8. as claimed in claim 1 layer structure, it is characterized in that: the insulating barrier of described trenched side-wall upper face extends to drift layer from device surface.
9. as claimed in claim 1 layer structure, it is characterized in that: the polycrystalline semiconductor material that described groove internal upper part is filled extends to drift layer from device surface.
10. the preparation method of a passive super knot groove MOS semiconductor device, is characterized in that: comprise the steps:
1) form the semi-conducting material drift layer of the first conduction type by epitaxial growth on substrate layer;
2) form passivation layer on the surface, at trench region surface removal passivation layer to be formed;
3) carry out the second conduction type Impurity Diffusion, then carry out the first conduction type Impurity Diffusion;
4) carry out the etching semiconductor material, form groove;
5) form the semi-conducting material of the second conduction type in groove;
6) semi-conducting material that carries out the second conduction type anti-carves erosion, forms insulating barrier in groove, forms polycrystalline semiconductor material in groove;
7) form passivation layer, then removal devices surface portion passivation layer at device surface.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010965A (en) * | 2016-10-30 | 2018-05-08 | 朱江 | A kind of groove MIS semiconductor devices and its manufacture method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010965A (en) * | 2016-10-30 | 2018-05-08 | 朱江 | A kind of groove MIS semiconductor devices and its manufacture method |
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Application publication date: 20131106 |