CN103199119A - Groove schottky semiconductor device with super junction structure and manufacturing method thereof - Google Patents
Groove schottky semiconductor device with super junction structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN103199119A CN103199119A CN2012100063849A CN201210006384A CN103199119A CN 103199119 A CN103199119 A CN 103199119A CN 2012100063849 A CN2012100063849 A CN 2012100063849A CN 201210006384 A CN201210006384 A CN 201210006384A CN 103199119 A CN103199119 A CN 103199119A
- Authority
- CN
- China
- Prior art keywords
- semiconductor material
- groove
- semiconductor device
- conductive
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000463 material Substances 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000003016 pheromone Substances 0.000 abstract 1
- 230000000630 rising effect Effects 0.000 abstract 1
- 239000002210 silicon-based material Substances 0.000 description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a groove schottky semiconductor device with a super junction structure. Charge compensation can be formed by second conductive semiconductor materials located on the lower portions inside grooves and first conductive semiconductor materials among the grooves, then the super junction structure is formed, and reverse breakdown voltages of devices are improved; meanwhile, when a semiconductor device is connected with a certain reverse bias voltage, a metal oxide semiconductor (MOS) structure is constructed by the second conductive semiconductor materials which are doped with metal or high-concentration impurities and arranged on the upper portions inside the grooves and insulating medium located on the side surfaces of the grooves, electric field intensity of drifting materials nearby schottky barrier can be restrained, the pheromone that the barrier height of the schottky barrier is reduced along with rising of the reverse bias voltage is reduced, accordingly reverse leakage current of the devices is reduced, and a reverse blocking characteristic of the devices is improved.
Description
Technical Field
The invention relates to a trench schottky semiconductor device with a super junction structure, and also relates to a preparation method of the trench schottky semiconductor device with the super junction structure.
Background
The power semiconductor device is used in power management and power application in a large number, particularly the semiconductor device with a groove structure becomes an important trend of device development, the schottky device has the advantages of low forward turn-on voltage, high turn-on and turn-off speed and the like, and meanwhile, the schottky device also has the defects of large reverse leakage current, incapability of being applied to a high-voltage environment and the like.
Schottky diodes can be manufactured by a number of different layout techniques, the most common being planar layouts. A typical trench type layout is shown in patent No. 5612567 to B J Baliga. The traditional groove type Schottky diode has an abrupt electric field distribution curve in a drift region, the reverse breakdown characteristic of the device is influenced, and meanwhile the traditional groove type Schottky diode has high on-resistance.
Disclosure of Invention
The present invention is made in view of the above problems, and provides a trench schottky semiconductor device having a super junction structure and a method for manufacturing the same.
A trench Schottky semiconductor device having a super junction structure, characterized in that: the method comprises the following steps: a plurality of grooves are arranged on the surface of the first conductive semiconductor material; an insulating medium is arranged on the surface of the inner wall of the groove; a second conductive semiconductor material is arranged at the lower part in the groove, and a second conductive semiconductor material doped with metal or high-concentration impurities is arranged at the upper part in the groove; the upper part of the first conductive semiconductor material between the grooves is a Schottky barrier junction. Wherein the high concentration impurity doped second conductive material or metal filled in the upper part in the trench is used as a conductive interconnection line, and the upper surface and the lower surface of the semiconductor device are covered with metal, and the upper surface metal connects the anode of the Schottky barrier junction in parallel with the material in the upper part of the trench.
The preparation method of the trench Schottky semiconductor device with the super junction structure comprises the following steps: forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material; carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, and then etching to remove part of the exposed semiconductor material to form a groove; forming an insulating dielectric material on the inner wall of the trench; depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material; depositing a second semiconductor material doped with high-concentration impurities in the groove, and then performing reverse etching on the second semiconductor material; corroding and removing the surface insulating medium; and depositing barrier metal on the surface of the semiconductor material, and sintering to form a Schottky barrier junction.
The other preparation method of the trench Schottky semiconductor device with the super junction structure comprises the following steps: forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material; carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, and then etching to remove part of the exposed semiconductor material to form a groove; forming an insulating dielectric material on the inner wall of the trench; depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material; corroding and removing the insulating medium on the upper surface of the material; depositing barrier metal on the surface of the semiconductor material to form a Schottky barrier junction; depositing metal on the surface.
The third preparation method of the trench schottky semiconductor device with the super junction structure comprises the following steps of: forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material; carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, and then etching to remove part of the exposed semiconductor material to form a groove; forming an insulating dielectric material on the inner wall of the trench; depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material; corroding and removing the insulating medium on the upper surface of the material; and depositing a barrier and electrode metal on the surface of the semiconductor material to form a Schottky barrier junction.
According to the trench Schottky semiconductor device with the super junction structure, when the semiconductor device is connected with a certain reverse bias voltage, the second conductive semiconductor material at the lower part in the trench and the first conductive semiconductor material between the trenches can form charge compensation to form the super junction structure, and the reverse breakdown voltage of a device is improved.
Because of the existence of the super junction structure. Therefore, the impurity doping concentration of the drift region can be improved, the forward on-resistance of the device can be reduced, and the forward on-characteristic of the device is improved.
Meanwhile, when the semiconductor device is connected with a certain reverse bias voltage, the metal or high-concentration impurity doped second conductive semiconductor material arranged at the upper part in the groove and the insulating medium on the side wall of the groove form an MOS structure, so that the electric field intensity of a drift material near a Schottky barrier junction can be inhibited, the phenomenon that the barrier height of the Schottky barrier is reduced along with the rise of the reverse bias voltage is inhibited, the reverse leakage current of the device is reduced, and the reverse blocking characteristic of the device is improved.
According to the preparation method of the groove Schottky semiconductor device with the super junction structure, the production and the manufacture of the device cells can be realized by using two photoetching processes.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench schottky semiconductor device having a super junction structure according to the present invention;
fig. 2 is a schematic cross-sectional view of a trench schottky semiconductor device having a super junction structure according to the present invention;
FIG. 3 is a schematic cross-sectional view of a first step in a process according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a second step of the process of the present invention;
FIG. 5 is a schematic cross-sectional view of a third step in the process of an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a fourth step in the process of an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a fifth step in the process of the first embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a seventh step in the process of the second embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a fifth step in the process of the third embodiment of the present invention.
Wherein,
1. a substrate layer;
2. an N-type semiconductor silicon material;
3. lightly doped P-type semiconductor polysilicon material;
4. thermally oxidizing the oxide layer;
5. heavily doped P-type semiconductor polysilicon material;
6. a Schottky barrier junction;
8. a silicon nitride layer;
9. a barrier metal;
10. an upper surface metal layer;
11. a lower surface metal layer.
Detailed Description
Example 1
Fig. 1 shows a trench schottky semiconductor device having a super junction structure according to the present invention, and the semiconductor device according to the present invention will be described in detail with reference to fig. 1.
A trench schottky semiconductor device having a super junction structure, comprising: the substrate layer 1 is made of N-conductive semiconductor silicon material, and the doping concentration of phosphorus atoms is 1E19/CM3An electrode is led out from the lower surface of the substrate layer 1 through a lower surface metal layer 11; an N-type semiconductor silicon material 2 on the substrate layer 1 and having a doping concentration of 1E16/CM3(ii) a A lightly doped P-type semiconductor polysilicon material 3 at the lower part of the trench and made of P-type semiconductor polysilicon material with boron doping concentration of 1E16/CM3(ii) a Heavily doped P-type semiconductor polysilicon material 5 located at the upper part of the trench and made of P-type semiconductor polysilicon material doped with boron atomsThe impurity concentration is 1E18/CM3(ii) a The thermal oxidation layer 4 is positioned between the N-type semiconductor silicon material 2 and the P-type semiconductor silicon material and is a semiconductor silicon material oxide; the Schottky barrier junction 6 is positioned on the upper surface of the N-type semiconductor silicon material 2 and is a silicide formed by the semiconductor silicon material and barrier metal; an upper surface metal layer 10 is attached to the upper surface of the device to lead out another electrode for the device.
The manufacturing process comprises the following steps:
firstly, depositing silicon nitride on the surface of an N-type semiconductor silicon material 2 with an N-type substrate layer 1 to form a silicon nitride layer 8, as shown in FIG. 3;
secondly, carrying out a photoetching corrosion process, removing part of the silicon nitride layer 8 on the surface of the semiconductor material, and then etching to remove part of the exposed semiconductor silicon material to form a groove, as shown in FIG. 4;
thirdly, performing a thermal oxidation process on the inner wall of the trench to form a thermal oxide layer 4, as shown in fig. 5;
fourthly, depositing a lightly doped P type semiconductor polycrystalline silicon material 3 in the groove, and then performing back etching on the lightly doped P type semiconductor polycrystalline silicon material 3, as shown in FIG. 6;
fifthly, depositing heavily doped P-type semiconductor polycrystalline silicon material 5 in the groove, and then performing back etching on the heavily doped P-type semiconductor polycrystalline silicon material 5, as shown in fig. 7;
sixthly, corroding and removing the silicon nitride layer 8 on the surface;
step seven, depositing barrier metal 9 nickel on the surface of the semiconductor material, sintering to form a Schottky barrier junction 6, and corroding to remove redundant metal nickel;
eighthly, depositing an upper surface metal layer 10 on the surface, and carrying out a photoetching process to remove partial metal on the surface;
in the ninth step, a back metallization process is performed to deposit a bottom metal layer 11 on the back, as shown in fig. 1.
Example 2
Fig. 2 is a trench schottky semiconductor device having a super junction structure according to the present invention, and the semiconductor device according to the present invention will be described in detail with reference to fig. 2.
A trench schottky semiconductor device having a super junction structure, comprising: the substrate layer 1 is made of N-conductive semiconductor silicon material, and the doping concentration of phosphorus atoms is 1E19/CM3An electrode is led out from the lower surface of the substrate layer 1 through a lower surface metal layer 11; an N-type semiconductor silicon material 2 on the substrate layer 1 and having a doping concentration of 1E16/CM3(ii) a A lightly doped P-type semiconductor polysilicon material 3 at the lower part of the trench and made of P-type semiconductor polysilicon material with boron doping concentration of 1E16/CM3(ii) a The thermal oxidation layer 4 is positioned between the N-type semiconductor silicon material 2 and the P-type semiconductor silicon material and is a semiconductor silicon material oxide; the Schottky barrier junction 6 is positioned on the upper surface of the N-type semiconductor silicon material 2 and is a silicide formed by the semiconductor silicon material and barrier metal; an upper surface metal layer 10 is attached to the upper surface of the device, is positioned on the upper part of the groove and the surface of the device, and is used for leading out another electrode for the device.
The manufacturing process comprises the following steps:
firstly, depositing silicon nitride on the surface of an N-type semiconductor silicon material 2 with an N-type substrate layer 1 to form a silicon nitride layer 8, as shown in FIG. 3;
secondly, carrying out a photoetching corrosion process, removing part of the silicon nitride layer 8 on the surface of the semiconductor material, and then etching to remove part of the exposed semiconductor silicon material to form a groove, as shown in FIG. 4;
thirdly, performing a thermal oxidation process on the inner wall of the trench to form a thermal oxide layer 4, as shown in fig. 5;
fourthly, depositing a lightly doped P type semiconductor polycrystalline silicon material 3 in the groove, and then performing back etching on the lightly doped P type semiconductor polycrystalline silicon material 3, as shown in FIG. 6;
fifthly, removing the silicon nitride layer 8 on the surface by corrosion;
sixthly, depositing barrier metal 9 nickel on the surface of the semiconductor material, sintering to form a Schottky barrier junction 6, and corroding to remove redundant metal nickel;
seventhly, depositing an upper surface metal layer 10 on the surface, and performing a photoetching process to remove part of metal on the surface, as shown in fig. 8;
in the eighth step, a back metallization process is performed to deposit a bottom metal layer 11 on the back, as shown in fig. 2.
Example 3
Fig. 2 is a trench schottky semiconductor device having a super junction structure according to the present invention, and the semiconductor device according to the present invention will be described in detail with reference to fig. 2.
A trench schottky semiconductor device having a super junction structure, comprising: the substrate layer 1 is made of N-conductive semiconductor silicon material, and the doping concentration of phosphorus atoms is 1E19/CM3An electrode is led out from the lower surface of the substrate layer 1 through a lower surface metal layer 11; an N-type semiconductor silicon material 2 on the substrate layer 1 and having a doping concentration of 1E16/CM3(ii) a A lightly doped P-type semiconductor polysilicon material 3 at the lower part of the trench and made of P-type semiconductor polysilicon material with boron doping concentration of 1E16/CM3(ii) a The thermal oxidation layer 4 is positioned between the N-type semiconductor silicon material 2 and the P-type semiconductor silicon material and is a semiconductor silicon material oxide; the Schottky barrier junction 6 is positioned on the upper surface of the N-type semiconductor silicon material 2 and is a silicide formed by the semiconductor silicon material and barrier metal; an upper surface metal layer 10 is attached to the upper surface of the device, is positioned on the upper part of the groove and the surface of the device, and is used for leading out another electrode for the device.
The manufacturing process comprises the following steps:
firstly, depositing silicon nitride on the surface of an N-type semiconductor silicon material 2 with an N-type substrate layer 1 to form a silicon nitride layer 8, as shown in FIG. 3;
secondly, a photoetching process is carried out, part of the silicon nitride layer 8 is removed from the surface of the semiconductor material,
then etching to remove part of the exposed semiconductor silicon material to form a trench, as shown in FIG. 4;
thirdly, performing a thermal oxidation process on the inner wall of the trench to form a thermal oxide layer 4, as shown in fig. 5;
fourthly, depositing a lightly doped P type semiconductor polycrystalline silicon material 3 in the groove, and then performing back etching on the lightly doped P type semiconductor polycrystalline silicon material 3, as shown in FIG. 6;
fifthly, etching to remove the surface silicon nitride layer 8, as shown in fig. 9;
sixthly, depositing an upper surface metal layer 10 on the surface, and carrying out a photoetching process to remove partial metal on the surface to form a Schottky barrier junction 6;
seventhly, a back metallization process is performed to deposit a bottom metal layer 11 on the back, as shown in fig. 2.
While the invention has been illustrated by the above examples, it will be understood that the invention may be practiced in other examples that depart from the specific details disclosed herein, and that the invention is therefore intended to be limited only by the scope of the appended claims.
Claims (11)
1. A trench Schottky semiconductor device having a super junction structure, characterized in that: the method comprises the following steps:
a plurality of grooves are arranged on the surface of the first conductive semiconductor material;
an insulating medium is arranged on the surface of the inner wall of the groove;
a second conductive semiconductor material is arranged at the lower part in the groove, and a second conductive semiconductor material doped with metal or high-concentration impurities is arranged at the upper part in the groove;
the upper part of the first conductive semiconductor material between the grooves is a Schottky barrier junction.
2. The semiconductor device according to claim 1, wherein: the insulating dielectric layer may be silicon dioxide.
3. The semiconductor device according to claim 1, wherein: the second conductive semiconductor material filled in the lower part in the groove is a polycrystalline semiconductor material with a certain impurity concentration.
4. The semiconductor device according to claim 1, wherein: the second conductive semiconductor material doped with high-concentration impurities filled in the upper part in the groove is a polycrystalline semiconductor material doped with high-concentration impurities.
5. The semiconductor device according to claim 1, wherein: the high-concentration impurity-doped second conductive material filled in the upper part of the groove is used as a conductive interconnecting wire.
6. The semiconductor device according to claim 1, wherein: the metal filled in the upper part of the groove can be electrode metal.
7. The semiconductor device according to claim 1, wherein: the upper and lower surfaces of the semiconductor device may be covered with a metal, the metal of the upper surface connecting the anode of the schottky barrier junction in parallel with the material of the upper portion of the trench.
8. The semiconductor device according to claim 1, wherein: when the semiconductor device is connected with a certain reverse bias voltage, the second conductive semiconductor material at the lower part in the groove and the first conductive semiconductor material between the grooves can form charge compensation to form a super junction structure.
9. The method for manufacturing a trench schottky semiconductor device having a super junction structure according to claim 1, wherein: the method comprises the following steps:
1) forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material;
2) carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, then etching, and removing part of the exposed semiconductor material to form a groove;
3) forming an insulating dielectric material on the inner wall of the trench;
4) depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material;
5) depositing a second semiconductor material doped with high-concentration impurities in the groove, and then performing reverse etching on the second semiconductor material;
6) corroding and removing the surface insulating medium;
7) and depositing barrier metal on the surface of the semiconductor material to form a Schottky barrier junction.
10. The method for manufacturing a trench schottky semiconductor device having a super junction structure according to claim 1, wherein: the method comprises the following steps:
1) forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material;
2) carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, then etching, and removing part of the exposed semiconductor material to form a groove;
3) forming an insulating dielectric material on the inner wall of the trench;
4) depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material;
5) corroding and removing the insulating medium on the upper surface of the material;
6) depositing barrier metal on the surface of the semiconductor material to form a Schottky barrier junction;
7) depositing metal on the surface.
11. The method for manufacturing a trench schottky semiconductor device having a super junction structure according to claim 1, wherein: the method comprises the following steps:
1) forming an insulating dielectric material on the surface of the drift layer of the first conductive semiconductor material on the substrate of the first conductive semiconductor material;
2) carrying out photoetching corrosion process, removing part of the insulating medium material on the surface of the semiconductor material, then etching, and removing part of the exposed semiconductor material to form a groove;
3) forming an insulating dielectric material on the inner wall of the trench;
4) depositing a second semiconductor material in the groove, and then performing reverse etching on the second semiconductor material;
5) corroding and removing the insulating medium on the upper surface of the material;
6) and depositing a barrier and electrode metal on the surface of the semiconductor material to form a Schottky barrier junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210006384.9A CN103199119B (en) | 2012-01-06 | 2012-01-06 | Groove schottky semiconductor device with super junction structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210006384.9A CN103199119B (en) | 2012-01-06 | 2012-01-06 | Groove schottky semiconductor device with super junction structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103199119A true CN103199119A (en) | 2013-07-10 |
| CN103199119B CN103199119B (en) | 2017-05-17 |
Family
ID=48721562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210006384.9A Active CN103199119B (en) | 2012-01-06 | 2012-01-06 | Groove schottky semiconductor device with super junction structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103199119B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024915A (en) * | 2016-07-25 | 2016-10-12 | 电子科技大学 | Super-junction Schottky diode |
| CN106158659A (en) * | 2015-04-23 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of the cushion of superjunction power tube and superjunction power tube |
| CN106298976A (en) * | 2016-08-08 | 2017-01-04 | 电子科技大学 | A kind of groove-shaped Schottky diode |
| CN106328718A (en) * | 2016-11-04 | 2017-01-11 | 四川洪芯微科技有限公司 | Mesa diode |
| CN107256886A (en) * | 2017-07-12 | 2017-10-17 | 付妮娜 | Groove-type Schottky diode and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6590240B1 (en) * | 1999-07-28 | 2003-07-08 | Stmicroelectronics S.A. | Method of manufacturing unipolar components |
| CN101189710A (en) * | 2005-04-22 | 2008-05-28 | 艾斯莫斯技术公司 | Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches |
| US20090032897A1 (en) * | 2004-12-10 | 2009-02-05 | Robert Bosch Gmbh | Semiconductor Device and Method for Its Manufacture |
| CN101803032A (en) * | 2007-09-21 | 2010-08-11 | 罗伯特·博世有限公司 | Semiconductor device and method for its manufacture |
| CN102222701A (en) * | 2011-06-23 | 2011-10-19 | 哈尔滨工程大学 | Schottky device with groove structure |
-
2012
- 2012-01-06 CN CN201210006384.9A patent/CN103199119B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6590240B1 (en) * | 1999-07-28 | 2003-07-08 | Stmicroelectronics S.A. | Method of manufacturing unipolar components |
| US20090032897A1 (en) * | 2004-12-10 | 2009-02-05 | Robert Bosch Gmbh | Semiconductor Device and Method for Its Manufacture |
| CN101189710A (en) * | 2005-04-22 | 2008-05-28 | 艾斯莫斯技术公司 | Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches |
| CN101803032A (en) * | 2007-09-21 | 2010-08-11 | 罗伯特·博世有限公司 | Semiconductor device and method for its manufacture |
| CN102222701A (en) * | 2011-06-23 | 2011-10-19 | 哈尔滨工程大学 | Schottky device with groove structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158659A (en) * | 2015-04-23 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of the cushion of superjunction power tube and superjunction power tube |
| CN106024915A (en) * | 2016-07-25 | 2016-10-12 | 电子科技大学 | Super-junction Schottky diode |
| CN106024915B (en) * | 2016-07-25 | 2019-01-01 | 电子科技大学 | A kind of super junction Schottky diode |
| CN106298976A (en) * | 2016-08-08 | 2017-01-04 | 电子科技大学 | A kind of groove-shaped Schottky diode |
| CN106298976B (en) * | 2016-08-08 | 2019-03-01 | 电子科技大学 | A kind of groove-shaped Schottky diode |
| CN106328718A (en) * | 2016-11-04 | 2017-01-11 | 四川洪芯微科技有限公司 | Mesa diode |
| CN107256886A (en) * | 2017-07-12 | 2017-10-17 | 付妮娜 | Groove-type Schottky diode and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103199119B (en) | 2017-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103137710B (en) | A kind of groove Schottky semiconductor device with multiple insulator separation and preparation method thereof | |
| CN103199119B (en) | Groove schottky semiconductor device with super junction structure and manufacturing method thereof | |
| CN103545381B (en) | A kind of horizontal structure groove Schottky semiconductor device and preparation method thereof | |
| CN103378171B (en) | A kind of groove Schottky semiconductor device and preparation method thereof | |
| CN103367396B (en) | Super junction Schottky semiconductor device and preparation method thereof | |
| CN103247694A (en) | Groove Schottky semiconductor device and manufacturing method thereof | |
| CN103515450B (en) | Groove charge compensation Schottky semiconductor device and manufacturing method thereof | |
| CN103367462A (en) | Schottky semiconductor device with insulating layer isolated super-junction structure and preparation method for Schottky semiconductor device | |
| CN103378178B (en) | Schottky semiconductor device with groove structures and preparation method thereof | |
| CN103515449B (en) | One kind has charge compensation groove Schottky semiconductor device and preparation method thereof | |
| CN103199102A (en) | Schottky semiconductor device with super junction structure and manufacturing method thereof | |
| CN103390651B (en) | Groove schottky semiconductor device and manufacturing method thereof | |
| CN103137711A (en) | Schottky semiconductor device with insulating layer isolation structure and preparation method thereof | |
| CN103378177B (en) | Schottky semiconductor device with grooves and preparation method thereof | |
| CN103378170A (en) | Schottky semiconductor device with super junction and preparation method thereof | |
| CN103579371A (en) | Channel terminal structure Schottky device and manufacturing method thereof | |
| CN103378172B (en) | Schottky semiconductor device and method for preparing same | |
| CN103489895B (en) | A kind of trench super junction semiconductor device | |
| CN103383968A (en) | Interface charge compensation Schottky semiconductor device and manufacturing method for same | |
| CN103579370B (en) | A kind of charge compensation semiconductor junction device with stoicheiometry mismatch insulating materials | |
| CN103390635B (en) | One kind has passive metal PN junction semiconductor device and preparation method thereof | |
| CN103378131A (en) | Charge compensation Schottky semiconductor device and manufacturing method thereof | |
| CN103378176B (en) | One kind has charge compensation Schottky semiconductor device and its manufacture method | |
| CN103367438B (en) | A kind of semiconductor device of metal semiconductor charge compensation and preparation method thereof | |
| CN103390652B (en) | Groove charge compensation schottky semiconductor device and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20170424 Address after: 310027 Hangzhou, Zhejiang Province, Xihu District, Zhejiang Road, No. 38, No. Applicant after: Sheng Kuang Address before: 113200 Liaoning Province Xinbin Manchu Autonomous County Federation of disabled persons Applicant before: Zhu Jiang Applicant before: Sheng Kuang |
|
| TA01 | Transfer of patent application right | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211228 Address after: 310000 Yuhang Tang Road, Xihu District, Hangzhou, Zhejiang 866 Patentee after: ZHEJIANG University Address before: 310027 No. 38, Zhejiang Road, Hangzhou, Zhejiang, Xihu District Patentee before: Sheng Kuang |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230322 Address after: 312000 No. 518, Linjiang Road, Gaobu street, Yuecheng District, Shaoxing City, Zhejiang Province Patentee after: Shaoxing SMIC integrated circuit manufacturing Co.,Ltd. Address before: 310000 Yuhang Tang Road, Xihu District, Hangzhou, Zhejiang 866 Patentee before: ZHEJIANG University |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20231225 Address after: Room 203-18, Building 1, No. 1433 Renmin East Road, Gaobu Street, Yuecheng District, Shaoxing City, Zhejiang Province, 312035 Patentee after: Xinlian Power Technology (Shaoxing) Co.,Ltd. Address before: 312000 No. 518, Linjiang Road, Gaobu street, Yuecheng District, Shaoxing City, Zhejiang Province Patentee before: Shaoxing SMIC integrated circuit manufacturing Co.,Ltd. |
|
| TR01 | Transfer of patent right |