CN103367433B - A kind of groove super junction MOS device and its manufacture method - Google Patents
A kind of groove super junction MOS device and its manufacture method Download PDFInfo
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- CN103367433B CN103367433B CN201210106239.8A CN201210106239A CN103367433B CN 103367433 B CN103367433 B CN 103367433B CN 201210106239 A CN201210106239 A CN 201210106239A CN 103367433 B CN103367433 B CN 103367433B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 239000000463 material Substances 0.000 claims description 49
- 210000000746 body region Anatomy 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000002210 silicon-based material Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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Abstract
Present invention relates generally to a kind of groove super junction MOS device, and be incorporated into super-junction structure in semiconductor device by grid and PN junction, the trench MOS structure semiconductor device of the present invention is super barrier rectifier and power MOSFET foundation structures, and the invention further relates to a kind of manufacturing process of groove super junction MOS device.
Description
Technical Field
The invention mainly relates to a trench super junction MOS semiconductor device, and introduces a super junction structure into the semiconductor device.
Background
Semiconductor devices having trench structures and super junction structures have become an important trend in device development. For power semiconductor devices, the requirements of continuously decreasing on-resistance and continuously increasing current density become important trends in device development.
In the traditional groove MOS device, gate oxide grows on the inner wall of a groove, polycrystalline silicon is filled in the groove, and a source region, a body region and a drain region are sequentially arranged on a semiconductor material on the side of the groove. The on-resistance of the device in the on state is mainly influenced by the resistance of the drain region drift layer.
Disclosure of Invention
The invention provides a trench super junction MOS semiconductor device, which introduces a super junction structure into a device through a grid.
A trench super junction MOS semiconductor device, characterized in that: the method comprises the following steps: the substrate layer is made of semiconductor materials; the drift layer is made of semiconductor materials of the first conduction type and is positioned on the substrate layer; a body region of a semiconductor material of a second conductivity type located over the drift layer; the plurality of grooves are positioned in the drift layer and the body region, the surface of the inner wall of each groove is provided with an insulating layer, meanwhile, the upper part in each groove is filled with a semiconductor material of a first conduction type, and the lower part in each groove is filled with a semiconductor material of a second conduction type; a plurality of source regions, which are semiconductor material of the first conductivity type, are adjacent to the trenches and the body regions. The semiconductor material of the first conductivity type filled in the trench may be a polycrystalline semiconductor material and is doped with high-concentration impurities to serve as a gate electrode of the device.
A method for manufacturing a trench super junction MOS semiconductor device is characterized in that: the method comprises the following steps: forming a semiconductor material drift layer of a first conduction type on the substrate layer through epitaxial production; forming a passivation layer on the surface, and removing the passivation layer on the surface of the region where the groove is to be formed; performing second conduction type impurity diffusion, and then performing first conduction type impurity diffusion; etching the semiconductor material to form a groove; forming an insulating layer on the inner wall of the groove, then forming a semiconductor material of a second conduction type in the groove, and carrying out back etching on the semiconductor material of the second conduction type; forming a semiconductor material of a first conduction type in the groove, and then performing reverse etching on the semiconductor material of the first conduction type; and forming a passivation layer on the surface of the device, and then removing part of the passivation layer on the surface of the device.
According to the trench super junction MOS semiconductor device, the super junction structure is introduced into the trench MOS structure through the grid and the PN junction, and compared with a traditional trench MOS device, the on-resistance of the device is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a trench super junction MOS semiconductor device according to the present invention;
wherein,
1. a substrate layer;
2. a drift layer;
3. a body region;
4. a source region;
5. an oxide layer;
6. a P-type single crystal semiconductor material;
7. an N-type polycrystalline semiconductor material.
Detailed Description
Example 1
Fig. 1 shows a schematic cross-sectional view of a trench super junction MOS semiconductor device of the present invention, and the fabrication of a power MOSFET device by a trench super junction MOS semiconductor device of the present invention will be described in detail with reference to fig. 1.
A trench super junction MOS semiconductor device comprising: the substrate layer 1 is N conductive semiconductor silicon material with phosphorus atom doping concentration of 1E19cm-3(ii) a A drift layer 2, which is located on the substrate layer 1 and is made of N-conductive semiconductor silicon material and doped with phosphorus atoms at a concentration of 1E16cm-3The thickness is 38 um; the body region 3 is located on the drift layer 2 and is made of P-type semiconductor materials, a boron atom heavily-doped contact region is arranged on the surface of the body region 3, and the thickness of the body region 3 is 4 microns; the source region 4 is adjacent to the groove and the body region 3 and is made of a phosphorus atom heavily doped N conduction type semiconductor material, and the thickness of the source region 4 is 1.5 um; the oxide layer 5 is an oxide of a silicon material and is positioned on the inner wall of the groove; the P-type single crystal semiconductor material 6 is P-type single crystal semiconductor silicon material and is located in the trench, and the doping concentration of boron atoms is 2E16cm-3(ii) a The width of the grooves is 2um, and the grooves are arranged between the groovesThe distance is 4um, and the groove penetrates through the whole drift layer 2; the N-type polycrystalline semiconductor material 7 is a polycrystalline semiconductor material doped with high concentration impurities and located above the P-type single crystal semiconductor material 6.
The process flow of the embodiment is as follows:
firstly, forming a drift layer 2 on a substrate layer 1 through epitaxial production;
secondly, thermally oxidizing the surface to form an oxide layer 5, and removing the oxide layer 5 from the surface of the region to be formed with the groove;
thirdly, performing boron diffusion to form a body region 3, and then performing phosphorus diffusion to form a source region 4;
fourthly, carrying out dry etching to remove the semiconductor material and form a groove;
fifthly, forming an oxide layer 5 on the inner wall of the groove through a thermal oxidation process, depositing a P-type monocrystalline semiconductor material 6 in the groove, and performing reverse etching on the P-type monocrystalline semiconductor material 6;
sixthly, depositing and forming an N-type polycrystalline semiconductor material 7 in the groove, and performing reverse etching on the N-type polycrystalline semiconductor material 7;
and seventhly, forming a passivation layer on the surface of the device, and then removing part of the passivation layer on the surface of the device, as shown in fig. 1.
And then depositing metal aluminum on the basis, and then reversely etching the aluminum to lead out a source electrode and a grid electrode for the device. And leading out the drain electrode for the device through a back metallization process.
As described above, when a reverse bias voltage is applied to the device, the gate potential is equivalent to the source, so the drift layer 2 and the P-type single crystal semiconductor material 6 can form a super junction structure, charge compensation is generated, the electric field is relatively uniformly distributed, that is, high-concentration impurity doping of the drift layer 2 can be realized, and the on-resistance of the device is greatly reduced.
The invention is illustrated by the two examples above, while other examples may be used to implement the invention. The present invention is not limited to the above specific examples, and for example, the present invention is also applicable to a super barrier rectifier. The invention is therefore defined by the scope of the appended claims.
Claims (5)
1. A trench super junction MOS semiconductor device, characterized in that: the method comprises the following steps:
the substrate layer is made of semiconductor materials;
the drift layer is made of semiconductor materials of the first conduction type and is positioned on the substrate layer;
a body region of a semiconductor material of a second conductivity type located over the drift layer; a plurality of
The trench is positioned in the drift layer and the body region, an insulating layer is arranged on the surface of the whole inner wall of the trench, meanwhile, the whole upper part in the trench is filled with a semiconductor material of a first conduction type, a polycrystalline semiconductor material doped with high-concentration impurities is used as a gate electrode, the lower part in the trench is filled with a semiconductor material of a second conduction type, the semiconductor material of the second conduction type filled at the lower part in the trench is not connected with the drift layer and the substrate layer, and the semiconductor material of the first conduction type of the polycrystal at the upper part in the trench is connected with the semiconductor material of the second conduction type at the lower part; a plurality of
A source region, which is a semiconductor material of a first conductivity type, is adjacent to the trench and the body region.
2. The semiconductor device according to claim 1, wherein: the semiconductor material filled in the groove and having the second conduction type is polycrystalline semiconductor material and is doped with low-concentration impurities.
3. The semiconductor device according to claim 1, wherein: the semiconductor material filled in the groove and having the second conduction type is a single crystal semiconductor material and is doped with low-concentration impurities.
4. The semiconductor device according to claim 1, wherein: and when the device is connected with a reverse bias voltage, charge compensation is formed, so that the electric field is relatively uniformly distributed.
5. A method for manufacturing a trench super junction MOS semiconductor device is characterized in that: the method comprises the following steps:
1) forming a semiconductor material drift layer of a first conduction type on the substrate layer through epitaxial production;
2) forming a passivation layer on the surface, and removing the passivation layer on the surface of the region where the groove is to be formed;
3) performing second conduction type impurity diffusion, and then performing first conduction type impurity diffusion;
4) etching the semiconductor material to form a groove;
5) forming an insulating layer on the whole inner wall of the groove, then forming a semiconductor material of a second conduction type in the groove, and carrying out back etching on the semiconductor material of the second conduction type;
6) forming a polycrystalline semiconductor material of the first conductivity type in the groove, and then performing reverse etching on the polycrystalline semiconductor material of the first conductivity type;
7) and forming a passivation layer on the surface of the device, and then removing part of the passivation layer on the surface of the device.
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| CN201210106239.8A CN103367433B (en) | 2012-04-02 | 2012-04-02 | A kind of groove super junction MOS device and its manufacture method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101019235A (en) * | 2004-09-03 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | Vertical semiconductor devices and methods of manufacturing such devices |
| CN101667579A (en) * | 2008-08-20 | 2010-03-10 | 万国半导体股份有限公司 | Configurations and methods for manufacturing charge balanced devices |
| CN103137689A (en) * | 2011-11-25 | 2013-06-05 | 盛况 | Semiconductor device with super junction ditch groove metal oxide semiconductor (MOS) structure and manufacture method thereof |
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| JP2010192691A (en) * | 2009-02-18 | 2010-09-02 | Rohm Co Ltd | Semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101019235A (en) * | 2004-09-03 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | Vertical semiconductor devices and methods of manufacturing such devices |
| CN101667579A (en) * | 2008-08-20 | 2010-03-10 | 万国半导体股份有限公司 | Configurations and methods for manufacturing charge balanced devices |
| CN103137689A (en) * | 2011-11-25 | 2013-06-05 | 盛况 | Semiconductor device with super junction ditch groove metal oxide semiconductor (MOS) structure and manufacture method thereof |
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Effective date of registration: 20210426 Address after: Room 301, 3rd floor, building 16, Guangxi Huike Technology Co., Ltd., No. 336, East extension of Beihai Avenue, Beihai Industrial Park, 536000, Guangxi Zhuang Autonomous Region Patentee after: Beihai Huike Semiconductor Technology Co.,Ltd. Address before: 113200 Liaoning Province Xinbin Xinbin Manchu Autonomous County town Yan Water Street No. 6, the Federation of the disabled Patentee before: Zhu Jiang |