CN104900703A - Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof - Google Patents
Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof Download PDFInfo
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- CN104900703A CN104900703A CN201510238897.6A CN201510238897A CN104900703A CN 104900703 A CN104900703 A CN 104900703A CN 201510238897 A CN201510238897 A CN 201510238897A CN 104900703 A CN104900703 A CN 104900703A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000000034 method Methods 0.000 title abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 241000446313 Lamella Species 0.000 claims description 25
- 239000011248 coating agent Substances 0.000 claims description 23
- 238000000576 coating method Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 210000002421 cell wall Anatomy 0.000 claims description 16
- 238000002360 preparation method Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 89
- 230000005684 electric field Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000009826 distribution Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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Abstract
The present invention discloses a trench MOSFET terminal structure which comprises a first conductive type substrate, a first conductive type epitaxial sheet layer which is arranged at one side of the first conductive type substrate, and a plurality of first voltage divider areas which comprise a plurality of first trenches. A first oxide layer is deposited at the walls and the bottoms of the first trenches respectively, the first trenches are internally provided with polysilicon layers which are deposited at the walls of the first trenches, and second conductive type implanted layers are arranged at the two sides of the first trenches and under the first trenches in the first conductive type epitaxial sheet layer. The trench MOSFET terminal structure also comprises a plurality of second voltage divider areas which comprise a plurality of second trenches. A first oxide layer is deposited at the walls and the bottoms of the second trenches respectively, and polysilicon layers are deposited in the second trenches. The invention also discloses a trench MOSFET device and a manufacture method thereof. The area of a chip is reduced, and the production cost is reduced.
Description
Technical field
The present invention relates to a kind of terminal structure, more precisely a kind of groove MOSFET terminal structure, the invention also discloses a kind of groove MOSFET terminal part and preparation method thereof.
Background technology
Along with the continuous maturation of power MOS (Metal Oxide Semiconductor) device technique and design, the competition of domestic and international power MOS (Metal Oxide Semiconductor) device is also more and more fierce, reduces the cost of device, the performance improving device and reliability also more and more urgent.Under the prerequisite not affecting device performance, the photoetching number of times reduced in device fabrication is reduce by two important means of device cost with the size reducing chip.
As shown in figure 14, it is the reverse withstand voltage emulation schematic diagram of the groove type power MOS device of the manufacture method manufacture of the trench semiconductor power device of prior art, the distribution of its depletion layer and analysis of electric field is observed by sunykatuib analysis, can see, second conductivity type regions of two points of peripheral first channel bottoms of nip only has fraction region depletion, and its equipotential line is also more loose, electric field strength is very low, and the withstand voltage effect in end ring is very little; Therefore in this region, adopting large scale groove, is waste chip area completely.
Summary of the invention
The object of this invention is to provide a kind of groove MOSFET terminal structure and groove MOSFET device and preparation method thereof, it is inadequate that it can solve the chip area utilance of depositing in prior art, the shortcoming of high cost.
The present invention is by the following technical solutions:
A kind of groove MOSFET terminal structure, comprising:
One first conduction type substrate;
One first conduction type extension lamella, it is located at the side of described first conduction type substrate;
Some first point of nips, it comprises some first grooves, the cell wall of described first groove and bottom land are all deposited with one first oxide skin(coating), and described first trench interiors is provided with polysilicon layer, and described polysilicon layer is deposited on the cell wall of described first groove, the both sides of the first groove and below are provided with the second conduction type implanted layer in described first conduction type epitaxial wafer;
Some second point of nips, it comprises some second grooves, and the cell wall of described second groove and bottom land are all deposited with one first oxide skin(coating), and is deposited with polysilicon layer in described second groove.
Also comprise a cut-off region, it comprises:
One second groove, it is located in described first conductive type epitaxial layer, and the cell wall of described second groove and bottom land are all deposited with one first oxide skin(coating), and is deposited with polysilicon layer in described second groove;
Also comprise one first conduction type implanted layer, it is located in described second conduction type implanted layer, and is in the edge of described second conduction type implanted layer.
Contact hole, and inject the second conductive type impurity in described contact hole, it is located at the first groove and the second conduction type implanted layer is inner, and the contact hole be located in the second conduction type implanted layer contacts with described first conduction type implanted layer;
One second oxide skin(coating), it establishes the first oxide skin(coating) and and the outside of the second groove;
One second metal level, it is located at the outside of the second oxide skin(coating), and the second metal level is connected with contact hole.
The width of described first groove is greater than the width of described second groove.
The width of described first groove is more than or equal to 2um.
A groove MOSFET device containing above-mentioned groove MOSFET terminal structure, also comprise a drain region electrode, it is located at the opposite side of described first conduction type substrate.
Also comprise:
One source pole electrode, it is connected with channel region with the source region in the first conduction type extension lamella by contact hole;
One gate electrode, it is connected with the polysilicon of the second groove in source region by contact hole;
A preparation method for groove MOSFET device, comprises the following steps:
First conduction type substrate layer grows the first conduction type extension lamella of homotype doping;
First conduction type extension lamella carries out etching groove, forms the first groove and the second groove;
The first oxide layer is grown as grid oxygen in the first groove and the second groove;
Depositing polysilicon in the first oxide layer, and etch, the second groove is all filled full, and the cell wall of the first groove is deposited with polysilicon;
The second conductive type impurity ion is injected at the first conduction type extension lamella and the first trench interiors, form the second conduction type implanted layer by heat treatment, and the second conduction type implanted layer is located at the upper surface of described first conductive type epitaxial layer and the below of the second groove;
The surface of the first conductivity type epitaxial layer makes by lithography the injection zone of the first conductive type impurity, and injects the first conductive type impurity ion, form the first conduction type implanted layer by heat treatment;
Deposit one second oxide skin(coating), forms a dielectric layer;
Contact hole photoetching and etching, contact hole and source region and channel region contacts,
Deposit the 3rd metal level, and carry out photoetching formation source electrode, grid and cut-off region;
Preparation drain region electrode.
Also comprise:
At the surface deposition one trioxide layer of the first conduction type extension lamella;
Photoetching, etching are carried out to trioxide layer, forms etching window and the masking layer of the first groove and the second groove.
Trioxide layer is removed.
Advantage of the present invention is: comprise several first groove in first point of nip, because the first groove is not filled completely by polysilicon, so when channel region is injected, second conductive type impurity can be injected into beneath trenches, form the second conduction type implanted layer, when draining high potential, the second conduction type implanted layer can exhaust completely, and depletion layer is expanded to the first conductive type epitaxial layer depths; Second point of nip comprises several small size groove, because Electric Field Distribution most of in end ring is at the channel bottom near source region, the electric field in second point of nip obviously reduces, and the second groove in second point of nip is changed to small size groove, decrease chip area, reduce production cost.
Accompanying drawing explanation
Below in conjunction with embodiment and accompanying drawing, the present invention is described in detail, wherein:
Fig. 1 is the structural representation of groove MOSFET terminal structure of the present invention.
Fig. 2 to Figure 13 is the structural representation preparing intermediate of groove MOSFET device of the present invention.
Figure 14 is the reverse withstand voltage emulation schematic diagram of the groove type power MOS device that the manufacture method of the trench semiconductor power device of prior art manufactures.
Embodiment
The specific embodiment of the present invention is set forth further below in conjunction with accompanying drawing:
As shown in Figure 1, a kind of groove MOSFET terminal structure, comprises the first conduction type substrate 1, one first conduction type extension lamella 2, some first point of nips 3, some second point of nips 4 and a cut-off region 5.One the second nip is as pressure ring, and most of Electric Field Distribution is at first point of nip, and second point of nip improves withstand voltage by the second groove further, simultaneously saving chip area; Device reliability, by equipotential design, is improved in cut-off region.
First conduction type extension lamella 2 is located at the side of the first conduction type substrate 1.First point of nip comprises some first grooves 7, cell wall and the bottom land of described first groove 7 are all deposited with one first oxide skin(coating) 11, and described first groove 7 inside is provided with polysilicon layer 12, and described polysilicon layer 12 is deposited on the cell wall of described first groove 7, the both sides of the first groove 7 and below are provided with the second conduction type implanted layer 9 in described first conduction type epitaxial wafer 2.Second point of nip comprises some second grooves 8, and cell wall and the bottom land of described second groove 8 are all deposited with one first oxide skin(coating) 11, and are deposited with polysilicon layer 12 in described second groove 8.
The present invention also comprises one first conduction type implanted layer 10, and it is located in described second conduction type implanted layer 9, and is in the edge of described second conduction type implanted layer 9.
Cut-off region 5 comprises: one second groove 8, contact hole 13,1 second oxide skin(coating) 6 and one second metal level 15.Second groove 8 its be located in described first conductive type epitaxial layer 2, and the cell wall of described second groove 8 and bottom land are all deposited with one first oxide skin(coating) 11, and are deposited with polysilicon layer 12 in described second groove, and polysilicon layer 12 is full by the second trench fill.Inject the second conductive type impurity in contact hole 13, it is located at the second groove 8 and the second conduction type implanted layer 9 is inner, and the contact hole 13 be located in the second conduction type implanted layer 9 contacts with described first conduction type implanted layer 10.Second oxide skin(coating) 6 establishes the first oxide skin(coating) 11 and and the outside of the second groove 8.Second metal level 15 is located at the outside of the second oxide skin(coating) 6, and the second metal level 6 is connected with contact hole 13.
In the present invention, the width of the first groove is greater than the width of described second groove, and the width of the first groove is more than or equal to 2um.
The invention also discloses a kind of trench semiconductor power device, it comprises above-mentioned groove MOSFET terminal structure and also comprises a drain region electrode, one source pole electrode and a gate electrode, and drain region electrode is located at the opposite side of described first conduction type substrate.Source electrode is connected with channel region with the source region in the first conduction type extension lamella by contact hole; Gate electrode is connected by the polysilicon of contact hole with source region second groove; Terminal structure comprises one first point of nip, one second point of nip and a cut-off region.
The invention discloses a kind of preparation method of groove MOSFET semiconductor power device, comprise the following steps:
First conduction type substrate layer grows the first conduction type extension lamella of homotype doping;
First conduction type extension lamella carries out etching groove, forms the first groove and the second groove;
The first oxide layer is grown as grid oxygen in the first groove and the second groove;
At depositing polysilicon, and the second groove is all filled full, and the cell wall of the first groove is deposited with polysilicon;
The second conductive type impurity ion is injected at the first conduction type extension lamella and the first trench interiors, form the second conduction type implanted layer by heat treatment, and the second conduction type implanted layer is located at the upper surface of described first conductive type epitaxial layer and the below of the first groove;
The surface of the first conductivity type epitaxial layer makes by lithography the injection zone of the first conductive type impurity, and injects the first conductive type impurity ion, form the first conduction type implanted layer by heat treatment;
Deposit one second oxide skin(coating), forms a dielectric layer;
Contact hole photoetching and etching, contact hole and source region and channel region contacts;
Deposit the 3rd metal level, and carry out photoetching formation source electrode, grid and cut-off region;
Preparation drain region electrode.
As shown in Fig. 2 to 13, it is the schematic diagram of the embodiment of the preparation method of a kind of groove MOSFET semiconductor power device of the present invention, comprises the following steps:
As shown in Figure 2, the first conduction type substrate layer 1 grows the first conduction type extension lamella 2 of homotype doping; First conduction type substrate layer grows the first conduction type extension lamella of homotype doping, and the doping content of the first conduction type extension lamella and thickness directly can affect the puncture voltage of MOSFET element.
As shown in Figure 3, at the surface deposition one trioxide layer 16 of the first conduction type extension lamella; At epitaxial loayer surface deposition trioxide layer, carry out photoetching to trioxide layer, form window and the masking layer of etching first groove and the second groove, reserve the window of etching groove, the trioxide layer stayed is as the masking layer of etching groove.
As shown in Figure 4, the first conduction type extension lamella carries out etching groove, forms the first groove and the second groove.
As shown in Figure 5, trioxide layer is removed.
As shown in Figure 6, in the first groove and the second groove, the first oxide layer is grown as grid oxygen.
As shown in Figure 7, depositing polysilicon, all filled by the second groove full, and the cell wall of the first groove and bottom is deposited with polysilicon.
As shown in Figure 8, etching polysilicon, fall more than epi-layer surface with the etching polysilicon of the first channel bottom, because the polysilicon thickness of the first trenched side-wall is thicker, the first trenched side-wall has residual polycrystalline silicon, the polysilicon of filling in the second groove retains.
As shown in Figure 9, the second conductive type impurity ion is injected at the first conduction type extension lamella and the first trench interiors, form the second conduction type implanted layer by heat treatment, and the second conduction type implanted layer is located at the upper surface of described first conductive type epitaxial layer and the below of the first groove.At the first conduction type extension lamella surface imp lantation second conductive type impurity, and make it spread under thermal process, diffusion junction depth is no more than gash depth, forms the channel region of MOSFET.
As shown in Figure 10, the surface of the second conduction type implanted layer makes the injection zone of the first conductive type impurity by lithography, and inject the first conductive type impurity ion, form the first conduction type implanted layer by heat treatment, form the source region of MOSFET simultaneously.
As shown in figure 11, deposit one second oxide skin(coating), forms a dielectric layer.
As shown in figure 12, contact hole photoetching and etching, the contact hole etching degree of depth should exceed source region junction depth, is less than channel region junction depth, ensure contact hole can with source region and channel region contacts; The laggard perform hole of contact hole etching is injected, and injects the second conductive type impurity, makes metal in contact hole can form ohmic contact with the second conduction type implanted layer; Deposited metal (as tungsten), ensures to be filled with metal completely in contact hole, the second conduction type implanted layer is contacted with the first conduction type implanted layer, and removes unnecessary metal by CMP (Chemical Mechanical Polishing) process.
As shown in figure 13, deposit the 3rd metal level, and carry out photoetching, the 3rd metal level remained is respectively as the electrode of source electrode and grid, and the cut-off region of device edge; Source electrode is connected with the first conduction type implanted layer with the second conduction type implanted layer in the first conductive type epitaxial layer by contact hole, and grid is connected with the polysilicon in the second groove by contact hole; The floating becket of device edge is connected with the first conduction type implanted layer with the second groove of outmost turns and the second conduction type implanted layer of outmost turns by contact hole, form cut-off region, and cut-off region of the present invention is a ring-type cut-off region.
Last deposit passivation layer 14, forms protective layer at device surface, improves the reliability of device, is needing the region of packaging and routing to carry out PAD hole etching, removes passivation layer.
Preparation drain region electrode, the first conduction type substrate back is thinning, deposit the 4th metal level, forms drain region electrode, the 4th metal level can for Ti+Ni+Ag layer or other can be used for the metal level that encapsulates.
Terminal structure of the present invention comprises, first point of nip that several first groove is formed, second point of nip that several second groove is formed, and the cut-off region that one second groove and one first conduction type implanted layer and one second conduction type implanted layer are connected to form by metal level.
Several first groove is comprised in first point of nip, because the first groove is not filled completely by polysilicon, so when the second conduction type implanted layer injects, second conductive type impurity can be injected into beneath trenches, form the second conduction type implanted layer, the second conductivity type implanted region is formed in beneath trenches, when draining high potential, second conduction type implanted layer can exhaust completely, and depletion layer is expanded to epitaxial loayer depths, for ensureing exhausting of the second conductivity regions, by optimizing the width of every root first groove, the optimization of Electric Field Distribution can be ensured.
Second point of nip comprises several second groove, because Electric Field Distribution most of in end ring is at the first channel bottom near source region, electric field in second point of nip obviously reduces, make bottom it, to inject the second conductive type impurity as re-used the first groove, the second conductivity type implanted region can not have been made again to exhaust completely, therefore, use the efficiency of the first groove to reduce very fast, waste chip area; Use the second groove can obtain the effect close with original first groove, but save a lot of area.By calculating, in the chip that more than 100V is withstand voltage, structure of the present invention can save the chip area of 2% ~ 5% than original structure.
Cut-off region is conventional cut-off ring design, connected to form by contact hole and the second metal level and chip edge one second conduction type implanted layer and one first conduction type implanted layer by one second groove, the second groove and the second conduction type implanted layer and the first conduction type implanted layer is made to form equipotential ring, effectively can prevent the removable electric charge of chip edge under electric field action, entering chip internal, improve the reliability of device.
Be only preferred embodiment of the present invention described in upper, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a groove MOSFET terminal structure, is characterized in that, comprising:
One first conduction type substrate;
One first conduction type extension lamella, it is located at the side of described first conduction type substrate;
Some first point of nips, it comprises some first grooves, the cell wall of described first groove and bottom land are all deposited with one first oxide skin(coating), and described first trench interiors is provided with polysilicon layer, and described polysilicon layer is deposited on the cell wall of described first groove, the both sides of the first groove and below are provided with the second conduction type implanted layer in described first conduction type epitaxial wafer;
Some second point of nips, it comprises some second grooves, and the cell wall of described second groove and bottom land are all deposited with one first oxide skin(coating), and is deposited with polysilicon layer in described second groove.
2. groove MOSFET terminal structure according to claim 1, is characterized in that, also comprise a cut-off region, it comprises:
One second groove, it is located in described first conductive type epitaxial layer, and the cell wall of described second groove and bottom land are all deposited with one first oxide skin(coating), and is deposited with polysilicon layer in described second groove;
One first conduction type implanted layer, it is located in described second conduction type implanted layer, and is in the edge of described second conduction type implanted layer;
Contact hole, and inject the second conductive type impurity in described contact hole, it is located at the second groove and the second conduction type implanted layer is inner, and the contact hole be located in the second conduction type implanted layer contacts with described first conduction type implanted layer;
One second oxide skin(coating), it establishes the first oxide skin(coating) and and the outside of the first groove;
One second metal level, it is located at the outside of the second oxide skin(coating), and the second metal level is connected with contact hole.
3. groove MOSFET terminal structure according to claim 1 and 2, is characterized in that, the width of described first groove is greater than the width of described second groove.
4. containing, for example a groove MOSFET device for the groove MOSFET terminal structure in claims 1 to 3 described in any one, it is characterized in that, also comprise a drain region electrode, it is located at the opposite side of described first conduction type substrate.
5. groove MOSFET device according to claim 4, is characterized in that, also comprises:
One source pole electrode, it is connected with channel region with the source region in the first conduction type extension lamella by contact hole;
One gate electrode, it is connected with the polysilicon of the second groove in source region by contact hole.
6. a preparation method for groove MOSFET device, is characterized in that, comprises the following steps:
First conduction type substrate layer grows the first conduction type extension lamella of homotype doping;
First conduction type extension lamella carries out etching groove, forms the first groove and the second groove;
The first oxide layer is grown as grid oxygen in the first groove and the second groove;
At depositing polysilicon, and the second groove is all filled full, and the cell wall of the first groove is deposited with polysilicon;
The second conductive type impurity ion is injected at the first conduction type extension lamella and the first trench interiors, form the second conduction type implanted layer by heat treatment, and the second conduction type implanted layer is located at the upper surface of described first conductive type epitaxial layer and the below of the first groove;
The surface of the first conductivity type epitaxial layer makes by lithography the injection zone of the first conductive type impurity, and injects the first conductive type impurity ion, form the first conduction type implanted layer by heat treatment;
Deposit one second oxide skin(coating), forms a dielectric layer;
Contact hole photoetching and etching, contact hole and source region and channel region contacts,
Deposit the 3rd metal level, and carry out photoetching formation source electrode, grid and cut-off region;
Preparation drain region electrode.
7. the preparation method of groove MOSFET device according to claim 6, is characterized in that, also comprises:
At the surface deposition one trioxide layer of the first conduction type extension lamella;
Photoetching is carried out to trioxide layer, forms window and the masking layer of etching first groove and the second groove.
8. the preparation method of groove MOSFET device according to claim 7, is characterized in that, also comprises: removed by trioxide layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810724A (en) * | 2016-04-29 | 2016-07-27 | 深圳尚阳通科技有限公司 | Shielding gate power device and manufacturing method thereof |
| CN105870172A (en) * | 2016-04-28 | 2016-08-17 | 上海格瑞宝电子有限公司 | MOSFET and preparation method therefor |
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