CN102832234A - Groove type semiconductor power device, method for producing same and terminal protection structure - Google Patents
Groove type semiconductor power device, method for producing same and terminal protection structure Download PDFInfo
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- CN102832234A CN102832234A CN2012103320178A CN201210332017A CN102832234A CN 102832234 A CN102832234 A CN 102832234A CN 2012103320178 A CN2012103320178 A CN 2012103320178A CN 201210332017 A CN201210332017 A CN 201210332017A CN 102832234 A CN102832234 A CN 102832234A
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Abstract
The invention discloses a semiconductor power device which can be used for lowering the production cost and improving the reverse breakdown voltage. The semiconductor power device comprises a semiconductor baseplate, wherein an active area which is formed by connecting unit cells in parallel is formed at the central area of the semiconductor baseplate, a terminal protection area is arranged at the periphery of the active area, and comprises at least one voltage dividing ring and at least one cut-off ring, and the cut-off ring is positioned at the periphery of the voltage dividing ring; a first groove is arranged in the terminal protection area, and forms the voltage dividing ring of the terminal protection area; an insulation gate oxide layer is formed on the inner wall of the first groove, and a first polycrystalline silicon field plate and a second polycrystalline silicon field plate are respectively arranged at the two sides of the groove, and are isolated from each other through an insulating medium layer; and second electric conducting type layers are respectively arranged at the two sides and the bottom of the first groove. The invention further discloses a method for producing the semiconductor power device. With the semiconductor power device, the manufacturing cost of the semiconductor power device is lowered, and the voltage resistance and the reliability of the semiconductor power device are also greatly improved.
Description
Technical field
The present invention relates to the manufacturing approach of a kind of trench semiconductor power device and terminal protection structure wherein and trench semiconductor power device.
Background technology
Along with the continuous maturation of power MOS (Metal Oxide Semiconductor) device technology and design, the competition of power MOS (Metal Oxide Semiconductor) device both at home and abroad is more and more fierce also, and the performance and the reliability that reduce device cost, raising device are also more and more urgent.Under the prerequisite that does not influence device performance, the photoetching number of times that reduces in the device fabrication is to reduce by two important means of device cost with the size of dwindling chip.
In the evolution of power MOS (Metal Oxide Semiconductor) device, in order to reduce cost, adopt the patent No. to be usually: the disclosed a kind of groove type MOS device fabrication based on four photoetching techniques of the Chinese invention patent of ZL200710302461.4 comes volume production groove type MOS device.Structure through the groove type power MOS device of this technology manufacturing is: on the top plan view of groove type MOS device; The active area and peripheral terminal protection structure that comprise the center, this terminal protection structure is by groove-shaped guard ring (or claiming potential dividing ring) and groove-shaped forming by ring; The groove of said guard ring is positioned at lightly doped second conductive type layer, and the degree of depth is goed deep into first conductive type layer of second conductive type layer below.
From the actual emulation result; Because its guard ring is first conductive type layer that simple groove structure and gash depth go deep into second conductive type layer below, when withstand voltage, first guard ring of inner ring has born nearly 80% voltage drop to the device of this structure reverse; At this moment; Can form narrow depletion layer at first guard ring of inner ring near the sidewall of active area is other, nearly 80% potential lines concentrates in the said depletion layer, in said depletion layer, forms strong electric field region; Can know from the actual emulation result; The withstand voltage that above-mentioned single guard ring groove structure can bear is 30V～40V; When device reverse biased during at 55V, the voltage drop that first guard ring groove of inner ring has born nearly 44V has surpassed its ability to bear; Cause device to puncture in advance at first guard ring groove place of inner ring, device withstand voltage is limited in about 55V.In addition, can know, because above-mentioned MOS device only adopts a groove-shaped ring that ends by actual emulation; It is a little less than ability, and when reverse voltage was higher, the MOS device can produce a large amount of leakage currents by the ring place; Cause device reliability to reduce, even cause the inefficacy of MOS device function property.
In sum; Existing four photoetching techniques only limit to the groove type MOS device products of puncture voltage below 55V; High voltage, powerful groove type MOS device products still adopt the manufacturing technology of six photoetching even eight layer photoetchings; Describe a kind of method that adopts six photoetching technique manufacturing groove type MOS devices among the Chinese patent ZL 201010003953.5 in detail, its step comprises:
1), field oxide growth;
2), active area etching (photoetching level 1);
3), guard ring zone etching, ion inject heat treatment formation terminal protection structure (photoetching level 2);
4), hard mask is grown and selective etch the zone (photoetching level 3) of definition etching groove;
5), utilize hard mask optionally to carry out etching groove;
6), the growth gate oxide, the deposit conductive polycrystalline silicon;
7), etching conductive polysilicon;
8), inject the second type dopant ion, heat treatment forms the second type trap layer;
9), photoetching forms first kind foreign ion injection zone, injection first kind foreign ion, heat treatment formation first kind injection region (photoetching level 4);
10), deposit insulating medium layer;
11), lithographic definition is drawn porose area, etching formation fairlead (photoetching level 5);
12), deposited metal, photoetching forms metal electrode (photoetching level 6).
With four photolithographic fabrication compared with techniques, the manufacturing cycle of six photolithographic fabrication technology is long, has increased the manufacturing cost of groove type MOS device, has reduced the market competitiveness of MOS device.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of and can reduce manufacturing cost, and can improve the trench semiconductor power device terminal protection structure of reverse breakdown voltage.
For solving the problems of the technologies described above; The technical scheme that the present invention adopts is: a kind of trench semiconductor power device terminal protection structure; Comprise: semiconductor substrate; Semiconductor substrate comprises first conductivity type substrate and is arranged on first conductive type epitaxial layer on first conductivity type substrate, and the surface of first conductive type epitaxial layer is first interarea, and the surface of first conductivity type substrate is second interarea; First interarea is provided with the active area that is positioned at the central area and is positioned at the peripheral terminal protection district of active area; Be coated with insulating medium layer on described first interarea, be provided with at least one potential dividing ring in the terminal protection district and be positioned at peripheral at least one of potential dividing ring and end ring;
Described potential dividing ring comprises: first groove that is arranged on the ring-type in the said terminal protection district; The inwall growth of first groove has the insulated gate oxide layer; First groove is respectively arranged with the first polysilicon field plate and the second polysilicon field plate of ring-type along its both sides inwall; Be provided with insulating medium layer between the first polysilicon field plate and the second polysilicon field plate; The first polysilicon field plate and the second polysilicon field plate are isolated through insulating medium layer, first conductive type epitaxial layer the both sides of first groove and below be provided with and contacted second conductive type layer of the outer wall of first groove;
The described ring that ends comprises: described first interarea is provided with second groove of ring-type in the terminal protection district; Second groove is deep in first conductive type epitaxial layer; The inwall growth of second groove has the insulated gate oxide layer; Be provided with conductive polycrystalline silicon in second groove, the both sides of second groove are respectively arranged with second conductive type layer.
The second conductive type layer top in said second groove outside is injected with the first conduction type implanted layer, and the first conduction type implanted layer in the conductive polycrystalline silicon in said second groove, second groove outside and second conductive type layer are through connecting into equipotential by the ring metallic plate.
Offer several first fairleads and several second fairleads facing to second groove and the outside thereof respectively along second groove on the said insulating medium layer that covers first interarea; And second fairlead stretches into second conductive type layer; Said bottom by the ring metallic plate is corresponding one by one to be provided with the pin that matches with first fairlead and second fairlead, and pin inserts respectively in corresponding first fairlead and second fairlead.
Said set-up mode by the ring metallic plate is: offer first lead-out groove and second lead-out groove facing to second groove and the outside thereof respectively along second groove on the said insulating medium layer that covers first interarea; And second lead-out groove stretches into second conductive type layer; Said bottom by the ring metallic plate is provided with two pins that match with first lead-out groove and second lead-out groove respectively, and two pins insert respectively in first lead-out groove and second lead-out groove.
The invention provides a kind of trench semiconductor power device that comprises trench semiconductor power device terminal protection structure of the present invention, second interarea of its semiconductor substrate is provided with drain electrode;
Be provided with the unit cell groove that several connect each other in the active area of its semiconductor substrate first interarea, be provided with conductive polycrystalline silicon in the unit cell groove and unify; The top of first conductive type epitaxial layer is provided with second conductive type layer, and the top that is positioned at second conductive type layer of active area is provided with the first conduction type implanted layer that contacts with unit cell groove outer wall; The both sides of unit cell groove are provided with source electrode lead-out groove or several source electrode fairleads; Be coated with the source metal plate in the said active area, the source metal plate extend into second conductive type layer from the dielectric laminar surface through source electrode lead-out groove or several source electrode fairleads; Said source metal plate forms the source electrode of said semiconductor power device;
Be provided with the 3rd groove that is connected with the unit cell groove between described active area and the terminal protection district; The inwall growth of the 3rd groove has insulating oxide; Be provided with in the 3rd groove with the unit cell groove in the conductive polycrystalline silicon that is connected of conductive polycrystalline silicon, the top of the 3rd groove is provided with the gate metal plate, the gate metal plate stretches in the 3rd groove from the dielectric laminar surface; Be connected with the conductive polycrystalline silicon in the 3rd groove, form the grid of said semiconductor power device.
The present invention also provides a kind of manufacturing approach that is used to make trench semiconductor power device of the present invention, the steps include:
A) provide claim 3 described semiconductor substrate;
B) deposit hard mask layer on first interarea makes hard mask etching zone by lithography, and the etching hard mask layer, is formed for the hard mask of etching groove;
C) etching first interarea forms unit cell groove, first groove, second groove and the 3rd groove;
D) insulating oxide of on described unit cell groove, first groove, second groove and the 3rd trench wall, growing;
E) remove hard mask layer and unit cell groove, first groove, second groove and the 3rd groove insulating oxide of inwall separately on said semiconductor substrate first interarea;
F) in unit cell groove, first groove, second groove and the 3rd groove growth insulated gate oxide layer on the inwall separately;
G) on first interarea, the conductive polycrystalline silicon of deposit simultaneously in unit cell groove, first groove, second groove and the 3rd groove;
H) etching conductive polysilicon; Remove the conductive polycrystalline silicon on first interarea, in first groove, form the first polysilicon field plate and the second polysilicon field plate;
I) inject the second conductive type impurity ion on first interarea and in first groove, form second conductive type layer through heat treatment, this second conductive type layer is positioned at the top of first conductive type epitaxial layer and the downside of first trench bottom;
J) make the injection zone of first conductive type impurity by lithography in the relevant position of first interarea, and inject the first conductive type impurity ion, form the first conduction type implanted layer through heat treatment;
K) deposit insulating medium layer on first interarea and in first groove;
L) photoetching fairlead zone, the etching insulating medium layer forms fairlead on first interarea;
M) deposited metal on first interarea and in the fairlead makes the lead-in wire zone by lithography, and etching forms metal lead wire;
N) on second interarea, carry out substrate and grind and depositing metal, form the backplate of said semiconductor power device.
Described step l) in, behind said etching insulating medium layer, the monocrystalline silicon in etching fairlead zone injects second conductive type impurity then.
The invention has the beneficial effects as follows:
1, compare existing six photoetching techniques, the present invention adopts photoetching technique four times, under the prerequisite that guarantees device performance and reliability, has saved the Twi-lithography operation, has reduced about 33% manufacturing cost, and has shortened the manufacturing cycle of device.
2, compare existing four photoetching techniques; First groove of potential dividing ring according to the invention is than the second ditch groove width by ring; In first groove, be provided with two polysilicon field plates of being isolated by insulating medium layer, and be provided with the second type dopant trap at the first channel bottom downside, electric field is evenly distributed between first trenched side-wall, first channel bottom and the two blocks of polysilicon field plates; And the first groove dividing potential drop of a plurality of potential dividing rings is even; Improved the voltage endurance capability and the reliability of trench semiconductor power device, the voltage endurance capability of trench semiconductor power device can be strengthened to 250V, has significantly improved the oppositely withstand voltage of trench semiconductor power device.
3, compare existing four photoetching techniques; The present invention groove-shapedly increases the reverse leakage current when withstand voltage of trench semiconductor power device by ability by ring through plural; Thereby reduced the leakage current of trench semiconductor power device, improved the reliability of trench semiconductor power device.
Description of drawings
Fig. 1 is the structural representation of N groove type power MOS device of the present invention;
Fig. 2 is the A-A partial sectional view of Fig. 1;
Fig. 3 is the B-B partial sectional view of Fig. 1;
Fig. 4 to Figure 13 be with manufacturing approach of the present invention in the structural representation of the corresponding N groove type power MOS device of processing step, wherein:
Fig. 4 is the cutaway view of semiconductor substrate;
Fig. 5 is the cutaway view behind the formation groove;
Fig. 6 is the cutaway view behind the formation gate oxide;
Fig. 7 is the cutaway view behind the deposit conductive polycrystalline silicon in the groove;
Fig. 8 is the cutaway view behind the etching conductive polysilicon;
Fig. 9 is the cutaway view behind the formation second conduction type implanted layer;
Figure 10 is the cutaway view behind the formation first conduction type implanted layer;
Figure 11 is the cutaway view behind the deposit insulating medium layer;
Figure 12 is the cutaway view behind the formation fairlead;
Figure 13 is the cutaway view after formation metal level and the backplate;
Reference numeral among Fig. 1 to Figure 13: 1, unit cell, 2, active area, 3, the terminal protection district, 4, potential dividing ring, 5, by ring, 6, N type substrate; 7, N type epitaxial loayer, 8, hard mask, 9, the unit cell groove, 10, first groove, 11, second groove; 12, the 3rd groove, 13, the insulated gate oxide layer, 14, conductive polycrystalline silicon, 15, the first polysilicon field plate, 16, the second polysilicon field plate; 17, P type layer, 18, N type implanted layer, 19, insulating medium layer, 21, the gate metal plate, 22, by the ring metallic plate; 23, backplate, 24, the source metal plate, 31, first fairlead, 32, second fairlead, 33, the source electrode fairlead.
Figure 14 is for adopting the reverse withstand voltage emulation sketch map of the groove type power MOS device that has four photoetching techniques manufacturings now;
Figure 15 is the reverse withstand voltage emulation sketch map of the groove type power MOS device of the manufacturing approach manufacturing of employing trench semiconductor power device according to the invention;
Reference numeral among Figure 14 to Figure 15: 25, depletion layer, 26, potential lines, 27, the electric current during device breakdown.
Embodiment
At first, in conjunction with accompanying drawing 1 to 3, be that example is described trench semiconductor power device of the present invention in detail with the N groove type power MOS device.
Like Fig. 1, Fig. 2 and shown in Figure 3; A kind of N groove type power MOS device; Comprise: semiconductor substrate, semiconductor substrate comprises: as the N type substrate 6 of first conductivity type substrate and be arranged on the N type epitaxial loayer 7 of conduct first conductive type epitaxial layer on the N type substrate 6, the surface of N type epitaxial loayer 7 is first interarea; The surface of N type substrate 6 is second interarea; First interarea is provided with the active area 2 that is positioned at the central area and is positioned on peripheral terminal protection district 3, the first interareas of active area 2 and is coated with insulating medium layer, be provided with in the terminal protection district 3 two potential dividing rings 4 with one be positioned at two potential dividing rings 4 peripheral by encircling 5; Described potential dividing ring 4 comprises: first groove 10 that is arranged on the ring-type in the said terminal protection district 3; The inwall growth of first groove 10 has insulated gate oxide layer 13; First groove 10 is respectively arranged with the first polysilicon field plate 15 and the second polysilicon field plate 16 of ring-type along its both sides inwall; Be provided with insulating medium layer 19 between the first polysilicon field plate 15 and the second polysilicon field plate 16; The first polysilicon field plate 15 and the second polysilicon field plate 16 are isolated through insulating medium layer 19, N type epitaxial loayer 7 the both sides of first groove 10 and below be provided with and the contacted P type of the outer wall of first groove 10 layer 17; The described ring 5 that ends comprises: described first interarea is provided with second groove 11 of ring-type in terminal protection district 3; Second groove 11 is deep in the N type epitaxial loayer 7; The inwall growth of second groove 11 has insulated gate oxide layer 13; The top that the both sides that are deposited with conductive polycrystalline silicon 14, the second grooves 11 in second groove 11 are respectively arranged with the P type layer 17 in P type layer 17, the second groove 11 outsides is injected with N type implanted layer 18; Conductive polycrystalline silicon 14 in said second groove 11, the N type implanted layer 18 in second groove, 11 outsides and P type layer 17 are through connecting into equipotential by ring metallic plate 22; Set-up mode by ring metallic plate 22 is: offer several first fairleads 31 and several second fairleads 32 facing to second groove 11 and the outside thereof respectively along second groove 11 on the said insulating medium layer 19 that covers first interarea; And second fairlead 32 stretches into P type layer 17; Be provided with the pin that matches with first fairlead 31 and second fairlead 32 by the bottom of ring metallic plate 22 is corresponding one by one, pin inserts in corresponding first fairlead 31 and second fairlead 32; Described second interarea is provided with drain electrode (not drawing among the figure); Be provided with the unit cell groove 9 that several connect each other in the active area 2 of said first interarea, be deposited with conductive polycrystalline silicon 14 in the unit cell groove 9, the conductive polycrystalline silicon 14 in all unit cell grooves 9 unifies; The top of N type epitaxial loayer 7 is provided with P type layer 17, and the top that is positioned at the P type layer 17 of active area 2 is provided with the N type implanted layer 18 that contacts with unit cell groove 9 outer walls; The both sides of unit cell groove 9 offer several source electrode fairleads 33 respectively along unit cell groove 9; Be coated with source metal plate 24 in the described active area 2, source metal plate 24 extend into P type layer 17 from insulating medium layer 19 surfaces through source electrode fairlead 33, and source metal plate 24 forms the source electrode of described semiconductor power device; Be provided with the 3rd groove 12 that is connected with unit cell groove 9 between described active area 2 and the terminal protection district 3; The inwall growth of the 3rd groove 12 has insulated gate oxide layer 13; Be provided with the conductive polycrystalline silicon 14 that is connected with unit cell groove 9 interior conductive polycrystalline silicons 14 in the 3rd groove 12; The top of the 3rd groove 12 is provided with gate metal plate 21; Gate metal plate 21 stretches in the 3rd groove 12 from insulating medium layer 19 surfaces, is connected with the 3rd groove 12 interior conductive polycrystalline silicons 14, forms the grid of said semiconductor power device.Described insulating medium layer 19 is a Si oxide, preferably the Si oxide of boron phosphorus doped; Described several source electrode fairleads 33, several first fairleads 31 and several second fairleads 32 all can be substituted by a groove.
Present embodiment adopt two potential dividing rings 4 with one by ring 5, potential dividing ring 4 and should confirm according to actual needs by the quantity of encircling 5.
Invent described trench semiconductor power device and comprise P raceway groove groove type power MOS device certainly, only need to change the N type substrate 6 in the above-mentioned N groove type power MOS device into P type substrate, N type epitaxial loayer 7 and change that P type epitaxial loayer, P type layer 17 change N type layer into, N type implanted layer 18 changes P type implanted layer into and gets final product into.
Next, in conjunction with accompanying drawing 4 to 13, be the manufacturing approach that example is described trench semiconductor power device of the present invention in detail with the N groove type power MOS device, the steps include:
A) the lightly doped N type epitaxial loayer 7 of growth on heavily doped N type substrate 6 forms with N type epitaxial loayer 7 surfaces as first interarea with the semiconductor substrate of N type substrate 6 surfaces as second interarea---referring to shown in Figure 4;
B) deposit hard mask layer on first interarea makes hard mask etching zone by lithography, and etching hard mask layer 8---referring to shown in Figure 5, be formed for the hard mask of etching groove;
C) etching first interarea forms unit cell groove 9, first groove 10, second groove 11 and the 3rd groove 12---referring to shown in Figure 5;
D) insulating oxide of on described unit cell groove 9, first groove 10, second groove 11 and the 3rd groove 12 inwalls, growing;
E) remove hard mask layer and unit cell groove 9 on said semiconductor substrate first interarea, first groove 10, second groove 11 and the 3rd groove 12 insulating oxide of inwall separately;
F) in unit cell groove 9, first groove 10, second groove 11 and the 3rd ditch 12 grooves growth insulated gate oxide layer 13 on the inwall separately---referring to shown in Figure 6;
G) conductive polycrystalline silicon of deposit simultaneously 14 in unit cell groove 9, first groove 10, second groove 11 and the 3rd groove 12---referring to shown in Figure 7;
H) etching conductive polysilicon; Remove the conductive polycrystalline silicon on first interarea, make to be full of conductive polycrystalline silicon 14 in unit cell groove 9, second groove 11, the 3rd groove 12, in first groove 10, form the first polysilicon field plate 15 and the second polysilicon field plate 16---referring to shown in Figure 8;
I) inject the p type impurity ion on first interarea and in first groove 10, form P type layer 17 through heat treatment, this P type layer 17 is positioned at the top of N type epitaxial loayer 7 and the outside of first groove, 10 bottom lands---referring to shown in Figure 9;
J) make the injection zone of N type foreign ion by lithography in the relevant position of first interarea, and inject N type foreign ion (N+), form N type implanted layer 18 through heat treatment---referring to shown in Figure 10;
K) deposit insulating medium layer 19 on first interarea and in first groove 10---referring to shown in Figure 11;
L) photoetching fairlead zone, the etching insulating medium layer forms various fairleads on first interarea---referring to shown in Figure 12; Behind the etching insulating medium layer, but the monocrystalline silicon in etching fairlead zone also injects the p type impurity ion then.
M) deposited metal on first interarea and in the various fairleads makes the lead-in wire zone by lithography, and it is corresponding various metallic plate that etching forms metal lead wire---referring to shown in Figure 13;
N) on second interarea, carry out substrate and grind and depositing metal, form the backplate 23 of said MOS device---referring to shown in Figure 13.
Figure 14 for existing four reticle structures in reverse analogous diagram when withstand voltage, emulation Figure 15 of contrast structure of the present invention can find out; When withstand voltage, most potential lines 26 all concentrate on the side place of first potential dividing ring of inner ring near active area to the MOS device of existing structure reverse, and depletion layer is thinner here; Intensive the causing of potential lines 26 produces local big electric field here; Breakdown potential streamline 27 by among Figure 14 can know that device punctures in advance herein, a little less than the voltage endurance capability.And can know by Figure 15; MOS device of the present invention is reverse when withstand voltage; Potential lines 26 is evenly distributed on the side-walls near active area of potential dividing ring 4, the groove of potential dividing ring 4 is in the depletion layer 25 interior insulating medium layers 19 that reach between the first polysilicon field plate 15 and the second polysilicon field plate 16 of first groove, 10 bottoms; Because avoided the intensive branch of potential lines 26, Electric Field Distribution is even here, voltage endurance capability is improved.
The present invention adopts photoetching technique four times, makes high-tension high-power MOS device, with respect to existing six photoetching techniques; It has reduced Twi-lithography on the basis that does not influence the power MOS (Metal Oxide Semiconductor) device performance; Reduce about 33% manufacturing cost, shortened the manufacturing cycle, improved competitiveness of product; Technology with respect to existing four photoetching; Power MOS (Metal Oxide Semiconductor) device potential dividing ring 4 of the present invention has adopted the first polysilicon field plate 15, the second polysilicon field plate 16, potential dividing ring bottom downside that the structure of P type layer 17 is set; Make power MOS (Metal Oxide Semiconductor) device reverse when withstand voltage Electric Field Distribution even; Improved the voltage endurance capability and the reliability of power MOS (Metal Oxide Semiconductor) device, broken through the restriction of existing four withstand voltage 55V of being lower than of photoetching technique product, made that power MOS (Metal Oxide Semiconductor) device is withstand voltage can bring up to 250V.
Claims (7)
1. trench semiconductor power device terminal protection structure; Comprise: semiconductor substrate; Semiconductor substrate comprises first conductivity type substrate and is arranged on first conductive type epitaxial layer on first conductivity type substrate; The surface of first conductive type epitaxial layer is first interarea, and the surface of first conductivity type substrate is second interarea; First interarea is provided with the active area that is positioned at the central area and is positioned at the peripheral terminal protection district of active area; Be coated with insulating medium layer on described first interarea, be provided with at least one potential dividing ring in the terminal protection district and be positioned at peripheral at least one of potential dividing ring and end ring; It is characterized in that:
Described potential dividing ring comprises: first groove that is arranged on the ring-type in the said terminal protection district; The inwall growth of first groove has the insulated gate oxide layer; First groove is respectively arranged with the first polysilicon field plate and the second polysilicon field plate of ring-type along its both sides inwall; Be provided with insulating medium layer between the first polysilicon field plate and the second polysilicon field plate; The first polysilicon field plate and the second polysilicon field plate are isolated through insulating medium layer, first conductive type epitaxial layer the both sides of first groove and below be provided with and contacted second conductive type layer of the outer wall of first groove;
The described ring that ends comprises: described first interarea is provided with second groove of ring-type in the terminal protection district; Second groove is deep in first conductive type epitaxial layer; The inwall growth of second groove has the insulated gate oxide layer; Be provided with conductive polycrystalline silicon in second groove, the both sides of second groove are respectively arranged with second conductive type layer.
2. trench semiconductor power device terminal protection structure according to claim 1 is characterized in that, the second conductive type layer top in said second groove outside is injected with the first conduction type implanted layer; The first conduction type implanted layer in the conductive polycrystalline silicon in said second groove, second groove outside and second conductive type layer are through connecting into equipotential by the ring metallic plate.
3. trench semiconductor power device terminal protection structure according to claim 2; It is characterized in that; Said set-up mode by the ring metallic plate is: offer several first fairleads and several second fairleads facing to second groove and the outside thereof respectively along second groove on the said insulating medium layer that covers first interarea; And second fairlead stretches into second conductive type layer; Said bottom by the ring metallic plate is corresponding one by one to be provided with the pin that matches with first fairlead and second fairlead, and pin inserts respectively in corresponding first fairlead and second fairlead.
4. trench semiconductor power device terminal protection structure according to claim 2; It is characterized in that; Said set-up mode by the ring metallic plate is: offer first lead-out groove and second lead-out groove facing to second groove and the outside thereof respectively along second groove on the said insulating medium layer that covers first interarea; And second lead-out groove stretches into second conductive type layer; Said bottom by the ring metallic plate is provided with two pins that match with first lead-out groove and second lead-out groove respectively, and two pins insert respectively in first lead-out groove and second lead-out groove.
5. a trench semiconductor power device is characterized in that, described trench semiconductor power device comprises the described trench semiconductor power device terminal protection structure of claim 1, and described second interarea is provided with drain electrode;
Be provided with the unit cell groove that several connect each other in the described active area, be provided with conductive polycrystalline silicon in the unit cell groove and unify; The top of first conductive type epitaxial layer is provided with second conductive type layer, and the top that is positioned at second conductive type layer of active area is provided with the first conduction type implanted layer that contacts with unit cell groove outer wall; The both sides of unit cell groove are provided with source electrode lead-out groove or several source electrode fairleads; Be coated with the source metal plate in the said active area, the source metal plate extend into second conductive type layer from the dielectric laminar surface through source electrode lead-out groove or several source fairleads; Said source metal plate forms the source electrode of said semiconductor power device;
Be provided with the 3rd groove that is connected with the unit cell groove between described active area and the terminal protection district; The inwall growth of the 3rd groove has the insulated gate oxide layer; Be provided with in the 3rd groove with the unit cell groove in the conductive polycrystalline silicon that is connected of conductive polycrystalline silicon, the top of the 3rd groove is provided with the gate metal plate, the gate metal plate stretches in the 3rd groove from the dielectric laminar surface; Be connected with the conductive polycrystalline silicon in the 3rd groove, form the grid of said semiconductor power device.
6. the manufacturing approach of trench semiconductor power device as claimed in claim 5 the steps include:
A) provide claim 4 described semiconductor substrate;
B) deposit hard mask layer on first interarea makes hard mask etching zone by lithography, and the etching hard mask layer, is formed for the hard mask of etching groove;
C) etching first interarea forms unit cell groove, first groove, second groove and the 3rd groove;
D) insulating oxide of on described unit cell groove, first groove, second groove and the 3rd trench wall, growing;
E) remove hard mask layer and unit cell groove, first groove, second groove and the 3rd groove insulating oxide of inwall separately on said semiconductor substrate first interarea;
F) in unit cell groove, first groove, second groove and the 3rd groove growth insulated gate oxide layer on the inwall separately;
G) on first interarea, the conductive polycrystalline silicon of deposit simultaneously in unit cell groove, first groove, second groove and the 3rd groove;
H) etching conductive polysilicon; Remove the conductive polycrystalline silicon on first interarea, in first groove, form the first polysilicon field plate and the second polysilicon field plate;
I) inject the second conductive type impurity ion on first interarea and in first groove, form second conductive type layer through heat treatment, this second conductive type layer is positioned at the top of first conductive type epitaxial layer and the downside of first trench bottom;
J) make the injection zone of first conductive type impurity by lithography in the relevant position of first interarea, and inject the first conductive type impurity ion, form the first conduction type implanted layer through heat treatment;
K) deposit insulating medium layer on first interarea and in first groove;
L) photoetching fairlead zone, the etching insulating medium layer forms fairlead on first interarea;
M) deposited metal on first interarea and in the fairlead makes the lead-in wire zone by lithography, and etching forms metal lead wire;
N) on second interarea, carry out substrate and grind and depositing metal, form the backplate of said semiconductor power device.
7. the manufacturing approach of trench semiconductor power device according to claim 6 is characterized in that: said step l), behind said etching insulating medium layer, the monocrystalline silicon in etching fairlead zone injects second conductive type impurity then.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151381A (en) * | 2013-02-02 | 2013-06-12 | 张家港凯思半导体有限公司 | Groove type semiconductor power device and manufacturing method and terminal protection structure thereof |
| CN104465488A (en) * | 2014-12-25 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Method for forming shallow-groove power device protective rings |
| CN104900703A (en) * | 2015-05-12 | 2015-09-09 | 上海格瑞宝电子有限公司 | Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof |
| CN110047934A (en) * | 2019-05-07 | 2019-07-23 | 张家港凯思半导体有限公司 | A kind of semiconductor power device and preparation method thereof for cutting down the light shield number of plies |
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| CN110061049A (en) * | 2019-05-07 | 2019-07-26 | 张家港凯思半导体有限公司 | A kind of low-power consumption shielding grid-type semiconductor power device and preparation method thereof |
| CN110277452A (en) * | 2018-03-17 | 2019-09-24 | Ixys有限责任公司 | Embedded field plate field effect transistor |
| CN110364568A (en) * | 2018-04-11 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | IGBT device and forming method thereof |
| CN110931548A (en) * | 2019-12-16 | 2020-03-27 | 安建科技(深圳)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN112802837A (en) * | 2020-12-29 | 2021-05-14 | 江苏捷捷微电子股份有限公司 | Trench MOSFET device with high electrostatic protection capability |
| WO2021114735A1 (en) * | 2019-12-12 | 2021-06-17 | 珠海格力电器股份有限公司 | Terminal structure and manufacturing method therefor and electronic device |
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
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| CN103151381A (en) * | 2013-02-02 | 2013-06-12 | 张家港凯思半导体有限公司 | Groove type semiconductor power device and manufacturing method and terminal protection structure thereof |
| CN104465488A (en) * | 2014-12-25 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Method for forming shallow-groove power device protective rings |
| CN104900703A (en) * | 2015-05-12 | 2015-09-09 | 上海格瑞宝电子有限公司 | Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof |
| CN110277452B (en) * | 2018-03-17 | 2022-06-03 | Ixys有限责任公司 | Embedded field plate field effect transistor |
| CN110277452A (en) * | 2018-03-17 | 2019-09-24 | Ixys有限责任公司 | Embedded field plate field effect transistor |
| CN110364568A (en) * | 2018-04-11 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | IGBT device and forming method thereof |
| CN110364568B (en) * | 2018-04-11 | 2024-02-02 | 中芯国际集成电路制造(上海)有限公司 | IGBT device and forming method thereof |
| CN110047831A (en) * | 2019-05-07 | 2019-07-23 | 张家港凯思半导体有限公司 | A kind of semiconductor power device and preparation method thereof |
| CN110061049A (en) * | 2019-05-07 | 2019-07-26 | 张家港凯思半导体有限公司 | A kind of low-power consumption shielding grid-type semiconductor power device and preparation method thereof |
| CN110047934B (en) * | 2019-05-07 | 2023-12-05 | 张家港凯思半导体有限公司 | Semiconductor power device capable of reducing number of photomask layers and preparation method thereof |
| CN110047831B (en) * | 2019-05-07 | 2023-12-05 | 张家港凯思半导体有限公司 | Semiconductor power device and preparation method thereof |
| CN110061049B (en) * | 2019-05-07 | 2023-12-19 | 张家港凯思半导体有限公司 | Low-power-consumption shielding grid type semiconductor power device and preparation method thereof |
| CN110047934A (en) * | 2019-05-07 | 2019-07-23 | 张家港凯思半导体有限公司 | A kind of semiconductor power device and preparation method thereof for cutting down the light shield number of plies |
| WO2021114735A1 (en) * | 2019-12-12 | 2021-06-17 | 珠海格力电器股份有限公司 | Terminal structure and manufacturing method therefor and electronic device |
| CN112993006A (en) * | 2019-12-12 | 2021-06-18 | 珠海格力电器股份有限公司 | Terminal structure, manufacturing method thereof and electronic device |
| CN110931548A (en) * | 2019-12-16 | 2020-03-27 | 安建科技(深圳)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN112802837A (en) * | 2020-12-29 | 2021-05-14 | 江苏捷捷微电子股份有限公司 | Trench MOSFET device with high electrostatic protection capability |
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
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