CN207966999U - A kind of IGBT device - Google Patents
A kind of IGBT device Download PDFInfo
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- CN207966999U CN207966999U CN201721904369.0U CN201721904369U CN207966999U CN 207966999 U CN207966999 U CN 207966999U CN 201721904369 U CN201721904369 U CN 201721904369U CN 207966999 U CN207966999 U CN 207966999U
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Abstract
The utility model discloses a kind of IGBT device, semiconductor substrate center is equipped with cellular region, first interarea of semiconductor substrate is equipped with terminal protection area of the surround ring around cellular region, the second conductive type collector area is equipped with above second interarea of semiconductor substrate, the top of second conductive type collector area is equipped with the first conduction type field stop layer, cellular in cellular region is equipped with groove structure, cellular groove is extended to through the second conduction type well layer in the first conductive type epitaxial layer in semiconductor substrate by the first interarea, Gate Electrode Conductive polysilicon is filled in cellular groove, insulation gate oxide is equipped between Gate Electrode Conductive polysilicon and cellular trench wall.The utility model extends channel length, reduces saturation current, to improve Tsc, increases short circuit current safety operation area, in addition, the utility model beneath trenches use super-junction structure, drift zone resistance rate can be reduced, to reduce Vce.Simultaneously when device turns off, because super-junction structure can accelerate carrier to extract speed, to reduce Eoff.
Description
Technical field
The utility model belongs to the technical field of semiconductor devices, is related to a kind of power IGBT device and its manufacturing method.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviation IGBT), because it is big
Current lead-through pressure drop is low, is widely used in various high-current switch conversions, such as new energy vehicle electric-control system inverter uses
Mainstream power device be exactly IGBT.The application is especially high for the switching loss of IGBT, and corresponding IGBT key parameters are to lead
Logical pressure drop Vce and Eoff, while the application has short-circuit trouble free service very high requirement, the key parameter of corresponding IGBT is short circuit
Bear time Tsc.In practical application, our target is to obtain alap Vce and Eoff and longer Tsc.Wherein
Drift zone resistance rate can be reduced, setting carrier accumulation layer is come real by increasing gully density to obtain lower Vce
It is existing；Eoff is reduced to accelerate carrier by reducing backside collector injection efficiency and extract the measures such as speed to realize； Tsc
With saturation current at inverse direction relations, saturation current is bigger, and the Tsc that can be born is shorter.
For example, patent US9299819B2 proposes to reduce saturation current by reducing gully density, Tsc is improved；By setting
Setting splitting bar reduces drift zone resistance rate between groove, while carrier accumulation layer is arranged, to reduce Vce.With wanting for application
Ask higher and higher, it is higher and higher to Vce and Eoff reductions amplitude requirement, while short-circuit safety operation area is required also increasingly
Height, the method that patent US9299819B2 is provided face more and more challenges, therefore how to further decrease power IGBT devices
Part conduction loss and switching loss, while short-circuit safety operation area is further increased as the important of those skilled in the art of the present technique
Research direction.
Utility model content
Technical problem to be solved in the utility model is to realize a kind of reduction Vce and Eoff, while further increasing Tsc
IGBT device.
To achieve the goals above, the technical solution adopted in the utility model is：A kind of IGBT device, in the IGBT devices
Include positioned at the cellular region of semiconductor substrate and terminal protection area, the terminal protection area in the top plan view of the emitter of part
Outer ring positioned at cellular region, and terminal protection area is around cellular region is surrounded, and includes several regular arrays and phase in the cellular region
The cellular of mutual parallel connection setting, on the section of the IGBT device, semiconductor substrate have corresponding first interarea with
Second interarea, the second interarea top are equipped with one layer of second conductive type collector area, the second conduction type collector
The first conduction type field stop layer is equipped with above area, the cellular in the cellular region is equipped with groove structure, the cellular groove by
First interarea is extended to through the second conduction type well layer in the first conductive type epitaxial layer in semiconductor substrate, the cellular ditch
Gate Electrode Conductive polysilicon is filled in slot, the Gate Electrode Conductive polysilicon is covered to the first interarea near cellular groove notch
Side forms T-slot grid conductive polycrystalline silicon, between the T-slot grid conductive polycrystalline silicon and the first interarea and cellular trench wall
It is equipped with insulation gate oxide.
The first conductive type emitter region, the first conductive type emitter region position are equipped with above the side wall of adjacent cellular groove
In the top of the second conduction type well layer, P+ layers are located at below the second conduction type well layer, the second conduction type well layer, P+
It is equipped with carrier accumulation layer between layer and the first conductive type epitaxial layer, first between the cellular groove and the second interarea
P columns are equipped in conductive type epitaxial layer, the P columns are located at immediately below cellular channel bottom, and P columns depth is most deep can to go deep into first
Conduction type field stop layer, but cannot pass through the first conduction type field stop layer and be in electrical contact with the second conductive type collector area.
Insulating medium layer is covered on the T-slot grid conductive polycrystalline silicon, being equipped with metal above the insulating medium layer connects
Line, the metal connecting line pass through the contact hole on insulating medium layer to be contacted with P+ layers and the first conductive type emitter region, the T
Filling metal connection between type groove grid conductive polycrystalline silicon and metal connecting line by fairlead and in fairlead, the metal
Passivation layer is provided with above line, the passivation layer is equipped with the metal linear window of bare metal line.
The doping concentration of the first conduction type field stop layer is greater than or equal to the doping of the first conductive type epitaxial layer
Concentration.
First conductive type epitaxial layer includes at least one layer of epitaxial layer structure.
The utility model uses polysilicon gate, extends channel length, reduces saturation current, to improve Tsc, increases
Short circuit current safety operation area is added, in addition, the utility model beneath trenches use super-junction structure, drift zone resistance can be reduced
Rate, to reduce Vce.Simultaneously when device turns off, because super-junction structure can accelerate carrier to extract speed, to reduce
Eoff。
Description of the drawings
The content of every width attached drawing expression in the utility model specification and the label in figure are briefly described below：
Fig. 1-15 is that the IGBT device of embodiment 1 produces schematic diagram；
Figure 16-23 is that the IGBT device of embodiment 2 produces schematic diagram
Label in above-mentioned figure is：1, the second conductive type collector area；2, the first conduction type field stop layer； 3、
First conductive type epitaxial layer；4, P columns；5, cellular groove；6, insulate gate oxide；7, T-slot grid conductive polycrystalline silicon；8, current-carrying
Sub- accumulation layer；9, the first conductive type emitter region；10, the second conduction type well layer；11, P+ layers；12, insulating medium layer；13、
Contact hole；14, metal connecting line；15, the first interarea；16, the second interarea；17, the first oxide layer；18, the second oxide layer；19,
Two conductive-type moldeed depth knots；20, hard mask layer；21, hard mask window；22, third oxide layer；23, the first metal layer；24, second
Metal layer；25, passivation layer；26, metal linear window；27, the first epitaxial layer；28, the second epitaxial layer；29, third epitaxial layer；30、
Fourth epitaxial layer；31, the 5th epitaxial layer.
Specific implementation mode
Embodiment 1：
Include positioned at the cellular region of semiconductor substrate center and positioned at cellular in the top plan view of power IGBT device
The terminal protection area of area outer ring, wherein terminal protection area surround ring include several regular arrays and phase in cellular region, cellular region
The cellular being mutually connected in parallel.
Such as Figure 15, the cellular plot structure of power IGBT device is merely illustrated, existing routine may be used in power IGBT device
Terminal protection plot structure.On the section of power IGBT device, semiconductor substrate includes the second conduction type collector polar region
And the first conduction type field stop layer 2 above second conductive type collector area 1 and the first conduction type extension
Layer 3, the first conductive type epitaxial layer 3 abut the second conductive type collector area 1, and the first conduction type field terminates the doping for prolonging layer
Concentration is more than the doping concentration of the first conductive type epitaxial layer 3.There are two corresponding interarea, two masters for semiconductor substrate tool
Face is respectively the first interarea 15 and the second interarea 16；The first interarea 15 of surface formation of first conductive type epitaxial layer 3, second
The surface of conductive type collector area 1 forms the second interarea 16, and the distribution corresponding with the second interarea 16 of the first interarea 15, first leads
Top in electric type epitaxial layer 3 is equipped with the second conduction type well layer 10 and P+ layers 11.
On the section of power IGBT device, the cellular in cellular region uses groove structure, cellular groove 5 to be located at outside first
Prolong above layer, and cellular groove 5 extends in the second conduction type well layer 10 from the first interarea 15 to the direction of the second interarea 16,
And the slot bottom of cellular groove 5 extends in the first conductive type epitaxial layer 3 of 10 lower section of the second conduction type well layer.Cellular groove
Be equipped with Gate Electrode Conductive polysilicon in 5, conductive polycrystalline silicon body covers primitive unit cell groove notch, conductive polycrystalline silicon to both sides at the top of notch or
Suitable distance is stretched out in side, forms T-slot grid conductive polycrystalline silicon 7.T-slot grid conductive polycrystalline silicon 7 is located at upper in cellular groove 5
Portion, and insulation gate oxide 6, institute are equipped between 5 side wall of T-slot grid conductive polycrystalline silicon 7 and cellular groove and between the first interarea 15
Insulation gate oxide 6 is stated to be grown on the side wall of corresponding cellular groove 5 and on the first interarea 15.T type groove grid conductive polycrystalline silicons
The outside on 7 tops is equipped with the first conductive type emitter region 9, and first conductive type emitter region 9 is located at the second conductive-type
The top of type well layer 10.
On the section of power IGBT device, 7 top of T-slot grid conductive polycrystalline silicon is covered by insulating medium layer 12, the T
The both sides of type groove grid conductive polycrystalline silicon 7 are equipped with contact hole 13, and the contact hole 13 extends to P+ from the surface of insulating medium layer 12
In layer 11, and contact hole 13 passes through corresponding first conductive type emitter region 9.It is deposited with metal connecting line on insulating medium layer 12
14, the metal connecting line 14 is covered on insulating medium layer 12, and is filled in contact hole 13.Metal connecting line 14 and the first conduction
11 ohm of type emitter region 9 and P+ layers.Connection between T-slot grid conductive polycrystalline silicon 7 and metal connecting line 14 can pass through lead
Hole and the filling metal connection in fairlead.Passivation layer 25, the passivation layer 25 can also be set on metal connecting line 14
It is the superposition by silicon dioxide layer and silicon nitride layer.
The power IGBT device of above structure can be realized by following processing steps：
A, the semiconductor substrate having there are two opposing main faces is provided；
B, as shown in Figure 1, on the first interarea 15 of semiconductor substrate one oxide layer 17 of growth regulation, that is, inject shielded layer,
Generally 250A to 500A is then injected into the first conductive type impurity, and impurity is generally phosphorus, and carrier storage is formed by annealing
Layer 8；
C, as shown in Fig. 2, making photoresist on the first interarea 15 of semiconductor substrate, cellular region is gone out by lithographic definition
After needing the region injected with termination environment, the second conductive type impurity is injected, impurity is generally boron, after removing photoresist, passes through
Annealing forms the second conductive-type moldeed depth knot 19；
D, as shown in figure 3, removing growth regulation titanium dioxide after the first oxide layer 17 on the first interarea 15 of semiconductor substrate
Layer 18, i.e. field oxide, general field oxide thickness are 5000A-20000A；Photoresist is made, the second oxide layer 18 is defined
The region etched is needed to carry out photoetching, as shown in figure 4, then removing the second oxide layer 18 of definition region by etching；
E, as shown in figure 5, on the first interarea 15 of semiconductor substrate deposit hard mask layer 20, and selectively masking and
The hard mask layer 20 is etched, as shown in fig. 6, forming the hard mask windows of etching groove on the first interarea 15 of semiconductor substrate
Mouth 21；
F, semiconductor-based by dry etching on the first interarea 15 as shown in fig. 7, using above-mentioned hard mask window 21
Plate, forms groove above the epitaxial layer of semiconductor substrate, and the groove includes cellular groove 5；
G, as shown in figure 8, using hard mask layer 20 as injection shielded layer, second conductive type impurity, note are injected
The injection for entering general multiple different-energy various dose, forms P columns 4 by knot below cellular groove 5 after injection；
H, photoresist is made on the first interarea of above-mentioned semiconductor substrate 15, goes out to need the p-well injected by lithographic definition
The second conductive type impurity is injected in area, and impurity is generally boron, then removes photoresist, and the second conduction type is formed by annealing
Well layer 10；
I, as shown in figure 9, removal hard mask layer 20, growth regulation three aoxidizes on the first interarea 15 of above-mentioned semiconductor substrate
Then layer 22, i.e. sacrificial oxide layer remove sacrificial oxide layer by wet etching, continue the first of above-mentioned half semiconductor substrate
Growth insulation gate oxide 6 on interarea 15, insulation gate oxide 6 is covered on the first interarea 15, and is covered in cellular groove 5
Side wall and bottom surface, and polysilicon depositing groove is formed in cellular groove 5；
J, as shown in Figure 10, conductive polycrystalline silicon body material layer, system are deposited on the first interarea 15 of above-mentioned semiconductor substrate
Make photoresist, after the region that conductive polycrystalline silicon needs remove is gone out by lithographic definition, passes through etching and remove conductive polycrystalline silicon, formed
T-slot grid conductive polycrystalline silicon 7；
K, as shown in figure 11, on the first interarea 15 of above-mentioned semiconductor substrate, photoresist is made, carries out emitter region light
It carves, and injects the first conductive type impurity ion, impurity is generally arsenic or phosphorus, is led by knot formation first after removing photoresist
Electric type emitter region 9；
L, insulating medium layer 12 is deposited on the first interarea 15 of above-mentioned semiconductor substrate, insulating medium layer 12 is covered in
First interarea 15 of semiconductor substrate；
M, 13 lithography and etching of contact hole is carried out to above-mentioned insulating medium layer 12, it is equal in the both sides of cellular conductive polycrystalline Si-gate
Contact hole 13 is formed, the second conductive type impurity is injected and annealing forms P+ layers 11；
N, as shown in figure 12, the first metal layer 23 is deposited on above-mentioned insulating medium layer 12, the first metal layer 23 covers
It on insulating medium layer 12, and is filled in contact hole 13, makes photoresist, define 23rd area of the first metal layer for needing to remove
Domain forms metal connecting line 14 by etching；Metal connecting line 14 forms ohm with the first conductive type emitter region and P+ layers 11 and connects
It touches；
O, as shown in figure 13, passivation layer 25 is deposited on metal connecting line 14, passivation layer 25, which generally comprises, is deposited on metal company
Silicon dioxide layer on line 14 and the silicon nitride layer in the silicon dioxide layer；Photoresist is made on passivation layer 25, it is fixed
Justice goes out passivation layer 25 and removes area, and the metal linear window 26 is formed by dry etching；
P, as shown in figure 14, it after the second interarea of above-mentioned semiconductor 16 is thinned to certain thickness, is noted on the second interarea 16
Enter the first conductive type impurity, impurity is generally phosphorus, then forms the first conduction type field stop layer 2 by annealing；
Q, the second conductive type impurity is injected on the second interarea 16, impurity is generally boron, then forms the by annealing
Two conductive type collector areas 1；
R, as shown in figure 15, by evaporating or sputtering second metal layer 24, second metal layer 24 1 on the second interarea 16
As be Al-Ti-Ni-Ag, second metal layer 24 and the second conductive type collector area 1 formation Ohmic contact.
Embodiment 2：
As shown in Figure 16-23, in the top plan view of the power IGBT device, including it is located at semiconductor substrate center
Cellular region and terminal protection area positioned at the cellular region outer ring, terminal protection area surround ring is around cellular region, the member
The cellular for including several regular arrays in born of the same parents area and being connected in parallel with each other.
Existing conventional terminal protection plot structure may be used in power IGBT device, in the section of the power IGBT device
On, the semiconductor substrate includes the second conduction type collector polar region and is located above second conductive type emitter region
The first conduction type field stop layer 2, the first epitaxial layer 27, the second epitaxial layer 28, third epitaxial layer 29, fourth epitaxial layer 30
And the 5th epitaxial layer 31, the first epitaxial layer 27 abut the second conductive type collector area 1, the first conduction type field, which terminates, prolongs layer
Doping concentration is more than the doping concentration of the first epitaxial layer 27.
For semiconductor substrate tool there are two corresponding interarea, two interareas are respectively the first interarea 15 and the second interarea 16,
The first interarea 15 of surface formation of 5th epitaxial layer 31, the second interarea 16 of surface formation of the second conductive type drain area, first
The distribution corresponding with the second interarea 16 of interarea 15, the top in the 5th epitaxial layer 31 are equipped with the second conduction type well layer 10 and P+ layers
11。
On the section of power IGBT device, the cellular in cellular region uses groove structure, the cellular groove 5 to be located at
Above 5th epitaxial layer, and cellular groove 5 is interior from the first interarea 15 to the side of the second interarea 16 in the second conduction type well layer 10
It is extended to the slot bottom of extension, and cellular groove 5 in the 5th epitaxial layer of 10 lower section of the second conduction type well layer.Cellular groove 5
Interior to be equipped with Gate Electrode Conductive polysilicon, conductive polycrystalline silicon body covers primitive unit cell groove notch, conductive polycrystalline silicon to both sides at the top of notch or
Suitable distance is stretched out in side, forms T-slot grid conductive polycrystalline silicon 7.T-slot grid conductive polycrystalline silicon 7 is located at upper in cellular groove 5
Portion, and insulation gate oxide 6, insulation are equipped between 5 side wall of T-slot grid conductive polycrystalline silicon 7 and cellular groove and between the first interarea 15
Gate oxide 6 is grown on the side wall of corresponding cellular groove 5 and on the first interarea 15.7 top of T-slot grid conductive polycrystalline silicon
Outside is equipped with the first conductive type emitter region 9, and the first conductive type emitter region 9 is located at the upper of the second conduction type well layer 10
Portion.
On the section of power IGBT device, 7 top of T-slot grid conductive polycrystalline silicon is covered by insulating medium layer 12, the T
The both sides of type groove grid conductive polycrystalline silicon 7 are equipped with contact hole 13, and contact hole 13 extends to P+ layers 11 from the surface of insulating medium layer 12
It is interior, and contact hole 13 passes through corresponding first conductive type emitter region 9.Metal connecting line 14 is deposited on insulating medium layer 12,
The metal connecting line 14 is covered on insulating medium layer 12, and is filled in contact hole 13.Metal connecting line 14 and the first conductive-type
11 ohm of type emitter region 9 and P+ layers.Connection between T-slot grid conductive polycrystalline silicon 7 and metal connecting line 14 can pass through fairlead
And the filling metal connection in fairlead.Passivation layer 25 can also be set on metal connecting line 14, and passivation layer 25 is by two
The superposition of silicon oxide layer and silicon nitride layer.
The power IGBT device of above structure can be realized by following processing steps：
A, semiconductor substrate comprising the second interarea 16 and the first epitaxial layer 27 is provided,
B, as shown in figure 16, photoresist is made on the first epitaxial layer 27, after going out 4 injection zone of P columns by lithographic definition, note
Enter the second conductive type impurity, general impurity is boron, then removes photoresist；
C, as shown in figure 17, then two epitaxial layer 28 of growth regulation on the first epitaxial layer 27 makes on the second epitaxial layer 28 again
Photoresist after going out 4 injection zone of P columns by lithographic definition, injects the second conductive type impurity, and general impurity is boron, is then gone
Except photoresist；
D, as shown in figure 18, then three epitaxial layer 29 of growth regulation on the second epitaxial layer 28 makes on third epitaxial layer 29 again
Photoresist after going out 4 injection zone of P columns by lithographic definition, injects the second conductive type impurity, and general impurity is boron, is then gone
Except photoresist；
E, as shown in figure 19, fourth epitaxial layer 30 is grown on third epitaxial layer 29, is then made in fourth epitaxial layer 30 again
Photoresist after going out 4 injection zone of P columns by lithographic definition, injects the second conductive type impurity, and general impurity is boron, is then gone
Except photoresist；
F, as shown in figure 20, the surface of five epitaxial layer 31 of growth regulation in fourth epitaxial layer 30, the 5th epitaxial layer 31 forms half
Then first interarea 15 of conductor forms P columns 4 by knot；
G, as shown in figure 21, one oxide layer 17 of growth regulation, that is, inject shielded layer on the first interarea 15 of semiconductor substrate,
Generally 250A to 500A is then injected into the first conductive type impurity, and impurity is generally phosphorus, and carrier storage is formed by annealing
Layer 8；
H, as shown in figure 22, photoresist is made on the first interarea 15 of semiconductor substrate, cellular is gone out by lithographic definition
After area and termination environment need the region injected, the second conductive type impurity is injected, impurity is generally boron, after removing photoresist, leads to
It crosses annealing and forms the second conductive-type moldeed depth knot 19；
I, photoresist is made on the first interarea of above-mentioned semiconductor substrate 15, goes out to need the p-well injected by lithographic definition
Area, injects the second conductive type impurity, and impurity is generally boron.Then photoresist is removed, the second conduction type is formed by annealing
Well layer 10；
J, growth regulation dioxide layer 18 after the first oxide layer 17 is removed on the first interarea 15 of semiconductor substrate, on the spot oxygen
Change layer, general field oxide thickness is 5000A-20000A；Photoresist is made, the second oxide layer 18 is defined and needs the area etched
Domain carries out photoetching, and the second oxide layer 18 of definition region is then removed by etching；
K, hard mask layer 20 is deposited on the first interarea 15 of semiconductor substrate, and is selectively sheltered and etched and is described hard
Mask layer 20 forms the hard mask window 21 of etching groove on the first interarea 15 of semiconductor substrate；
L, as shown in figure 23, semiconductor-based by dry etching on the first interarea 15 using above-mentioned hard mask window 21
Plate, forms groove above the 5th epitaxial layer of semiconductor substrate, and the groove includes cellular groove 5；
M, hard mask layer 20 is removed, three oxide layer 22 of growth regulation, i.e., sacrificial on the first interarea 15 of above-mentioned semiconductor substrate
Then domestic animal oxide layer removes sacrificial oxide layer by wet etching, continue on the first interarea 15 of above-mentioned half semiconductor substrate
Growth insulation gate oxide 6, insulation gate oxide 6 be covered on the first interarea 15, and be covered in cellular groove 5 side wall and
Bottom surface, and polysilicon depositing groove is formed in cellular groove 5；
N, conductive polycrystalline silicon body material layer is deposited on the first interarea 15 of above-mentioned semiconductor substrate, makes photoresist, is led to
It crosses lithographic definition to go out after conductive polycrystalline silicon needs the region that removes, passes through etching and remove conductive polycrystalline silicon, it is conductive to form T-slot grid
Polysilicon 7；
O, on the first interarea 15 of above-mentioned semiconductor substrate, photoresist is made, carries out emitter region photoetching, and inject the
One conductive type impurity ion, impurity are generally arsenic or phosphorus, are emitted by knot the first conduction type of formation after removing photoresist
Polar region 9；
P, insulating medium layer 12 is deposited on the first interarea 15 of above-mentioned semiconductor substrate, insulating medium layer 12 is covered in
First interarea 15 of semiconductor substrate；
Q, 13 lithography and etching of contact hole is carried out to above-mentioned insulating medium layer 12, it is equal in the both sides of cellular conductive polycrystalline Si-gate
Contact hole 13 is formed, the second conductive type impurity is injected and annealing forms P+ layers 11；
R, the first metal layer 23 is deposited on above-mentioned insulating medium layer 12, the first metal layer 23 is placed on insulating medium layer
It on 12, and is filled in contact hole 13, makes photoresist, define 23 region of the first metal layer for needing to remove, pass through etching
Form metal connecting line 14；Metal connecting line 14 and the first conductive type emitter region and P+ layers 11 form Ohmic contact.
S, passivation layer 25 is deposited on metal connecting line 14, passivation layer 25 generally comprises two be deposited on metal connecting line 14
Silicon oxide layer and the silicon nitride layer in the silicon dioxide layer；Photoresist is made on passivation layer 25, defines passivation layer
25 removal areas, the metal linear window 26 is formed by dry etching；
T, after the second interarea of above-mentioned semiconductor 16 is thinned to certain thickness, the first conductive-type is injected on the second interarea 16
Type impurity, impurity are generally phosphorus, then form the first conduction type field stop layer 2 by annealing.
U, the second conductive type impurity is injected on the second interarea 16, impurity is generally boron, then forms the by annealing
Two conductive type collector areas 1.
V, by evaporating or sputtering second metal layer 24 on the second interarea 16, second metal layer 24 is generally Al-Ti-
Ni-Ag, second metal layer 24 and the second conductive type collector area 1 form Ohmic contact.
The operation principle of this patent：By T-type trench gate structure IGBT, increased compared to conventional trench grid result IGBT
Channel width reduces saturation current, to improve short-circuit safety operation area.Additionally by beneath trenches, superjunction knot is set
Structure accelerates carrier extraction process, to reduce Eoff in turn off process.
The utility model is exemplarily described above in conjunction with attached drawing, it is clear that the utility model specific implementation not by
The limitation of aforesaid way, as long as using the methodology of the utility model and various unsubstantialities that technical solution carries out change
Into, or it is not improved the design of the utility model and technical solution are directly applied into other occasions, in the utility model
Protection domain within.
Claims (5)
1. a kind of IGBT device includes the member positioned at semiconductor substrate in the top plan view of the emitter of the IGBT device
Born of the same parents area and terminal protection area, the terminal protection area is located at the outer ring of cellular region, and terminal protection area is around encirclement cellular region, institute
It includes several regular arrays and the cellular being arranged in parallel that is mutually parallel to state in cellular region, on the section of the IGBT device, half
Conductor substrate has corresponding first interarea and the second interarea, and one layer of second conduction type collection is equipped with above second interarea
Electrode district, the second conductive type collector area top are equipped with the first conduction type field stop layer, it is characterised in that：The member
Cellular in born of the same parents area is equipped with groove structure, and the top in the first conductive type epitaxial layer is equipped with the second conduction type well layer, cellular
Groove is extended to through the second conduction type well layer in the first conductive type epitaxial layer in semiconductor substrate by the first interarea, described
Gate Electrode Conductive polysilicon is filled in cellular groove, the Gate Electrode Conductive polysilicon is covered to first near cellular groove notch
Above interarea, T-slot grid conductive polycrystalline silicon is formed, in the T-slot grid conductive polycrystalline silicon and the first interarea and cellular groove
Insulation gate oxide is equipped between wall.
2. IGBT device according to claim 1, it is characterised in that：It is led equipped with first above the side wall of adjacent cellular groove
Electric type emitter region, the first conductive type emitter region are located at the top of the second conduction type well layer, second conductive-type
The top of type well layer be equipped with P+ layers, the second conduction type well layer, P+ layers be equipped between the first conductive type epitaxial layer
Carrier accumulation layer, the first conductive type epitaxial layer between the cellular groove and the second interarea are interior equipped with P columns, the P columns
Immediately below cellular channel bottom, P columns depth is most deep can to go deep into the first conduction type field stop layer, but cannot pass through first
Conduction type field stop layer is in electrical contact with the second conductive type collector area.
3. IGBT device according to claim 2, it is characterised in that：It is covered on the T-slot grid conductive polycrystalline silicon absolutely
Edge dielectric layer, the insulating medium layer top are equipped with metal connecting line, and the metal connecting line passes through the contact hole on insulating medium layer
It is contacted with P+ layers and the first conductive type emitter region, passes through lead between the T-slot grid conductive polycrystalline silicon and metal connecting line
Hole and the filling metal connection in fairlead, are provided with passivation layer above the metal connecting line, on the passivation layer
Metal linear window equipped with bare metal line.
4. IGBT device according to claim 3, it is characterised in that：The doping of the first conduction type field stop layer is dense
Doping concentration of the degree more than or equal to the first conductive type epitaxial layer.
5. according to the IGBT device described in any one of claim 1-4, it is characterised in that：First conductive type epitaxial layer
Including at least one layer of epitaxial layer structure.
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| CN201721904369.0U CN207966999U (en) | 2017-12-29 | 2017-12-29 | A kind of IGBT device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| WO2020135138A1 (en) * | 2018-12-25 | 2020-07-02 | 广东美的白色家电技术创新中心有限公司 | Trench gate igbt and device |
-
2017
- 2017-12-29 CN CN201721904369.0U patent/CN207966999U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| CN107994069B (en) * | 2017-12-29 | 2024-03-15 | 安徽赛腾微电子有限公司 | IGBT device and manufacturing method thereof |
| WO2020135138A1 (en) * | 2018-12-25 | 2020-07-02 | 广东美的白色家电技术创新中心有限公司 | Trench gate igbt and device |
| US11764293B2 (en) | 2018-12-25 | 2023-09-19 | Guangdong Midea White Home Appliance Technology Innovation Center Co., Ltd. | Trench gate IGBT and device |
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