CN208674122U - A kind of superjunction IGBT with shield grid - Google Patents
A kind of superjunction IGBT with shield grid Download PDFInfo
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- CN208674122U CN208674122U CN201821366866.4U CN201821366866U CN208674122U CN 208674122 U CN208674122 U CN 208674122U CN 201821366866 U CN201821366866 U CN 201821366866U CN 208674122 U CN208674122 U CN 208674122U
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Abstract
The utility model discloses a kind of superjunction IGBT with shield grid; it includes semiconductor substrate; cellular region and terminal protection area, semiconductor substrate include the second conductive type collector area, the first conduction type field stop layer and at least one layer of first conductive type epitaxial layer；Cellular region includes the cellular that several are connected in parallel with each other, it includes several cellular grooves and the Gate Electrode Conductive polysilicon and shield grid that are filled in cellular groove, the notch two sides of cellular groove opposing gate conductive polycrystalline silicon and side wall are equipped with the 7th oxide layer, the 5th oxide layer is equipped between Gate Electrode Conductive polysilicon and shield grid, cellular groove is equipped with the 4th oxide layer with respect to the bottom and side wall of shield grid；P column is additionally provided in first conductive type epitaxial layer, one end of P column connects the second conduction type well layer, and the other end extends towards the first conduction type field stop layer.The utility model uses shielded gate structures, miller capacitance is reduced, to reduce switching loss.
Description
Technical field
The utility model relates to power semiconductor device technology field more particularly to a kind of superjunction with shield grid
IGBT。
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is big as high pressure
Main product in power power electronic device, with keeping updating for its structure, application range is also increasingly wider.
The key parameter of IGBT includes that time Tsc is born in conduction voltage drop Vce, switching loss Eoff and short circuit.In practical applications, I
Target be to obtain alap conduction voltage drop Vce and switching loss Eoff and time Tsc is born in longer short circuit.
It is proposed of the superjunction technology in power device, having broken reduces conduction voltage drop and improves pressure resistance in traditional silicon device
Contradiction, in superjunction IGBT, the N-type base area of device is highly doped by p-type and the highly doped structure being mixed to form of N-type, p-type are highly doped
Miscellaneous area forms P column, and N-type high-doped zone forms N column, different from the N-type base area of Uniform Doped in common power device, due to superjunction
IGBT uses N-type in N-type base area and p-type is alternately tied deeply, so that the field distribution in N-type base area tends to uniformly, to make N
As resistance to pressure area, the voltage that the resistance to pressure area of unit length can be born is remarkably enhanced for type base area.
However, although superjunction IGBT in terms of have very big improvement, as the requirement of application is got over
Come it is higher, it is higher and higher to the reduction amplitude requirement of conduction voltage drop Vce and switching loss Eoff, while to short-circuit safety operation area
It is required that also higher and higher, existing IGBT device also faces more and more challenges, therefore how to further decrease IGBT device
Conduction voltage drop and switching loss, while further increasing short circuit and bearing time Tsc as the important of those skilled in the art of the present technique
Research direction.
Utility model content
The purpose of this utility model is to provide a kind of superjunction with shield grid for above-mentioned deficiency in the prior art
IGBT, further decreases the conduction voltage drop and switching loss of device, while further increasing short circuit and bearing the time.
The utility model is used to solve the technical solution of the above technical problem are as follows: provides a kind of superjunction with shield grid
IGBT, including semiconductor substrate, the cellular region on the semiconductor substrate and the terminal positioned at the cellular region outer ring
Protection zone, the semiconductor substrate includes the second conductive type collector area, and is sequentially arranged in the second conduction type collection
The first conduction type field stop layer and at least one layer of first conductive type epitaxial layer above electrode district, it is described at least one layer of
Upper surface formation first interarea of first conductive type epitaxial layer far from second conductive type collector area, described at least one
The second conduction type well layer being arranged close to first interarea is additionally provided in first conductive type epitaxial layer of layer；The member
Born of the same parents area includes the cellular that several are connected in parallel with each other, and the cellular includes:
Several cellular grooves, one end are set on first interarea, and the other end extends to first conduction type
In epitaxial layer, the depth of the cellular groove is deeper than the second conduction type well layer；
Gate Electrode Conductive polysilicon is filled in each cellular groove, described in the Gate Electrode Conductive polysilicon covering
Cellular groove notch simultaneously extends to form Gate Electrode Conductive polysilicon along the notch two sides of first interarea towards the cellular groove
Extension；The notch two sides of the relatively described Gate Electrode Conductive polysilicon of the cellular groove and side wall are equipped with the 7th oxide layer；
Shield grid is set to below the Gate Electrode Conductive polysilicon, sets between the Gate Electrode Conductive polysilicon and shield grid
There is the 5th oxide layer；The bottom and side wall of the relatively described shield grid of cellular groove is equipped with the 4th oxide layer；It is described at least
P column is additionally provided in one layer of the first conductive type epitaxial layer, one end of the P column connects the second conduction type well layer,
The other end of the P column extends towards the first conduction type field stop layer.
Wherein, the one end of the P column far from the second conduction type well layer is terminated set on first conduction type field
It is connected in layer and in the first conduction type field stop layer.
Wherein, the first conductive type emitter region, first conductive-type are provided in the second conduction type well layer
Type emitter region is located at the second conduction type well layer top and is arranged close to the Gate Electrode Conductive polysilicon extension.
Wherein, the P+ being additionally provided in first conductive type epitaxial layer below the second conduction type well layer
Layer, is provided with carrier accumulation layer between first conductive type epitaxial layer and the second conduction type well layer and P+ layers.
Wherein, it is provided with insulating medium layer in the second conduction type well layer, offers position on the insulating medium layer
Contact hole in the Gate Electrode Conductive polysilicon extension two sides, the contact hole is through the insulating medium layer and through described the
It is extended to after one conductive type emitter region in P+ layers described.
Wherein, it is provided with metal connecting line on the insulating medium layer, the metal connecting line is towards the insulating medium layer
Side is used for and first conductive type emitter region and P+ layers towards extending and filling the contact hole in the contact hole
Form Ohmic contact.
Wherein, at least one layer of first conductive type epitaxial layer includes being sequentially arranged in the first conduction type field stop layer
First the first epitaxial layer of conduction type, first the second epitaxial layer of conduction type, the first conduction type third epitaxial layer, of top
The 5th epitaxial layer of one conduction type fourth epitaxial layer and the first conduction type, the upper table of the 5th epitaxial layer of the first conduction type
Face forms first interarea.
Implement a kind of superjunction IGBT with shield grid provided by the utility model, has the advantages that
The superjunction IGBT uses shielded gate structures, reduces miller capacitance, so that raising is opened and turn-off speed, reduces
Switching loss；Meanwhile the super-junction structure that the utility model uses can reduce drift zone resistance rate, to reduce conducting pressure
Drop, and super-junction structure and the second conduction type well layer are connected, and in turn off process, can increase substantially the extraction speed of carrier
Degree, so that switching loss further be greatly lowered.
Detailed description of the invention
Below in conjunction with accompanying drawings and embodiments, the utility model is described in further detail, in attached drawing:
Fig. 1 is the diagrammatic cross-section of superjunction IGBT provided by the embodiment of the utility model；
Fig. 2~Figure 12 is the process section of the specific manufacturing process of superjunction IGBT in Fig. 1；
Label in above-mentioned attached drawing is equal are as follows: the 1, second conductive type collector area；2, the first conduction type field stop layer；3,
First conductive type epitaxial layer；31, first the first epitaxial layer of conduction type；32, first the second epitaxial layer of conduction type；33,
One conduction type third epitaxial layer；34, the first conduction type fourth epitaxial layer；35, the 5th epitaxial layer of the first conduction type；41,
Second conduction type well layer；42, P+ layers；43, carrier accumulation layer；44, the first conductive type emitter region；51, cellular groove；
52, Gate Electrode Conductive polysilicon；53, shield grid；54, Gate Electrode Conductive polysilicon extension；55, the 4th oxide layer；56, the 5th oxidation
Layer；57, the 7th oxide layer；6, P column；7, insulating medium layer；71, contact hole；72, metal connecting line；73, metal linear window；8, blunt
Change layer；11, the first interarea；12, the second interarea；9, second metal layer；91, the second conductive-type moldeed depth knot.
Specific embodiment
In order to enable those skilled in the art that the utility model is more clearly understood, below in conjunction with attached drawing and specifically
Embodiment does further detailed description to the utility model.
Fig. 1 is the diagrammatic cross-section of superjunction IGBT provided by the embodiment of the utility model, as shown in Figure 1, the superjunction
IGBT includes semiconductor substrate, the cellular region on the semiconductor substrate, and the terminal positioned at the cellular region outer ring
Protection zone, the terminal protection area are surrounded around cellular region, and the terminal protection area can use existing conventional terminal protection
Plot structure, the present embodiment do not limit.
The semiconductor substrate includes: the second conduction type collector polar region 1, and is set in turn in the second conduction type
First conduction type field stop layer 2 of 1 top of collector polar region and at least one layer of first conductive type epitaxial layer 3.
Specifically, the first conductive type epitaxial layer 3 includes be sequentially arranged in 2 top of the first conduction type field stop layer first
Conduction type the first epitaxial layer 31, first conduction type the second epitaxial layer 32, the first conduction type third epitaxial layer 33, first are led
The 5th epitaxial layer 35 of electric type fourth epitaxial layer 34 and the first conduction type, and the doping of the first conduction type field stop layer 2 is dense
Degree is greater than the doping concentration of first the first epitaxial layer of conduction type 31.
Surface of the 5th epitaxial layer 35 of first conduction type far from the second conduction type collector polar region 1 is the semiconductor
First interarea 11 of substrate, the surface of the second conduction type collector polar region 1 are the second interarea 12 of the semiconductor substrate, i.e.,
The semiconductor substrate has the first interarea 11 and the second interarea 12 being oppositely arranged.
Positioned at 35 top of the 5th epitaxial layer of the first conduction type is additionally provided in the 5th epitaxial layer 35 of first conduction type
Two conduction type well layer 41 and the P+ layer 42 below the second conduction type well layer 41.First conduction type fourth epitaxial layer 34
Carrier accumulation layer 43 is additionally provided between the second conduction type well layer 41 and P+ layer 42, carrier accumulation layer 43 is for preventing
And the hole that P+ layer 42 launches is stored, and then significantly reduce conduction voltage drop；Since carrier accumulation layer 43 is close to P+ layer 42
Setting, when a switch is off, the hole of storage can quickly be taken away, can reduce switching loss.
The cellular region includes the cellular that several are connected in parallel with each other, and the specific structure of the cellular includes: several
It is provided with the cellular groove 51 of 3 top of the first conductive type epitaxial layer, one end of cellular groove 51 is set on the first interarea 11, separately
One end extends in the first conductive type epitaxial layer 3, and the depth of cellular groove 51 is deeper than the second conduction type well layer 41.
The cellular further includes the Gate Electrode Conductive polysilicon 52 and shield grid 53 being filled in cellular groove 51, wherein grid
Pole conductive polycrystalline silicon 52 is set to the upper area of cellular groove 51, and shield grid 53 is spaced grid conductive polycrystalline silicon 52 and is set to cellular ditch
The bottom section of slot 51.
Gate Electrode Conductive polysilicon 52 covers 51 notch of cellular groove and along the first interarea 11 towards 51 notch two of cellular groove
Side or side extend certain distance and form Gate Electrode Conductive polysilicon extension 54, and the grid between two neighboring cellular groove 51
Conductive polycrystalline silicon extension 54 is connected with each other.It is set on the notch two sides of 51 opposing gate conductive polycrystalline silicon 52 of cellular groove and side wall
There is the 7th oxide layer 57.Shield grid 53 is set to 52 lower section of Gate Electrode Conductive polysilicon, and shield grid 53 and Gate Electrode Conductive polysilicon 52
Between be equipped with the 5th oxide layer 56.Cellular groove 51 is equipped with the 4th oxide layer 55 with respect to the bottom and side wall of shield grid 53.
In the present embodiment, the quantity of each member cellular groove 51 intracellular is 2, and the depth of cellular groove 51 is 3
~7 μm, the 7th oxide layer 57 with a thickness of 500A~2000A, the thickness of the 5th oxide layer 56 is generally 2000A~15000A.
It should be noted that the 7th oxide layer 57, the 5th oxide layer 56 and the 4th oxide layer 55 in attached drawing 1 provided in this embodiment it
Between boundary line be intended merely to clearer differentiation, actual boundary more than the complexity provided in attached drawing 1, the present embodiment not with
Attached drawing 1 limits the positional relationship between three.
Further, P column 6, one end of P column 6 and the second conductive type of trap are additionally provided in the first conductive type epitaxial layer 3
Layer 41 connects, and the other end can be extended towards the first conduction type field stop layer 2, but cannot pass through the first conduction type field end
Only layer 2 is contacted with the second conductive type collector area 1.In the present embodiment, the one end of P column 6 far from the second conduction type well layer 41
Extend in towards the first conduction type field stop layer 2 and is connected with the first conduction type field stop layer 2.
It should be noted that above-mentioned P column 6 is connected with the second conduction type well layer 41, compares and be normally at beneath trenches
Floating super-junction structure, the utility model can increase substantially the extraction speed of carrier, thus greatly during switch OFF
Amplitude reduction switching loss.
Further, several the first conductive type emitter regions 44 are additionally provided in the second conduction type well layer 41, the
One conductive type emitter region 44 is located at 41 top of the second conduction type well layer, and more close to the Gate Electrode Conductive of each cellular groove
Crystal silicon extension 54 is arranged.
It is additionally provided with insulating medium layer 7 above second conduction type well layer 41, is covered on the extension of Gate Electrode Conductive polysilicon
54 top of portion.The contact hole 71 positioned at 54 two sides of Gate Electrode Conductive polysilicon extension, contact hole 71 are offered on insulating medium layer 7
Upper end run through the upper surface of insulating medium layer 7, the lower end of contact hole 71 is after insulating medium layer 7 towards extending in P+ layer 42
Setting, and contact hole 71 passes through corresponding first conductive type emitter region 44.
It is additionally provided with metal connecting line 72 on insulating medium layer 7, covers insulating medium layer 7, the bottom surface court of metal connecting line 72
Extend simultaneously filling contact hole 71 into contact hole 71.Wherein, metal connecting line 72 is through contact hole 71 and the first conduction type emitter
Area 44 and P+ floor 42 form Ohmic contact, and are electrically connected with Gate Electrode Conductive polysilicon 52.
In the present embodiment, electric connection between Gate Electrode Conductive polysilicon 52 and metal connecting line 72 can by fairlead and
Filling metal connection in fairlead.
It is additionally provided with passivation layer 8 on metal connecting line 72, passivation layer 8 is by being overlapped mutually the silicon dioxide layer and silicon nitride of setting
Layer composition.
In the present embodiment, the first conduction type is N-type, and the second conduction type is p-type.Also can in other embodiments are as follows:
First conduction type is p-type, and the second conduction type is N-type.
Further, in conjunction with shown in Fig. 1~Figure 12, the manufacturing method of the above-mentioned superjunction IGBT with shield grid includes following
Processing step:
S1, the semiconductor substrate with the first interarea 11 and the second interarea 12 is provided, is formed with P in the semiconductor substrate
Column 6；
Wherein, step S1 is specifically included:
S111, referring to figs. 1 and 2 is provided with first conduction type the first epitaxial layer 31 and the second interarea 12
Semiconductor substrate, first conduction type the first epitaxial layer 31 and the second interarea 12 are oppositely arranged；
S112, photoresist is made on first the first epitaxial layer of conduction type 31, the injection of P column 6 is gone out by lithographic definition
The second conductive type impurity is injected behind region, then removes photoresist；Wherein, second conductive type impurity is generally boron；
S113, as shown in connection with fig. 3, one the second extension of conduction type of growth regulation on first the first epitaxial layer of conduction type 31
Layer 32, then makes photoresist on first the second epitaxial layer of conduction type 32, the injection zone of P column 6 is gone out by lithographic definition
After inject the second conductive type impurity, then remove photoresist；Second conductive type impurity is generally boron；
S114, as shown in connection with fig. 4, the one conduction type third extension of growth regulation on first the second epitaxial layer of conduction type 32
Layer 33, then makes photoresist on the first conduction type third epitaxial layer 33, the injection zone of P column 6 is gone out by lithographic definition
After inject the second conductive type impurity, then remove photoresist；Second conductive type impurity is generally boron；
S115, as shown in connection with fig. 5, the one conduction type fourth epitaxial of growth regulation on the first conduction type third epitaxial layer 33
Layer 34, then makes photoresist in the first conduction type fourth epitaxial layer 34, the injection zone of P column 6 is gone out by lithographic definition
After inject the second conductive type impurity, then remove photoresist；Second conductive type impurity is generally boron；
S116, as shown in connection with fig. 6, the 5th extension of one conduction type of growth regulation in the first conduction type fourth epitaxial layer 34
Then layer 35 forms P column 6 by knot；The 5th epitaxial layer 35 of first conduction type is far from the first conduction type fourth epitaxial layer
34 upper surface forms the first interarea 11 of the semiconductor substrate.
Further, the manufacturing method further includes following processing step after end step S1:
S2, as shown in connection with fig. 7, one oxide layer of growth regulation on the first interarea 11, i.e. injection shielded layer, is then injected into first
Conductive type impurity, and carrier accumulation layer 43 is formed by annealing；Wherein, described to inject arriving with a thickness of 250A for shielded layer
500A, first conductive type impurity are generally phosphorus；
S3, as shown in connection with fig. 8, makes photoresist on the first interarea 11, goes out cellular region and termination environment by lithographic definition
Behind the region for needing to inject, the second conductive type impurity is injected, after removing photoresist, the second conductive-type moldeed depth is formed by annealing
Knot 91；Wherein, second conductive type impurity is generally boron；
S4, growth regulation dioxide layer, i.e. field oxide after the first oxide layer are removed on the first interarea 11, make photoetching
Glue defines the region that the second oxide layer needs to etch and carries out photoetching, then passes through the second oxidation of etching removal definition region
Layer；Wherein, the thickness of the field oxide is generally 5000A-20000A；
S5, as shown in connection with fig. 9, deposits hard mask layer on the first interarea 11, and selectively shelters and etch and is described hard
Mask layer forms the hard mask window for being used for etching groove on the first interarea 11, then utilizes above-mentioned hard mask window, the
By semiconductor substrate described in dry etching on one interarea 11, formation is recessed inwardly above the first conductive type epitaxial layer 3
Groove, the groove include several cellular grooves 51；
S6, the removal hard mask layer, make photoresist on the first interarea 11, go out what needs injected by lithographic definition
The second conductive type impurity is injected after second conduction type well region, and after removing photoresist, the second conduction type is formed by annealing
The upper end of well layer 41, P column 6 connects the second conduction type well layer 41；
S7, as shown in connection with fig. 10, three oxide layer of growth regulation, i.e. sacrificial oxide layer on the first interarea 11, then by wet
Method etching removal third oxide layer, and continue four oxide layer 55 of growth regulation, the 4th oxide layer 55 on the first interarea 11 and be covered in
The side wall and bottom surface of cellular groove 51, to form shield grid conductive polycrystalline silicon depositing groove in cellular groove 51；
S8, the deposition grid conductive polycrystalline silicon material layer on the first interarea 11 make photoresist, are gone out by lithographic definition
Behind the region that shield grid 53 needs to remove, by the shield grid conductive polycrystalline silicon material layer of etching removal definition region, screen is formed
Cover grid 53；
S9, in conjunction with shown in Figure 11, on the first interarea 11 deposit the 5th oxide layer, make photoresist, pass through lithographic definition
Behind the region that the 5th oxide layer needs to remove out, by the 5th oxide layer of etching removal definition region, the 5th oxide layer is formed
56, i.e. spacer insulator oxide layer；
S10, six oxide layer of growth regulation, i.e. sacrificial oxide layer on the first interarea 11, then remove institute by wet etching
The 6th oxide layer is stated, continues seven oxide layer 57 of growth regulation, i.e. gate oxide, the gate oxide on the first interarea 11 and is covered in
It on first interarea 11, and is covered on the side wall and the 5th oxide layer of cellular groove 51, to form grid in cellular groove 51
Conductive polycrystalline silicon depositing groove；
S11, Gate Electrode Conductive polysilicon material layer is deposited on the first interarea 11, make photoresist, gone out by lithographic definition
Behind the region that Gate Electrode Conductive polysilicon needs to remove, pass through the Gate Electrode Conductive polycrystalline silicon material of etching removal definition region
Layer, forms Gate Electrode Conductive polysilicon 52, and the top of Gate Electrode Conductive polysilicon 52 is along the first interarea 11 towards the slot of cellular groove 51
Extend to form Gate Electrode Conductive polysilicon extension 54 mouthful two layers；
S12, in conjunction with shown in Figure 12, make photoresist on the first interarea 11, carry out emitter region photoetching, and inject first
Conductive type impurity after removing photoresist, forms the first conductive type emitter region 44 of cellular region by knot；
S13, deposit forms insulating medium layer 7 on the first interarea 11, and insulating medium layer 7 is covered in the semiconductor substrate
The first interarea 11 on, then to insulating medium layer 7 carry out lithography and etching, in the two sides of Gate Electrode Conductive polysilicon extension 54
Contact hole 71 is formed, injects the second conductive type impurity to 71 bottom of contact hole, and anneal and form P+ layer 42；Insulating medium layer 7
By including but is not limited to that silica glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) material are made；
S14, the first metal layer is deposited on insulating medium layer 7, the first metal layer is covered on insulating medium layer 7 simultaneously
It is filled in contact hole 71；Photoresist is made, after the region that the first metal layer needs to remove is gone out by lithographic definition, passes through etching
The first metal layer for removing definition region forms metal connecting line 72, metal connecting line 72 and the first conductive type emitter region 44 and P+
Layer 42 forms Ohmic contact；
S15, passivation layer 8 is deposited on metal connecting line 72, and make photoresist on passivation layer 8, define metal wire window
Mouthful, metal linear window 73 is formed by dry etching；Wherein, the passivation layer includes two be successively deposited on metal connecting line 72
Silicon oxide layer and the silicon nitride layer in the silicon dioxide layer；
S16, after the second interarea 12 is thinned to certain thickness, the first conductive type impurity is injected simultaneously on the second interarea 12
Annealing forms the first conduction type field stop layer 2；One end direction first conductive-type of the P column 6 far from the second conduction type well layer 41
Type field stop layer 2 extends；
S17, the second conductive type impurity is injected on the second interarea 12 and is annealed, form the second conductive type collector area
1；
S18, second metal layer formed by evaporation or sputtering on the second interarea 12, second metal layer and the second conductive-type
Type collector area 1 forms Ohmic contact；Wherein, the second metal layer is generally Al-Ti-Ni-Ag metal.
In the present embodiment, the first conduction type is N-type, and the second conduction type is p-type.Also can in other embodiments are as follows:
First conduction type is p-type, and the second conduction type is N-type.
In conclusion a kind of superjunction IGBT with shield grid provided by the utility model has the advantages that
(1) the Gate Electrode Conductive polysilicon structure that the utility model uses extends the channel length of cellular groove, reduces
Saturation current increases short circuit current safety operation area so that improving short circuit bears the time；
(2) the utility model uses shielded gate structures, reduces miller capacitance, improve switch opens and turn off speed
Degree, reduces switching loss；
(3) the utility model uses super-junction structure, drift zone resistance rate can be reduced, to reduce conduction voltage drop；Simultaneously
In device shutdown, because super-junction structure can accelerate carrier to extract speed, to reduce switching loss；
(4) super-junction structure and the first conduction type well layer that the utility model uses are connected, and compare positioned at beneath trenches
Floating super-junction structure the extraction speed of carrier can be increased substantially, thus further significantly during switch OFF
Reduce switching loss.
Above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to aforementioned reality
Example is applied the utility model is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and model of various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (7)
1. a kind of superjunction IGBT with shield grid, including semiconductor substrate, the cellular region on the semiconductor substrate with
And the terminal protection area positioned at the cellular region outer ring, the semiconductor substrate include the second conductive type collector area, and
The the first conduction type field stop layer and at least one layer of first being sequentially arranged in above second conductive type collector area are led
Electric type epitaxial layer, at least one layer of first conductive type epitaxial layer is far from the upper of second conductive type collector area
Surface forms the first interarea, is additionally provided at least one layer of first conductive type epitaxial layer close to first interarea and sets
The the second conduction type well layer set；The cellular region includes the cellular that several are connected in parallel with each other, which is characterized in that the member
Born of the same parents include:
Several cellular grooves, one end are set on first interarea, and the other end extends to the first conduction type extension
In layer, the depth of the cellular groove is deeper than the second conduction type well layer；
Gate Electrode Conductive polysilicon is filled in each cellular groove, and the Gate Electrode Conductive polysilicon covers the cellular
Groove notch simultaneously extends to form the extension of Gate Electrode Conductive polysilicon along the notch two sides of first interarea towards the cellular groove
Portion；The notch two sides of the relatively described Gate Electrode Conductive polysilicon of the cellular groove and side wall are equipped with the 7th oxide layer；
Shield grid is set to below the Gate Electrode Conductive polysilicon, and the is equipped between the Gate Electrode Conductive polysilicon and shield grid
Five oxide layers；The bottom and side wall of the relatively described shield grid of cellular groove is equipped with the 4th oxide layer；At least one layer
The first conductive type epitaxial layer in be additionally provided with P column, one end of the P column connects the second conduction type well layer, the P
The other end of column extends towards the first conduction type field stop layer.
2. superjunction IGBT according to claim 1, which is characterized in that the P column is far from the second conduction type well layer
One end be set to the first conduction type field stop layer in and in the first conduction type field stop layer connect.
3. superjunction IGBT according to claim 1, which is characterized in that be provided with first in the second conduction type well layer
Conductive type emitter region, first conductive type emitter region are located at the second conduction type well layer top and close to institutes
State the setting of Gate Electrode Conductive polysilicon extension.
4. superjunction IGBT according to claim 3, which is characterized in that be additionally provided in first conductive type epitaxial layer
P+ layer below the second conduction type well layer, first conductive type epitaxial layer and second conductive type of trap
Carrier accumulation layer is provided between layer and P+ layers.
5. superjunction IGBT according to claim 4, which is characterized in that be provided with insulation in the second conduction type well layer
Dielectric layer offers the contact hole positioned at the Gate Electrode Conductive polysilicon extension two sides on the insulating medium layer, described to connect
Contact hole through the insulating medium layer and extends in P+ layers described after first conductive type emitter region.
6. superjunction IGBT according to claim 5, which is characterized in that it is provided with metal connecting line on the insulating medium layer,
The metal connecting line towards the side of the insulating medium layer towards the contact hole in extend and fill the contact hole, be used for
With first conductive type emitter region and P+ layers of formation Ohmic contact.
7. superjunction IGBT according to claim 1, which is characterized in that at least one layer of first conductive type epitaxial layer
Including first the first epitaxial layer of conduction type, the first conduction type second being sequentially arranged in above the first conduction type field stop layer
Epitaxial layer, the first conduction type third epitaxial layer, the 5th epitaxial layer of the first conduction type fourth epitaxial layer and the first conduction type,
The upper surface of the 5th epitaxial layer of first conduction type forms first interarea.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037312A (en) * | 2018-08-23 | 2018-12-18 | 惠州市乾野微纳电子有限公司 | A kind of superjunction IGBT and its manufacturing method with shield grid |
| CN113497132A (en) * | 2020-04-07 | 2021-10-12 | 苏州华太电子技术有限公司 | Super junction insulated gate bipolar transistor and manufacturing method thereof |
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2018
- 2018-08-23 CN CN201821366866.4U patent/CN208674122U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037312A (en) * | 2018-08-23 | 2018-12-18 | 惠州市乾野微纳电子有限公司 | A kind of superjunction IGBT and its manufacturing method with shield grid |
| CN109037312B (en) * | 2018-08-23 | 2024-04-09 | 无锡市乾野微纳科技有限公司 | Super-junction IGBT with shielding grid and manufacturing method thereof |
| CN113497132A (en) * | 2020-04-07 | 2021-10-12 | 苏州华太电子技术有限公司 | Super junction insulated gate bipolar transistor and manufacturing method thereof |
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