CN205488135U - IGBT device with charge carrier storage structure - Google Patents
IGBT device with charge carrier storage structure Download PDFInfo
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- CN205488135U CN205488135U CN201620229014.5U CN201620229014U CN205488135U CN 205488135 U CN205488135 U CN 205488135U CN 201620229014 U CN201620229014 U CN 201620229014U CN 205488135 U CN205488135 U CN 205488135U
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Abstract
The utility model relates to a IGBT device with charge carrier storage structure, its active area adopts the groove structure, is equipped with the 2nd conductivity type tagma in a conductivity type drift region of active area, and the cellular slot lies in the 2nd conductivity type tagma, and the degree of depth stretches into in the conductivity type drift region of the 2nd conductivity type tagma below, be equipped with the charge carrier storage structure in a conductivity type drift region of active area, the charge carrier storage structure is including being used for stretching into the conductivity type charge carrier storage district that a conductivity type drift region inside and outside wall surrounded entirely with the cellular slot, and the doping concentration in conductivity type charge carrier storage district is greater than the doping concentration of a conductivity type drift region. The utility model discloses can satisfy lower pressure drop and the extremely fast shutoff characteristic of switching on simultaneously to can distinguish withstand voltage puncture position adjustment to the cellular guaranteeing, in order to guarantee higher anti voltage surge ability, not increase the chip manufacture cost, reduce chip area.
Description
Technical field
This utility model relates to a kind of IGBT device, a kind of IGBT device with carrier storage organization, belongs to the technical field of IGBT device.
Background technology
The full name of IGBT is Insulate Gate Bipolar Transistor, i.e. igbt, and it has the multiple advantages of MOSFET and GTR concurrently, extends the application of power semiconductor greatly.As the main representative of Novel power semiconductor device, IGBT is widely used in industry, information, new forms of energy, medical science, traffic, military affairs and aviation field.The advantages such as IGBT is one of currently the most important ones power device, and IGBT is high owing to having input impedance, and on-state voltage drop is low, and drive circuit is simple, safety operation area width, and current handling capability is strong, increasingly cause the attention of people in various power switch are applied.IGBT device is at motor control, IF switch power supply and inverter, robot, air-conditioning and requires that quick low-loss many fields have a wide range of applications.
Saturation voltage drop (Vcesat), impact resistance and the voltage endurance of IGBT is the several important indicators weighing IGBT device.Saturation voltage drop is the important parameter weighing IGBT product conduction loss, reduces IGBT saturation voltage drop and can effectively reduce IGBT power attenuation, reduces product heating, improves power conversion efficiency.Voltage endurance is one of most important parameters of product, and pressure deficiency may cause IGBT device to occur when using puncturing the risk burnt.One of major embodiment of IGBT product impact resistance is exactly product anti-short circuit capability, is the important parameter index embodying product reliability.
In order to improve IGBT properties of product, the method for multiple optimization IGBT structure and technique is suggested, the most representational improved structure as disclosed in the file that notification number is CN 204144266U；Described open file proposes to be provided with the second conductivity type regions inactive area not contacted with emitter metal being parallel to trench gate direction, and this region is floating state；When IGBT forward conduction, minority carrier can effectively strengthen conductivity modulation effect in the accumulation formed below of this region, reduces conduction voltage drop (Vcesat).But also there is open defect in described open file.The existence being primarily due to floating state the second conductivity type regions inactive area reduces gully density so that it is limited that conduction voltage drop (Vcesat) reduces amount；Secondly, owing to the second conductivity type regions inactive area is floating state, when device bears pressure, second conduction type active region is inconsistent with inactive area current potential, therefore the second conduction type inactive area exhaust speed can be substantially slow with the second conduction type active region, when the second conduction type active region width is close or larger than the second conduction type inactive area width, depletion layer can be gone out and substantially be bent, and product is pressure, and meeting significantly reduces.
In light of the shortcomings of the prior art, one can effectively improve IGBT performance, and with existing IGBT process compatible, do not increase product technology difficulty and the IGBT device of process costs and manufacturing process be extremely necessary.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of IGBT device with carrier storage organization is provided, its compact conformation, relatively low conduction voltage drop (Vceon) and the turn-off characteristic being exceedingly fast can be met simultaneously, and by ensureing, pressure puncture place can be adjusted to cellular region, to ensure higher reactance voltage surge capacity, not increase chip manufacturing cost, reduce chip area, safe and reliable.
The technical scheme provided according to this utility model; the described IGBT device with carrier storage organization; in the top plan view of described IGBT device; including the active area being positioned on semiconductor substrate and terminal protection district; described active area is positioned at the center of semiconductor substrate, and terminal protection district is positioned at the outer ring of active area and around surrounding described active area；On the cross section of described IGBT device, semiconductor substrate has two relative interareas, and described interarea includes the first interarea and second interarea corresponding with the first interarea, includes the first conduction type drift region between the first interarea of semiconductor substrate and the second interarea；
On the cross section of described IGBT device, active area uses groove structure, it is provided with the second conductivity type body region in the first conduction type drift region of active area, second conductivity type body region is positioned at the top of the first conduction type drift region, cellular groove is positioned at the second conductivity type body region, and the degree of depth stretches in the first conduction type drift region below the second conductivity type body region；
It is provided with carrier storage organization in the first conduction type drift region of active area, described carrier storage organization includes for cellular groove stretches into the first conduction type carrier memory block that the first conduction type drift region inside and outside wall surrounds entirely, and the doping content of the first conduction type carrier memory block is more than the doping content of the first conduction type drift region.
Sidewall and diapire growth at described cellular groove have insulated gate oxide layer, are filled with Gate Electrode Conductive polysilicon in growth has the cellular groove of insulated gate oxide layer, and the notch of cellular groove is covered by insulating medium layer；It is arranged over the first conduction type launch site in adjacent cellular groove lateral wall, described first conduction type launch site is positioned at the second conductivity type body region, first conduction type launch site contacts with the lateral wall of cellular groove, described first conduction type launch site, the second conductivity type body region all with the emitter metal Ohmic contact on semiconductor substrate the first interarea, emitter metal is isolated by the Gate Electrode Conductive polysilicon insulation in insulating medium layer and cellular groove.
Being additionally provided with the second conduction type bonding pad, the second conduction type bonding pad and emitter metal Ohmic contact in described second conductivity type body region, the second conductivity type body region is electrically connected with emitter metal by the second conduction type bonding pad；Gate Electrode Conductive polysilicon electrically connects with the gate metal above semiconductor substrate the first interarea.
On the cross section of described IGBT device; terminal protection district includes that the second conduction type protection ring, the first conduction type end ring and for forming the second conduction type interface of main knot; described second conduction type interface and the cellular trench contact of adjacent terminals protection zone in active area; second conduction type protection ring is positioned at the second conduction type interface and the first conduction type cut-off interannular; first conduction type cut-off ring is positioned at the outer ring in terminal protection district, the first conduction type cut-off ring and the cut-off ring metal ohmic contact on semiconductor substrate the first interarea.
Described second conduction type interface and the second conduction type protection ring are that same technique manufactures layer; first interarea in terminal protection district is additionally provided with block media floor; be also covered with insulating medium layer on described block media layer, cut-off ring metal be supported on on insulating medium layer.
The second conduction type collecting zone, described second conduction type collecting zone and the collector electrode metal Ohmic contact on semiconductor substrate the second interarea it is additionally provided with in described first conduction type drift region.
The first conduction type electric field cutoff layer it is additionally provided with in described first conduction type drift region, described first conduction type electric field cutoff layer adjoins the first conduction type drift region and the second conduction type collecting zone, and the doping content of the first conduction type electric field cutoff layer is more than the doping content of the first conduction type drift region.
In both described " the first conduction type " and " the second conduction type ", for N-type insulated gate bipolar transistor, the first conduction type refers to N-type, and the second conduction type is p-type；For p-type insulated gate bipolar transistor IGBT, the type of the first conduction type and the second conduction type indication and N-type insulated gate bipolar transistor IGBT contrast.
Compared with prior art, advantage of the present utility model is:
1, when IGBT forward conduction, surround the first conduction type carrier memory block of cellular channel bottom, owing to the existence of Built-in potential can hinder the minority carrier circulation to emitter stage, the accumulation of minority carrier can be formed, conductivity modulation effect strengthens, IGBT saturation voltage drop can be substantially reduced, reduce conduction loss；
2, when IGBT forward blocking, owing to surrounding the doping content doping content higher than the first conduction type drift region of the first conduction type carrier memory block of cellular channel bottom, peak surface electric field reduces further, the puncture place of whole IGBT device is evenly distributed in active area, improves the impact resistance of IGBT device further；
3, in above-mentioned IGBT manufacture method, injecting formation the first conduction type carrier memory block by carrying out the first conductive type impurity in the bottom of cellular groove, process costs does not have the biggest change；
That 4, can cellular density be done is bigger, can suitably reduce chip area, reduce further chip cost.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Fig. 2 ~ Fig. 9 is that this utility model concrete technology implements step sectional view, wherein
Fig. 2 is the sectional view of this utility model semiconductor substrate.
Fig. 3 is the sectional view after this utility model obtains hard mask layer.
Fig. 4 is the sectional view after this utility model obtains hard mask window.
Fig. 5 is the sectional view after this utility model obtains cellular groove.
Fig. 6 is the sectional view after this utility model obtains N+ carrier memory block.
Fig. 7 is the sectional view after this utility model obtains P body district.
Fig. 8 is the sectional view after this utility model obtains emitter metal, gate metal and cut-off ring metal.
Fig. 9 is the sectional view after this utility model obtains collector electrode metal.
Description of reference numerals: 1-N type drift region, 2-P type protection ring, 3-block media layer, 4-insulating medium layer, 5-cellular groove, 6-N+ carrier memory block, 7-insulated gate oxide layer, 8-Gate Electrode Conductive polysilicon, 9-P body district, 10-N+ launch site, 11-P+ bonding pad, 12-gate metal, 13-emitter metal, 14-ends ring metal, 15-N type electric field cutoff layer, 16-P type collecting zone, 17-collector electrode metal, 18-active area, 19-terminal protection district, 20-polysilicon connector, 21-P type interface, 22-N+ ends ring and the hard mask window of 23-and 24-hard mask layer.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the utility model is described in further detail.
As shown in Fig. 1 and Fig. 9: in order to meet relatively low conduction voltage drop (Vceon) and the turn-off characteristic being exceedingly fast simultaneously, and by ensureing, pressure puncture place can be adjusted to cellular region, to ensure higher reactance voltage surge capacity, do not increase chip manufacturing cost, as a example by N-type IGBT device, this utility model is in particular: in the top plan view of described IGBT device, including the active area 18 being positioned on semiconductor substrate and terminal protection district 19, described active area 18 is positioned at the center of semiconductor substrate, terminal protection district 19 is positioned at the outer ring of active area 18 and around surrounding described active area 18；On the cross section of described IGBT device, semiconductor substrate has two relative interareas, and described interarea includes the first interarea and second interarea corresponding with the first interarea, includes N-type drift region 1 between the first interarea of semiconductor substrate and the second interarea；
On the cross section of described IGBT device, active area 18 uses groove structure, is provided with PXing Ti district 9 in the N-type drift region 1 of active area, and PXing Ti district 9 is positioned at the top of N-type drift region 1, cellular groove 5 is positioned at PXing Ti district 9, and the degree of depth stretches in the N-type drift region 1 below PXing Ti district 9；
Carrier storage organization it is provided with in the N-type drift region 1 of active area 18, described carrier storage organization includes for cellular groove 5 stretches into the N+ carrier memory block 6 that N-type drift region 1 inside and outside wall surrounds entirely, and the doping content of N+ carrier memory block 6 is more than the doping content of N-type drift region.
Specifically; active area 18 is positioned at the central area of semiconductor substrate; terminal protection district 19 is surrounded with source region 18; by active area 18 for forming the functional areas of IGBT device; being used for protecting active area 18, active area 18 to use groove structure by terminal protection district 19, the cellular in active area 18 passes through Gate Electrode Conductive polysilicon 8 parallel connection in one; matching relationship between active area 18 and terminal protection district 19 is that known to those skilled in the art, here is omitted.Semiconductor substrate can use the material that the art is conventional, such as silicon etc., the first interarea is generally the front of semiconductor substrate, and the second interarea is generally the back side of semiconductor substrate, it is positioned between the first interarea and the second interarea in N-type drift region 1, specially known to those skilled in the art.
Some active cellulars are included in active area 18, when using groove structure, active cellular includes cellular groove 5, cellular groove 5 passes perpendicularly through PXing Ti district 9, the bottom land of cellular groove 5 is positioned at the N-type drift region 1 below PXing Ti district 9, and the degree of depth of cellular groove 5 is not more than the thickness of N-type drift region 1, and PXing Ti district 9 is p-well, the N-type drift region 1 of active area 18 is crossed in PXing Ti district 9, and JiPXing Ti district 9 is positioned between adjacent cellular groove 5.
In this utility model embodiment, in carrier storage organization, the quantity of N+ carrier memory block 6 can be consistent with the quantity of cellular groove 5, all there is N+ carrier memory block 6 in the i.e. bottom at each cellular groove 5, each N+ carrier memory block 6 surrounds the bottom of corresponding cellular groove 5, i.e. by N+ carrier memory block 6, cellular groove 5 is positioned at the region part below PXing Ti district 9 entirely to surround, now, the part that cellular groove 5 is positioned at below PXing Ti district 9 is mutually isolated with N-type drift region 1 by N+ carrier memory block 6.In addition, when preparing N+ carrier memory block 6, adjacent N+ carrier memory block 6 can also be connected with each other, in the N-type drift region 1 of active area 1, i.e. form one piece of N+ carrier memory block 6, no matter in carrier storage organization, which kind of form N+ carrier memory block 6 uses, and is required to the region by cellular groove 5 is positioned at below PXing Ti district 9 and entirely surrounds.The doping content of N+ carrier memory block 6 is more than the doping content of N-type drift region 1.After adjacent N+ carrier memory block 6 is connected with each other, in the carrier storage organization formed, being perpendicular to cellular groove 5 length and be parallel on the length direction of cellular groove 5, in carrier storage organization, n-type doping concentration is non-equally distributed.
After carrier storage organization is set in N-type drift region 1, when IGBT forward conduction, surround the N+ carrier memory block 6 existence obstruction minority carrier circulation to emitter stage due to Built-in potential of cellular groove 5 bottom, the accumulation of minority carrier can be formed, conductivity modulation effect strengthens, IGBT saturation voltage drop can be substantially reduced, reduce conduction loss.When IGBT forward blocking, the doping content of the N+ carrier memory block 6 surrounding cellular groove 5 bottom is higher than the doping content of N-type drift region 1, peak surface electric field reduces further, the puncture place of whole device is evenly distributed in active area 18, it is thus possible to the impact resistance of the device improved further.
Further, sidewall and diapire growth at described cellular ditch 5 groove have insulated gate oxide layer 7, are filled with Gate Electrode Conductive polysilicon 8 in growth has the cellular groove 5 of insulated gate oxide layer 7, and the notch of cellular groove 5 is covered by insulating medium layer 4；It is arranged over N+ launch site 10 in adjacent cellular groove 5 lateral wall, described N+ launch site 10 is positioned at PXing Ti district 9, N+ launch site 10 contacts with the lateral wall of cellular groove 5, described N+ launch site 10, PXing Ti district 9 all with emitter metal 13 Ohmic contact on semiconductor substrate the first interarea, emitter metal 13 is dielectrically separated from the Gate Electrode Conductive polysilicon 8 in cellular groove 5 by dielectric 4.
In this utility model embodiment, insulated gate oxide layer 7 can cover at the sidewall of cellular groove 5 and diapire by the growth of the technique such as thermal oxide, Gate Electrode Conductive polysilicon 8 is filled in cellular groove 5, Gate Electrode Conductive polysilicon 8 is dielectrically separated from by sidewall and the diapire of insulated gate oxide layer 7 with cellular groove 5, insulating medium layer 4 covers the notch of cellular groove 5, the width of insulating medium layer 4 is more than the width of rebate of cellular groove 5, thus the Gate Electrode Conductive polysilicon 8 in cellular groove 5 can be dielectrically separated from emitter metal 13 by insulating medium layer 4.There is the region between adjacent cellular groove 5 above lateral wall in N+ launch site 10, N+10 launch site 10 is positioned at PXing Ti district 9.
Being additionally provided with P+ bonding pad 11, P+ bonding pad 11 and emitter metal 13 Ohmic contact in described PXing Ti district 9, PXing Ti district 9 is electrically connected with emitter metal 13 by P+ bonding pad 11；Gate Electrode Conductive polysilicon 8 electrically connects with the gate metal 12 above semiconductor substrate the first interarea.
In this utility model embodiment, in order to reduce contact resistance, being additionally provided with P+ bonding pad 11, P+ bonding pad 11 and emitter metal 13 Ohmic contact in PXing Ti district 9, PXing Ti district 9 is electrically connected with emitter metal 13 by P+ bonding pad 11.The doping content of P+ bonding pad 11 is more than the doping content in PXing Ti district 9.Gate Electrode Conductive polysilicon 8 electrically connects with gate metal 12, and Gate Electrode Conductive polysilicon in active area 18 8 is electrically connected with gate metal 12 after being connected by polysilicon connector 20, with by Gate Electrode Conductive polysilicon 8 parallel connection in one.
On the cross section of described IGBT device; terminal protection district 19 includes p-type protection ring 2, N+ cut-off ring 22 and for forming the p-type interface 21 of main knot; described p-type interface 21 contacts with the cellular groove 5 of adjacent terminals protection zone 19 in active area 18; p-type protection ring 2 is positioned between p-type interface 21 and N+ cut-off ring 22; N+ cut-off ring 22 is positioned at the outer ring in terminal protection district 19, N+ cut-off ring 22 and cut-off ring metal 14 Ohmic contact on semiconductor substrate the first interarea.
In this utility model embodiment; terminal protection district 19 can arrange one or more p-type protection ring 2; p-type protection ring 2 is surrounded with source region 18; in order to realize transition; p-type interface 21 is set in terminal protection district 19; p-type interface 21 is by forming main knot with the N-type drift region 1 of lower section, and p-type interface 21 contacts with the lateral wall of the cellular groove 5 of adjacent terminals protection zone 19.N+ cut-off ring 22 is positioned at the edge of outer ring, terminal protection district 19, and N+ cut-off ring 22 is around p-type protection ring 2, N+ cut-off ring 22 and cut-off ring metal 14 Ohmic contact.
Described p-type interface 21 and p-type protection ring 2 be that same technique manufactures layer, be additionally provided with block media floor 3, described block media layer 3 is also covered with insulating medium layer 4 on first interarea in terminal protection district 19, end ring metal 14 be supported on on insulating medium layer 4.
In this utility model embodiment, block media layer 3 can be silicon dioxide layer, and 3, block media floor covers on first interarea in terminal protection district 19, and insulating medium layer 4, in addition to covering the notch of cellular groove 5, also covers on block media layer 3.Cut-off ring metal 14 is partially supported upon on insulating medium layer 4.
P-type collecting zone 16, described p-type collecting zone 16 and collector electrode metal 17 Ohmic contact on semiconductor substrate the second interarea it is additionally provided with in described N-type drift region 1.
Being additionally provided with N-type electric field cutoff layer 15 in described N-type drift region 1, described N-type electric field cutoff layer 15 adjoins N-type drift region 1 and p-type collecting zone 16, and the doping content of N-type electric field cutoff layer 15 is more than the doping content of N-type drift region 1.
In this utility model embodiment, the colelctor electrode of IGBT device can be formed by p-type collecting zone 16 and collector electrode metal 17, in the specific implementation, p-type collecting zone 16 can be continuous print, can also be discrete, when p-type collecting zone 16 is discontinuous, N-type drift region 1 part and collector electrode metal 17 Ohmic contact.P-type collecting zone 16 consecutive hours, p-type collecting zone 16 crosses N-type drift region 1.P-type collecting zone 16 can also be connected with N-type drift region 1 by N-type electric field cutoff layer 15.
As shown in Fig. 2 ~ Fig. 9, the above-mentioned IGBT device with carrier storage organization, can be prepared by following concrete technology step, specifically, described IGBT device manufacture method comprises the steps:
Step a, offer have two semiconductor substrates with opposing main faces, and said two opposing main faces includes the first interarea and second interarea corresponding with the first interarea, includes N-type drift region 1 between the first interarea and the second interarea；
Specifically, the material of described semiconductor substrate includes silicon, it is of course also possible to use the semi-conducting material that other are conventional, the front of semiconductor substrate forms the first interarea, and the back side of semiconductor substrate forms the second interarea, as shown in Figure 2.
Step b, on the first interarea of above-mentioned semiconductor substrate, carry out the injection of p type impurity ion, with in the terminal protection district 19 of semiconductor substrate formed needed for p-type interface 21 and p-type protection ring 2；
Specifically; the p type impurity ion of described injection can be boron ion etc.; when carrying out p type impurity ion implanting; photoresist etc. can be coated on the first interarea of active area 18 to block; p type impurity ion is only injected in terminal protection district 19; and in terminal protection district 19, form p-type interface 21 and some p-type protection rings 2; the quantity of p-type protection ring 2 and p-type interface 21, the p-type protection ring 21 degree of depth in N-type drift region 1 all can carry out selecting control by technique; specific embodiment is to know described in those skilled in the art, and here is omitted.
Step c, block media layer 3 is set on the first interarea of above-mentioned semiconductor substrate, and removes the block media layer 3 on active area 18 first interarea, to obtain the block media floor 3 on terminal protection district 19 first interarea；
In this utility model embodiment, after preparing p-type interface 21 and p-type protection ring 2, by techniques such as thermal oxides, on the first interarea, growth obtains block media layer 3, and block media layer 3 can be silicon dioxide layer.Remove the block media layer 3 on active area 18 first interarea; only retain and be positioned at the block media floor 3 on terminal protection district 19 first interarea; thus utilize block media floor 3 can terminal protection district 19 be blocked; it is convenient for follow-up processing step to perform; the process specifically arranging block media layer 3 and part removal block media layer 3 is that known to those skilled in the art, here is omitted.
Step d, arranging hard mask layer 24 on the first interarea of above-mentioned semiconductor substrate, described hard mask layer 24 covers on the first interarea of active area 18 and the block media floor 3 in terminal protection district 19；
In this utility model embodiment, the processing step using the art conventional prepares hard mask layer 24, and described hard mask layer covers on the block media floor 3 on first interarea and terminal protection district 19 of active area 18, as shown in Figure 3.
Step e, optionally shelter and etch above-mentioned hard mask layer 24, to obtain the hard mask window 23 of through hard mask layer 24；
In this utility model embodiment, hard mask layer 24 is performed etching by the processing step using the art conventional, to obtain hard mask window 23, described hard mask window 23 is positioned at the top of active area 18 first interarea, the first interarea making active area 18 corresponding by hard mask window 23 is exposed, as shown in Figure 4.
Step f, utilizing above-mentioned hard mask window 23 to perform etching the first interarea of active area 18, to obtain required cellular groove 5 in active area 18, described cellular groove 5 extends vertically downward in N-type drift region 1 from the first interarea of active area 18；
In this utility model embodiment, after making corresponding first interarea of active area 18 exposed by hard mask window 23, utilizing the first interarea to semiconductor substrate to carry out etching groove, concrete etching process is that known to those skilled in the art, here is omitted.The degree of depth of cellular groove 5 is less than the thickness of N-type drift region 1, and the notch of cellular groove 5 is positioned on the first interarea, thus obtains some cellular grooves 5 in active area 18, as shown in Figure 5.
Step g, on the first interarea of above-mentioned semiconductor substrate, inject N-type impurity ion, and after pushing away trap, form required N+ carrier memory block 6, and after forming N+ carrier memory block 6, remove above-mentioned hard mask layer 24；
In this utility model embodiment, masking action due to hard mask layer 24, when carrying out N-type impurity ion implanting, N-type impurity ion only can be infused in around the region below cellular groove 5 bottom land, and N-type impurity ion can be phosphonium ion etc., after injecting N-type impurity ion, by pushing away the processing steps such as trap, can form N+ carrier memory block 6, described N+ carrier memory block 6 surrounds cellular groove 5 corresponding region part, as shown in Figure 6.After obtaining N+ carrier memory block 6, hard mask layer 24 is removed by Conventional process steps, being known to those skilled in the art by the process of N-type impurity ion implanting formation N+ carrier memory block 6 and the process of removal hard mask layer 24, here is omitted.In the specific implementation, surround and can be connected with each other between the N+ carrier memory block 6 of cellular groove 5 lower area, it is also possible to separate existence, specifically can be realized by corresponding technology controlling and process, specific embodiment is that known to those skilled in the art, here is omitted.
Step h, utilize convention trench grid technique, successively in sidewall and the diapire growth insulated gate oxide layer 7 of cellular groove 5, and in growth has the cellular groove 5 of insulated gate oxide layer 7, fill Gate Electrode Conductive polysilicon 8, and PXing Ti district 9 is set between adjacent cellular groove 5, described PXing Ti district 9 is positioned at above N+ carrier memory block 6 in N-type drift region 1；
In this utility model embodiment, insulated gate oxide layer 7 can be prepared by processing steps such as thermal oxides, and Gate Electrode Conductive polysilicon 8 deposit is filled in cellular groove 5；PXing Ti district 9 is obtained by implanting p-type foreign ion, specifically prepares insulated gate oxide layer 7, the process in Gate Electrode Conductive polysilicon 8 and PXing Ti district 9 is that known to those skilled in the art, here is omitted.In the specific implementation, when filling Gate Electrode Conductive polysilicon 8, also prepare the polysilicon connector 20 for being drawn by the Gate Electrode Conductive polysilicon 8 in cellular groove 5, described polysilicon connector 8 is supported on block media layer 3, polysilicon connector 20 can also be conductive polycrystalline silicon, by polysilicon connector 20 for being drawn, specially known to those skilled in the art by the Gate Electrode Conductive polysilicon 8 in cellular grooves 5 all in active area 18, here is omitted, as shown in Figure 7.
Step i, being selectively implanted N-type impurity ion on the first interarea of above-mentioned semiconductor substrate, to obtain N+ launch site 10 in active area 18, and obtain N+ in terminal protection district 19 and end ring 22, described N+ launch site 10 is positioned at PXing Ti district 9；
In this utility model embodiment, when removing hard mask layer 24, need the part by block media layer 3 edge to remove simultaneously, with when carrying out N-type impurity ion implanting, can obtain N+ launch site 10 and N+ simultaneously and end ring 22, described N+ launch site 10, N+ end the corresponding doping content of ring 22 and are all higher than the doping content of N-type drift region 1.N+ launch site 10 is positioned at above the side of adjacent cellular groove 5 outer wall, and N+ launch site 10 contacts with the outer wall of cellular groove 5, and the technical process preparing N+ launch site 10 and N+ cut-off ring 22 is that known to those skilled in the art, here is omitted.
Step j, on the first interarea of above-mentioned semiconductor substrate deposit insulating medium layer 4; described insulating medium layer 4 covers on the first interarea of active area 18 and the block media floor 3 in terminal protection district 19; and described insulating medium layer 4 is optionally sheltered and etched, to obtain the contact hole of through described insulating medium layer 4；
In this utility model embodiment; insulating medium layer 4 can be silicon dioxide layer etc.; during deposit insulating medium layer 4, insulating medium layer 4 can be coated with the block media floor 3 above the first interarea of source region 18 and terminal protection district 19, and insulating medium layer 4 also can cover polysilicon connector 20 simultaneously.Insulating medium layer 4 is optionally sheltered and etches, can obtain contact hole, described contact hole includes being positioned at the emitter metal contact hole of cellular groove 5 both sides, being positioned at the connector contact hole above polysilicon connector 20 and the cut-off ring metal contact hole above N+ cut-off ring 22.
Step l, on the first interarea of above-mentioned semiconductor substrate deposited metal, and described metal level was optionally sheltered and after the moment, obtain emitter metal 13, gate metal 12 and cut-off ring metal 14, described emitter metal 13 and N+ launch site 10, PXing Ti district 9 Ohmic contact, gate metal 12 electrically connects with Gate Electrode Conductive polysilicon 8, and cut-off ring metal 14 ends ring 22 Ohmic contact with N+；
In this utility model embodiment, during deposited metal, described metal level can be filled in above-mentioned contact hole, when emitter metal 13 is filled in emitter metal contact hole, can be with N+ launch site 10, PXing Ti district 9 Ohmic contact, after gate metal 12 is filled in connector contact hole, can electrically connect with polysilicon connector 20, cut-off ring metal 14 be filled in cut-off ring metal contact hole in time, cut-off ring metal 14 can end ring 22 Ohmic contact with N+, it is not in contact with each other, as shown in Figure 8 between emitter metal 13, gate metal 12 and cut-off ring metal 14.Additionally, P+ bonding pad 11 can also be arranged in PXing Ti district 9, by the Ohmic contact of P+ bonding pad 11 with emitter metal 13, it is possible to reduce the contact resistance between PXing Ti district 9 and emitter metal 13.
Step m, above-mentioned semiconductor substrate second interarea make needed for N-type electric field cutoff layer 15 and p-type collecting zone 16, N-type electric field cutoff layer 15 adjoins N-type drift region 1 and p-type collecting zone 16；
In this utility model embodiment, preparing N-type electric field cutoff layer 15 and p-type collecting zone 16 by carrying out ion implanting etc. at the second interarea of semiconductor substrate, concrete preparation process is known to those skilled in the art, and here is omitted.Additionally, before preparation N-type electric field cutoff layer 15 and p-type collecting zone 16, it is also possible to as required semiconductor substrate being carried out the PROCESS FOR TREATMENT such as thinning, concrete technology can be determined as required, and here is omitted.
Step n, collector electrode metal 17 is set on aforementioned p-type collecting zone 16, described collector electrode metal 17 and p-type collecting zone 16 Ohmic contact.
In this utility model embodiment, collector electrode metal 17 and p-type collecting zone 16 Ohmic contact such that it is able to form the colelctor electrode of IGBT device, as shown in Figure 9.
As shown in Fig. 1 and Fig. 9; when described IGBT adds positive bias-voltage in collector electrode metal 17; when emitter metal 13 and gate metal 12 ground connection; increase along with bias-voltage positive in collector electrode metal 17; depletion layer broadening; until reaching avalanche breakdown; different maximum crash ionization rate centrostigmas according to design; the i.e. position of avalanche breakdown point is different; it is likely to be present near the p-type protection ring 2 in terminal protection district 19 or in active area 19; in order to bear higher avalanche energy, puncture place need to be arranged on active area 19, with maximal efficiency current-sharing；In this utility model embodiment, by adjusting the concentration of N+ carrier accumulation layer 6 and the degree of depth, puncture place is transferred in active area 18, with can current-sharing, it is achieved maximum avalanche breakdown energy；
When adding positive bias-voltage in collector electrode metal 17, emitter metal 13 ground connection, when gate metal 12 connects 15V positive bias, IGBT device forward conduction, existence due to N+ carrier memory block 6, the few sub-hole of part is collected at the bottom of N+ carrier memory block 6, and conductivity modulation effect strengthens, and conduction voltage drop Vceon reduces；Compared with existing IGBT device, this utility model can make electric current density promote, the conduction voltage drop (Vceon) conduction voltage drop far below existing IGBT；Only change front Carrier Profile due to N+ carrier memory block 6, therefore turn-off power loss Eoff is not the most reduced by conduction voltage drop (Vceon) is affected.
Claims (7)
1. an IGBT device with carrier storage organization; in the top plan view of described IGBT device; including the active area being positioned on semiconductor substrate and terminal protection district; described active area is positioned at the center of semiconductor substrate, and terminal protection district is positioned at the outer ring of active area and around surrounding described active area；On the cross section of described IGBT device, semiconductor substrate has two relative interareas, and described interarea includes the first interarea and second interarea corresponding with the first interarea, includes the first conduction type drift region between the first interarea of semiconductor substrate and the second interarea；
On the cross section of described IGBT device, active area uses groove structure, it is provided with the second conductivity type body region in the first conduction type drift region of active area, second conductivity type body region is positioned at the top of the first conduction type drift region, cellular groove is positioned at the second conductivity type body region, and the degree of depth stretches in the first conduction type drift region below the second conductivity type body region；It is characterized in that:
It is provided with carrier storage organization in the first conduction type drift region of active area, described carrier storage organization includes for cellular groove stretches into the first conduction type carrier memory block that the first conduction type drift region inside and outside wall surrounds entirely, and the doping content of the first conduction type carrier memory block is more than the doping content of the first conduction type drift region.
The IGBT device with carrier storage organization the most according to claim 1, it is characterized in that: sidewall and diapire growth at described cellular groove have insulated gate oxide layer, being filled with Gate Electrode Conductive polysilicon in growth has the cellular groove of insulated gate oxide layer, the notch of cellular groove is covered by insulating medium layer；It is arranged over the first conduction type launch site in adjacent cellular groove lateral wall, described first conduction type launch site is positioned at the second conductivity type body region, first conduction type launch site contacts with the lateral wall of cellular groove, described first conduction type launch site, the second conductivity type body region all with the emitter metal Ohmic contact on semiconductor substrate the first interarea, emitter metal is isolated by the Gate Electrode Conductive polysilicon insulation in insulating medium layer and cellular groove.
The IGBT device with carrier storage organization the most according to claim 2, it is characterized in that: in described second conductivity type body region, be additionally provided with the second conduction type bonding pad, second conduction type bonding pad and emitter metal Ohmic contact, the second conductivity type body region is electrically connected with emitter metal by the second conduction type bonding pad；Gate Electrode Conductive polysilicon electrically connects with the gate metal above semiconductor substrate the first interarea.
The IGBT device with carrier storage organization the most according to claim 1, it is characterized in that: on the cross section of described IGBT device, terminal protection district includes the second conduction type protection ring, first conduction type ends ring and for forming the second conduction type interface of main knot, described second conduction type interface and the cellular trench contact of adjacent terminals protection zone in active area, second conduction type protection ring is positioned at the second conduction type interface and the first conduction type cut-off interannular, first conduction type cut-off ring is positioned at the outer ring in terminal protection district, first conduction type cut-off ring and the cut-off ring metal ohmic contact on semiconductor substrate the first interarea.
The IGBT device with carrier storage organization the most according to claim 4; it is characterized in that: described second conduction type interface and the second conduction type protection ring are that same technique manufactures layer; first interarea in terminal protection district is additionally provided with block media floor; be also covered with insulating medium layer on described block media layer, cut-off ring metal be supported on on insulating medium layer.
The IGBT device with carrier storage organization the most according to claim 1, it is characterized in that: in described first conduction type drift region, be additionally provided with the second conduction type collecting zone, described second conduction type collecting zone and the collector electrode metal Ohmic contact on semiconductor substrate the second interarea.
The IGBT device with carrier storage organization the most according to claim 6, it is characterized in that: in described first conduction type drift region, be additionally provided with the first conduction type electric field cutoff layer, described first conduction type electric field cutoff layer adjoins the first conduction type drift region and the second conduction type collecting zone, and the doping content of the first conduction type electric field cutoff layer is more than the doping content of the first conduction type drift region.
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| CN201620229014.5U CN205488135U (en) | 2016-03-23 | 2016-03-23 | IGBT device with charge carrier storage structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633139A (en) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | IGBT device with carrier storage structure and manufacturing method of IGBT device |
| CN110137249A (en) * | 2018-02-09 | 2019-08-16 | 苏州东微半导体有限公司 | IGBT power device and its manufacturing method |
| CN110416073A (en) * | 2018-04-28 | 2019-11-05 | 上海先进半导体制造股份有限公司 | IGBT and its manufacturing method |
| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
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2016
- 2016-03-23 CN CN201620229014.5U patent/CN205488135U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633139A (en) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | IGBT device with carrier storage structure and manufacturing method of IGBT device |
| CN105633139B (en) * | 2016-03-23 | 2019-02-15 | 无锡新洁能股份有限公司 | IGBT device and its manufacturing method with carrier storage organization |
| CN110137249A (en) * | 2018-02-09 | 2019-08-16 | 苏州东微半导体有限公司 | IGBT power device and its manufacturing method |
| CN111316445A (en) * | 2018-02-09 | 2020-06-19 | 苏州东微半导体有限公司 | IGBT power device and manufacturing method thereof |
| US11450763B2 (en) | 2018-02-09 | 2022-09-20 | Suzhou Oriental Semiconductor Co., Ltd. | IGBT power device and fabrication method therefor |
| CN110416073A (en) * | 2018-04-28 | 2019-11-05 | 上海先进半导体制造股份有限公司 | IGBT and its manufacturing method |
| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
| CN114927535B (en) * | 2022-05-20 | 2023-09-22 | 无锡鉴微华芯科技有限公司 | X-ray detector with double three-dimensional full-surrounding protection ring and preparation method thereof |
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