CN111211168B - RC-IGBT chip and manufacturing method thereof - Google Patents
RC-IGBT chip and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention relates to an RC-IGBT chip, which comprises an IGBT region and an FRD region, wherein the IGBT region and the FRD region respectively comprise a P-type base region and a contact region, and the thickness and the doping concentration of the P-type base region in the IGBT region are both larger than those of the P-type base region in the FRD region, so that the reverse recovery characteristic of the RC-IGBT chip is improved. Meanwhile, the doping concentration of the contact region in the IGBT is greater than that of the FRD region, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced. In addition, the invention also relates to a manufacturing method of the RC-IGBT chip.
Description
Technical Field
The invention relates to a semiconductor device, in particular to an RC-IGBT chip, and further relates to a manufacturing method of the RC-IGBT chip.
Background
The RC-IGBT is a semiconductor device in which a freewheeling diode FRD is integrated inside an IGBT device. The existing RC-IGBT device usually adopts one-time ion implantation, and simultaneously forms P-type base regions of an IGBT region and an FRD region. The peak concentration of the P-type base region along the effective conduction channel in the IGBT region determines the magnitude of its threshold voltage. Meanwhile, the concentration of the P-type base region must be matched with the withstand voltage condition of the cellular region. Therefore, the process window for P-base adjustable tends to be small. In the diode region, when the withstand voltage condition is satisfied, the smaller the doping concentration of the P-type base region is, the better the reverse recovery performance of the diode is. Because the adjustable process window of the P-type base region is small, the selection of the doping concentration of the P-type base region is difficult to achieve the optimization, the reverse recovery performance of the diode is improved while the static parameter performances of the IGBT device such as threshold voltage, breakdown voltage and the like are ensured, and therefore the reverse recovery characteristic of the diode cannot be fully reduced in the existing RC-IGBT device.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide an RC-IGBT chip with good reverse recovery characteristics.
The RC-IGBT chip comprises an IGBT region and an FRD region, wherein the IGBT region and the FRD region respectively comprise an N-type drift region formed by a semiconductor substrate, an N-type field termination region positioned on the back of the N-type drift region and a collector positioned below the N-type field termination region, a P-type collector region is arranged between the N-type field termination region and the collector in the IGBT region, an N-type field termination region is arranged between the N-type field termination region and the collector in the FRD region, an accumulation region is arranged on the surface of the N-type drift region in the IGBT region, a plurality of gate groove regions and virtual groove regions are further arranged in the IGBT region, the bottom ends of the gate groove regions are positioned in the N-type drift region, a plurality of emission groove regions are arranged in the FRD region, an insulating film positioned on the surface of the gate groove regions and a gate electrode positioned above the insulating film are arranged in the gate groove regions, an insulating film positioned on the surface of the virtual groove regions and a virtual gate electrode positioned above the insulating film are arranged in the virtual groove regions, an insulating film positioned on the surface of the emitting groove region and an emitting gate electrode positioned above the insulating film are arranged in the emitting groove region, an insulating medium layer positioned on the surface of a semiconductor substrate is arranged above the gate electrode, the virtual gate electrode and the emitting gate electrode, a P-type base region positioned above the accumulation region is arranged in the IGBT region, a P-type base region positioned above the N-type drift region is also arranged in the FRD region, the ion concentration of the P-type base region in the IGBT region is greater than that of the P-type base region in the FRD region, an N + emitting region is arranged on the surface of the P-type base region in the IGBT region, a contact region positioned below the N + emitting region is also arranged in the P-type base region, a contact region is also arranged on the surface of the P-type base region in the FRD region, the doping concentration of the contact region in the IGBT region is greater than that in the contact region, the thickness of the contact region in the IGBT region is greater than that in the FRD region, and emitting electrode electrically connected with the contact region are arranged on the surfaces of the IGBT region and the FRD region, and a gate metal layer connected with the gate electrode is further arranged on the surface of the IGBT area, and the virtual gate electrode in the IGBT area is electrically connected with the emitter electrode.
By the scheme, the invention at least has the following advantages: according to the RC-IGBT chip, the contact area of the FRD area and the contact area of the IGBT area are formed through different ion implantation processes, the thickness of the contact area of the FRD area is smaller than that of the contact area of the IGBT area, the contact area of the IGBT area is formed through a process of multiple times of ion implantation, the thickness of the contact area is thicker when the ion implantation times are more, and a cavity is more easily extracted when the RC-IGBT chip is turned off, so that latch-up is inhibited; and the contact region of the FRD region is formed only by one ion implantation, and the thinner the thickness thereof, the less holes are injected, whereby the reverse recovery performance of the diode can be improved. Ultimately, both latch-up is suppressed and reverse recovery characteristics are improved. Meanwhile, the P-type base region of the FRD region and the P-type base region of the IGBT region are formed by different masks through different ion implantation respectively, so that the doping concentration of the P-type base region of the FRD region is lower than that of the P-type base region of the IGBT region; under the condition of ensuring voltage resistance, the P-type base region of the FRD region adopts lower doping concentration, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced; in addition, the doping concentration of the contact region of the FRD region is lower than that of the contact region of the IGBT region, the doping concentration is reduced, so that the reverse recovery characteristic of the diode is improved, and since latch-up is not a problem in the diode, it is not necessary to form a contact region of high concentration.
In conclusion, the reverse recovery characteristic of the RC-IGBT chip is good.
Furthermore, in the RC-IGBT chip, an accumulation region is arranged on the surface of the N-type drift region in the FRD region.
In the manufacturing method of the RC-IGBT chip, the P-type base region of the FRD region and the P-type base region of the IGBT region are formed by the following steps:
and forming the P-type base region of the FRD region and the P-type base region of the IGBT region by using different masks through different ion implantation respectively.
Furthermore, according to the manufacturing method of the RC-IGBT chip, the mask which is not used for carrying out ion implantation in the FRD region but only used for carrying out ion implantation in the IGBT region is used, boron ion implantation is carried out in the gap between the gate trench region and the virtual trench region, and the P-type base region is formed in the IGBT region.
Furthermore, the method for manufacturing the RC-IGBT chip of the invention has the concentration of the implanted boron ions of 2E13-3E13 cm-2The implantation energy is 80 to 120 Kev.
Further, in the manufacturing method of the RC-IGBT chip of the present invention, the method of forming the P-type base region in the FRD region is as follows:
and (3) using a mask which is not used for carrying out ion implantation in the IGBT region but is only used for carrying out ion implantation in the FRD region, carrying out boron ion implantation in the gap of the emission groove region, and thus forming a P-type base region in the FRD region.
The P-type base region of the FRD region and the P-type base region of the IGBT region are formed by using different masks and respectively injecting different ions; the doping concentration of the P-type base region of the FRD region is lower than that of the P-type base region of the IGBT region; under the condition of ensuring voltage resistance, the P-type base region of the FRD region adopts lower doping concentration, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced;
furthermore, the method for manufacturing the RC-IGBT chip of the invention injects boron ions with the concentration of 1E13-2E13 cm-2The implantation energy is 80 to 120 Kev.
Further, in the manufacturing method of the RC-IGBT chip of the present invention, the forming method of the contact region in the IGBT region is as follows:
s1: etching the insulating medium layer in the IGBT area and etching the semiconductor substrate downwards to form a contact groove;
specifically, a mask which is not used for etching the FRD region but is only used for etching the IGBT region is used for etching the insulating medium layer 17 on the surface of the N + emission region 16 in the IGBT region to form a contact window and etching the semiconductor substrate downwards to form a contact groove 18 with the downward depth of 0.3 um; contact trenches 18 are located in the gaps between each trench region.
S2: and injecting boron ions into the N + emitter region for multiple times through the contact groove in the IGBT region to form a P + high-doped region, namely a contact region.
The P + contact region of the IGBT region is formed by a plurality of boron ion implantation steps, and the greater the number of boron ion implantation steps, the greater the thickness of the P + contact region, and the more easily holes are extracted when the device is turned off, thereby suppressing latch-up.
Further, in the manufacturing method of the RC-IGBT chip of the present invention, the formation method of the contact region in the FRD region is as follows:
s1: etching the insulating medium layer in the FRD region to form a contact groove, wherein the bottom end of the contact groove in the FRD region is at the same level with the surface of the semiconductor substrate;
specifically, a mask which is not used for etching the IGBT region but is only used for etching the FRD region is used for etching the insulating medium layer 17 on the surface of the P-type base region in the FRD region to form a contact groove 28, the bottom end of the contact groove in the FRD region is in the same level with the surface of the semiconductor substrate, the contact groove 28 in the FRD region does not extend into the semiconductor substrate, the semiconductor substrate is not etched downwards in the FRD region to form a shallow groove, and therefore a thinner P + contact region is formed on the surface of the P-type base region in the FRD region, and the reverse recovery performance of the diode is further improved.
S2: and carrying out primary boron ion implantation on the surface of the P-type base region of the FRD region through the contact groove in the FRD region to form a contact region.
The contact area formed by one-time boron ion implantation has a small thickness and a low concentration.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of the front structure of the RC-IGBT chip of the invention;
FIG. 2 is a sectional view of an IGBT region in the embodiment;
FIG. 3 is a sectional view of an FRD region in the example.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1 to 3, the RC-IGBT chip according to a preferred embodiment of the invention includes an IGBT region 1 and an FRD region 2, each of the IGBT region and the FRD region includes an N-type drift region formed by a semiconductor substrate 100, an N-type field stop region 210 located on the back of the N-type drift region, and a collector 5 located below the N-type field stop region, a P-type collector region 220 is disposed between the N-type field stop region and the collector in the IGBT region, an N-type collector region 230 is disposed between the N-type field stop region and the collector in the FRD region, an accumulation region 11 is disposed on the surface of the N-type drift region in the IGBT region, a plurality of gate trench regions 12 and dummy trench regions 32 having bottom ends located in the N-type drift region are further disposed in the IGBT region, a plurality of emitter trench regions 22 having bottom ends located in the N-type drift region are disposed in the FRD region, an insulating film 13 located on the surface of the gate trench region and a gate electrode 14 located above the insulating film are disposed in the gate trench region, an insulating film 33 located on the surface of the dummy trench region and a dummy gate electrode 34 located above the insulating film are disposed in the dummy trench region, an insulating film 23 positioned on the surface of the emitting trench region and an emitting gate electrode 24 positioned above the insulating film are arranged in the emitting trench region, an insulating medium layer 17 positioned on the surface of the semiconductor substrate is arranged above the gate electrode, the dummy gate electrode and the emitting gate electrode, a P-type base region 15 positioned above the accumulation region is arranged in the IGBT region, a P-type base region 25 positioned above the N-type drift region is also arranged in the FRD region, the ion concentration of the P-type base region in the IGBT region is greater than that of the P-type base region in the FRD region, an N + emitting region 16 is arranged on the surface of the P-type base region in the IGBT region, a contact region 19 positioned below the N + emitting region is also arranged in the P-type base region, a contact region 29 is also arranged on the surface of the P-type base region in the FRD region, the doping concentration of the contact region in the IGBT region is greater than that in the FRD region, the thickness of the contact region in the IGBT region is greater than that in the FRD region, and contact regions 19, a gate electrode positioned above the gate electrode and a gate electrode positioned above the contact region, 29, a gate metal layer connected with the gate electrode is further arranged on the surface of the IGBT area, and the virtual gate electrode in the IGBT area is electrically connected with the emitter electrode.
The contact area of the FRD area and the contact area of the IGBT area are formed through different ion implantation processes, the thickness of the contact area of the FRD area is smaller than that of the contact area of the IGBT area, the contact area of the IGBT area is formed through a plurality of ion implantation processes, the thickness of the contact area is thicker when the ion implantation times are more, and a cavity is easier to extract when the IGBT area is turned off, so that latch-up is inhibited; and the contact region of the FRD region is formed only by one ion implantation, and the thinner the thickness thereof, the less holes are injected, whereby the reverse recovery performance of the diode can be improved. Ultimately, both latch-up is suppressed and reverse recovery characteristics are improved. Meanwhile, the P-type base region of the FRD region and the P-type base region of the IGBT region are formed by different masks through different ion implantation respectively, so that the doping concentration of the P-type base region of the FRD region is lower than that of the P-type base region of the IGBT region; under the condition of ensuring voltage resistance, the P-type base region of the FRD region adopts lower doping concentration, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced; in addition, the doping concentration of the contact region of the FRD region is lower than that of the contact region of the IGBT region, the doping concentration is reduced, so that the reverse recovery characteristic of the diode is improved, and since latch-up is not a problem in the diode, it is not necessary to form a contact region of high concentration.
Preferably, in the RC-IGBT chip of the present invention, the accumulation region 21 is provided on the surface of the N-type drift region in the FRD region.
According to the manufacturing method of the RC-IGBT chip, the forming method of the P-type base region of the FRD region and the P-type base region of the IGBT region comprises the following steps:
and forming the P-type base region of the FRD region and the P-type base region of the IGBT region by different ion implantations respectively by using different masks.
Preferably, in the method for manufacturing the RC-IGBT chip according to the present invention, boron ion implantation is performed in the gap between the gate trench region 12 and the dummy trench region 32 using a mask for ion implantation only in the IGBT region without ion implantation in the FRD region, thereby forming the P-type base region 15 in the IGBT region.
Preferably, in the method for manufacturing the RC-IGBT chip, the concentration of the implanted boron ions is 2E13-3E13 cm-2The implantation energy is 80 to 120 Kev.
Preferably, in the method for manufacturing the RC-IGBT chip of the present invention, the method for forming the P-type base region in the FRD region is as follows:
boron ion implantation is performed in the gap of the emitter trench region 22 using a mask for ion implantation only of the FRD region without performing ion implantation in the IGBT region, thereby forming a P-type base region in the FRD region.
The P-type base region of the FRD region and the P-type base region of the IGBT region are formed by using different masks and respectively injecting different ions; the doping concentration of the P-type base region of the FRD region is lower than that of the P-type base region of the IGBT region; under the condition of ensuring voltage resistance, the P-type base region of the FRD region adopts lower doping concentration, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced;
preferably, in the method for manufacturing the RC-IGBT chip, the concentration of the implanted boron ions is 1E13-2E13 cm-2The implantation energy is 80 to 120 Kev.
Preferably, in the method for manufacturing the RC-IGBT chip according to the present invention, the contact region in the IGBT region is formed by:
s1: etching the insulating medium layer 17 in the IGBT area and etching the semiconductor substrate downwards to form a contact groove 18;
specifically, a mask which is not used for etching the FRD region but is only used for etching the IGBT region is used for etching the insulating medium layer 17 on the surface of the N + emission region 16 in the IGBT region to form a contact window and etching the semiconductor substrate downwards to form a contact groove 18 with the downward depth of 0.3 um; contact trenches 18 are located in the gaps between each trench region.
S2: boron ions are implanted into the N + emitter region multiple times through the contact trench 18 in the IGBT region to form a P + highly doped region, i.e., a contact region 19.
The P + contact region of the IGBT region is formed by a plurality of boron ion implantation steps, and the greater the number of boron ion implantation steps, the greater the thickness of the P + contact region, and the more easily holes are extracted when the device is turned off, thereby suppressing latch-up.
Further, in the manufacturing method of the RC-IGBT chip of the present invention, the contact region in the FRD region is formed by the following steps:
s1: and etching the insulating medium layer 17 in the FRD region to form a contact groove 28, wherein the bottom end of the contact groove of the FRD region is at the same level with the surface of the semiconductor substrate.
Specifically, a mask which is not used for etching the IGBT area but is only used for etching the FRD area is used for etching the insulating medium layer 17 on the surface of the P-type base area in the FRD area to form a contact groove 28, the bottom end of the contact groove in the FRD area is in the same level with the surface of the semiconductor substrate, the contact groove 28 in the FRD area does not extend into the semiconductor substrate, the semiconductor substrate is not etched downwards in the FRD area to form a shallow groove, and therefore a thinner P + contact area is formed on the surface of the P-type base area in the FRD area, and the reverse recovery performance of the diode is further improved.
S2: boron ion implantation is performed once to the surface of the P-type base region of the FRD region through the contact trench 28 in the FRD region to form a contact region 29.
The contact area formed by one-time boron ion implantation has a small thickness and a low concentration.
The following is a relatively complete manufacturing method of the RC-IGBT chip of the present embodiment:
1. taking an N-type RC-IGBT device as an example, an N-type single crystal silicon material or an N-type epitaxial silicon material is used as a semiconductor substrate material to serve as a drift region of the RC-IGBT device.
2. Neglecting the forming process of the terminal region, a cellular structure of the RC-IGBT device is formed in the active region.
3. Accumulation regions 11 and 21 are formed in the device active region of the semiconductor substrate 100 by ion implantation and high-temperature drive-in. In which an accumulation region 11 is formed in the IGBT region and an accumulation region 21 is formed in the FRD region, both of which are completed in the same process. The high concentration accumulation region in the diode can reduce hole injection of the anode, thereby improving reverse recovery characteristics. In the IGBT, the accumulation region can inhibit holes from flowing into the P-type base region, and the conduction voltage drop is reduced. Here, it is also possible to use a mask for ion implantation only for the IGBT region without ion implantation in the FRD region, so that the accumulation region 11 is formed only in the IGBT region, and not in the FRD region.
4. The gate trench region 12, the emitter trench region 22, and the dummy trench region 32 are formed in the surface of the semiconductor substrate 100 by photolithography and reactive ion etching. The IGBT region is provided with a gate groove region 12 and a virtual groove region 32, and the gate groove region 12 and the virtual groove region 32 can be formed according to a certain proportion of 1: n is set. An emission trench region 22 is formed in the FRD region. The groove regions may be arranged at equal intervals or at unequal intervals. Specifically, a silicon dioxide barrier layer with the thickness of 1000-10000A is grown on the surface of the semiconductor substrate 100 and is used as a barrier layer for trench etching; etching the silicon dioxide barrier layer by using the photoetching mask to form a silicon dioxide barrier layer pattern; then removing the photoresist by wet etching; etching the silicon substrate by using the silicon dioxide barrier layer pattern as a mask, namely deeply digging a plurality of grooves to form a gate groove region 12, an emission groove region 22 and a virtual groove region 32; and removing the residual silicon dioxide barrier layer by wet etching. Wherein, the depth of the groove is 3-7 um, and the width of the cross section is 0.8-1.5 um.
5. A layer of insulating film 13, 23 and 33 with higher compactness is grown on the inner wall of each groove area. Specifically, a sacrificial oxide layer is grown on the inner wall of each groove area through high-temperature oxidation, and then the sacrificial oxide layer is corroded by a wet method, so that the insulating film is smooth and flat; and growing an insulating film on the inner wall of each groove region through high-temperature oxidation. Wherein the insulating film has a thickness of 1000-2000A; the operation steps are to reduce crystal defects and impurities, so that an insulating film with better compactness is grown to be used as a gate oxide film of an MOS structure;
6. a layer of polysilicon is deposited on the surface of the semiconductor substrate 100 and doped to form N-type polysilicon. Specifically, polysilicon is deposited on the surface of the semiconductor substrate 100 by a high-temperature furnace tube and subjected to in-situ doping to form N-type polysilicon, the thickness of the polysilicon is 1-2 um, and the concentration of the polysilicon is 1E20 cm-3(ii) a And then activating the polysilicon at high temperature of 950 ℃ for 30 minutes.
7. And performing reactive ion etching on the polycrystalline silicon on the surface of the semiconductor substrate 100, wherein the etching thickness is 1-2 um, and only the polycrystalline silicon in each groove area and on channels of the PAD and BUS of the gate electrode is reserved. Thereby forming gate electrode 14, dummy gate electrode 34, and emitter gate electrode 24. Wherein the gate electrode 14 is formed in the gate trench region 12, the dummy gate electrode 34 is formed in the dummy trench region 32, and the emitter gate electrode 24 is formed in the emitter trench region 22.
8. Ion implantation is performed in the gap between the gate trench region 12 and the dummy trench region 32. Specifically, a mask for not performing ion implantation in the FRD region but performing ion implantation only in the IGBT region is used, thereby forming the P-type base region 15 in the IGBT region. Wherein the concentration of the implanted boron ions is 2E13-3E13 cm-2The implantation energy is 80-120 Kev.
9. Ion implantation is performed in the gap of the emitter trench region 22. Specifically, a mask for not performing ion implantation in the IGBT region but only performing ion implantation in the IGBT region is used, thereby forming a P-type base region in the FRD region. Wherein the concentration of the implanted boron ions is 1E13-2E13 cm-2The implantation energy is 80-120 Kev. The P-type base region of the FRD region and the P-type base region of the IGBT region are formed by using different masks and respectively injecting different ions; the doping concentration of the P-type base region of the FRD region is lower than that of the P-type base region of the IGBT region; in ensuring enduranceUnder the condition of voltage, the P-type base region of the FRD region adopts lower doping concentration, so that the reverse recovery current and the reverse recovery loss of the diode are reduced, and the robustness of the device is enhanced;
10. carrying out high-temperature well pushing to form the P- type base regions 15 and 25;
11. an N + emitter region 16 is formed on the upper surface of the P-type base region 15 in the IGBT region through ion implantation and high-temperature drive-in. Specifically, an implantation window of an N + emission region is formed by using a photolithographic mask, using a mask for not performing ion implantation in the FRD region but only performing ion implantation in the IGBT region; and injecting high-energy arsenic ions into the injection window of the N + emitter region and pushing the trap at high temperature, so that an N + emitter region 16 is formed on the upper surface of the P-type base region in the IGBT region. Wherein the implantation dosage of arsenic ion is 1E15-8E15cm-2The implantation energy is 80-120 Kev.
12. An insulating dielectric layer 17 is deposited on the surface of the semiconductor substrate and reflowed to be planarized. The thickness of the insulating medium layer is 1-1.5 um; the insulating medium layer can be formed by stacking a plurality of layers of insulating media;
13. the insulating dielectric layer 17 is etched in the IGBT region and the semiconductor substrate is etched down, forming contact trenches 18. Specifically, a mask which is not used for etching the FRD region but is only used for etching the IGBT region is used for etching the insulating medium layer 17 on the surface of the N + emission region 16 in the IGBT region to form a contact window and etching the semiconductor substrate downwards to form a contact groove 18 with the downward depth of 0.3 um; contact trenches 18 are located in the gaps between each trench region.
14. Boron ions are implanted multiple times into the N + emitter region through the contact trench 18 to form a P + highly doped region, i.e., a contact region 19. The P + contact area of the IGBT area is formed by a process of multiple times of boron ion injection, the thickness of the P + contact area is thicker when the number of times of boron ion injection is larger, and a hole is easier to be drawn out when a device is turned off, so that latch-up is inhibited;
15. the insulating dielectric layer 17 is etched in the FRD region to form contact trenches 28. Specifically, a mask which is not used for etching the IGBT region but is only used for etching the FRD region is used for etching the insulating medium layer 17 on the surface of the P-type base region in the FRD region to form a contact groove 28, at the moment, the lower part of the contact groove 28 in the FRD region is in the same level with the surface of the semiconductor substrate, namely, the contact groove 28 in the FRD region does not extend into the semiconductor substrate, the semiconductor substrate is not etched downwards in the FRD region to form a shallow groove, and therefore a thinner P + contact region is formed on the surface of the P-type base region in the FRD region, and the reverse recovery performance of the diode is further improved.
16. And boron ion implantation is carried out on the surface of the P-type base region of the FRD region through the contact trench 28 for one time, so that a P + contact region 29 with a small thickness and a low concentration is formed.
17. And depositing emitter metal on the surface of the device and forming an emitter electrode 3 and a gate metal layer by etching. Specifically, a metal film with the thickness of 1-5 um is deposited on the surface of the device; then forming an emitter electrode 3 and a gate metal layer by etching; the emitter electrode 3 and the gate metal layer are isolated from each other by an insulating dielectric layer 17. The metal is aluminum/silicon alloy or aluminum/silicon/copper alloy or other materials, the thickness is 1-5 um, and ohmic contact is formed between the highly doped silicon and the metal through heating alloying at about 400 ℃, so that the contact resistance is reduced.
18. And after the front metallization of the power device is completed, turning over the chip and thinning the back.
19. Forming an N-type field stop region 210 on the back surface of the semiconductor substrate by phosphorus ion implantation and a high-temperature drive-in process; the doping concentration of the N-type field stop region 210 is 1E15-1E17 cm-3The junction depth is 1-3 um, so that the compromise characteristic of the IGBT can be improved, and the current trailing time when the IGBT is turned off is reduced.
20. Forming a back P-type collector region 220 on the back side of the semiconductor substrate by boron ion implantation and a high-temperature drive-in process; wherein the doping concentration of the P-type collector region 220 is 1E18-5E19 cm-3The junction depth is 0.5-1 um, so as to control the hole emission efficiency. The P-type collector region 220 is formed only in the IGBT region.
21. A back N-type collector region 230 is formed on the back surface of the semiconductor substrate by phosphorus ion implantation and a high-temperature drive-in process. The N-type collector region 230 is formed only in the FRD region.
22. And carrying out back metallization on the RC-IGBT device to form a back collector 5.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, it should be noted that, for those skilled in the art, many modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (9)
1. The RC-IGBT chip comprises an IGBT area and an FRD area, and is characterized in that: the IGBT region and the FRD region respectively comprise an N-type drift region formed by a semiconductor substrate (100), an N-type field termination region (210) positioned on the back of the N-type drift region and a collector (5) positioned below the N-type field termination region, a P-type collector region (220) is arranged between the N-type field termination region and the collector in the IGBT region, an N-type collector region (230) is arranged between the N-type field termination region and the collector in the FRD region, an accumulation region (11) is arranged on the surface of the N-type drift region in the IGBT region, a plurality of gate groove regions (12) and virtual groove regions (32) are further arranged in the IGBT region, the bottom ends of the gate groove regions are positioned in the N-type drift region, a plurality of emission groove regions (22) are arranged in the FRD region, an insulating film (13) and a gate electrode (14) are arranged in the gate groove regions and positioned above the insulating film, and an insulating film (33) and a virtual gate electrode (34) are arranged in the virtual groove regions, an insulating film (23) positioned on the surface of the transmitting groove region and a transmitting gate electrode (24) above the insulating film are arranged in the transmitting groove region, an insulating medium layer (17) positioned on the surface of the semiconductor substrate is arranged above the gate electrode, the virtual gate electrode and the transmitting gate electrode, a P-type base region (15) positioned above the accumulation region is arranged in the IGBT region, a P-type base region (25) positioned above the N-type drift region is also arranged in the FRD region, the ion concentration of the P-type base region in the IGBT region is greater than that of the P-type base region in the FRD region, an N + transmitting region (16) is arranged on the surface of the P-type base region in the IGBT region, a contact region (19) positioned below the N + transmitting region is also arranged in the P-type base region, a contact region (29) is also arranged on the surface of the P-type base region in the FRD region, the doping concentration of the contact region in the FRD region is greater than that in the contact region, and the thickness of the contact region in the IGBT region is greater than that in the FRD region, emitter electrodes (3) electrically connected with the contact areas (19 and 29) are arranged on the surfaces of the IGBT area and the FRD area, a gate metal layer connected with the gate electrode is further arranged on the surface of the IGBT area, and the virtual gate electrode in the IGBT area is electrically connected with the emitter electrodes.
2. The RC-IGBT chip according to claim 1, wherein: and an accumulation region (21) is arranged on the surface of the N-type drift region in the FRD region.
3. The manufacturing method of the RC-IGBT chip according to claim 2, wherein the P-type base region of the FRD region and the P-type base region of the IGBT region are formed by the following steps:
and forming the P-type base region of the FRD region and the P-type base region of the IGBT region by using different masks through different ion implantation respectively.
4. The method of manufacturing an RC-IGBT chip according to claim 3, characterized in that: a P-type base region (15) is formed in the IGBT region by implanting boron ions into the gap between the gate trench region (12) and the dummy trench region (32) using a mask for ion implantation of only the IGBT region without ion implantation into the FRD region.
5. The method of manufacturing an RC-IGBT chip according to claim 4, wherein: the concentration of the implanted boron ions is 2E13-3E13 cm-2The implantation energy is 80 to 120 Kev.
6. The method for manufacturing an RC-IGBT chip according to claim 3, wherein the method for forming the P-type base region in the FRD region is as follows:
boron ion implantation is performed in the gap of the emitter trench region (22) using a mask for ion implantation only of the FRD region without ion implantation in the IGBT region, thereby forming a P-type base region in the FRD region.
7. The RC-I of claim 6A method for manufacturing a GBT chip, comprising: the concentration of the implanted boron ions is 1E13-2E13 cm-2The implantation energy is 80 to 120 Kev.
8. The method for manufacturing an RC-IGBT chip according to claim 3, wherein the contact region in the IGBT region is formed by the following steps:
s1: etching the insulating medium layer (17) in the IGBT area and etching the semiconductor substrate downwards to form a contact groove (18);
s2: boron ions are implanted into the N + emitter region for multiple times through the contact trench (18) in the IGBT region to form a P + highly doped region, namely a contact region (19).
9. The method of manufacturing an RC-IGBT chip according to claim 3, wherein the contact region in the FRD region is formed by:
s1: etching the insulating medium layer (17) in the FRD region to form a contact groove (28), wherein the bottom end of the contact groove of the FRD region is at the same level with the surface of the semiconductor substrate;
s2: and carrying out primary boron ion implantation on the surface of the P-type base region of the FRD region through the contact groove (28) in the FRD region to form a contact region (29).
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