JP2013145903A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent characteristics.SOLUTION: A semiconductor device comprises a base layer of a first conductivity type, a barrier layer of a first conductivity type which is provided on the base layer of a first conductivity type and has a higher impurity concentration than that of the base layer of a first conductivity type, a diffusion layer of a second conductivity type which is provided adjacently to the barrier layer, a base layer of a second conductivity type provided on the barrier layer, a trench which is provided in contact with the barrier layer, the diffusion layer and the base layer of a second conductivity type so as to position its bottom in the barrier layer and the diffusion layer, a first conductor layer provided within the trench via an insulating film, a first electrode electrically connected to the base layer of a first conductivity type, and a second electrode electrically connected to the base layer of a second conductivity type.

Description

  The present invention relates to a semiconductor device.

As an example of a power semiconductor device, an IGBT (Insulated Gate Bipolar Transis
tor). In the IGBT, a p-type collector layer and an n-type base layer are stacked in this order on a collector electrode, and a plurality of stripe-shaped trench gate electrodes are provided thereon. A p-type base layer is provided in a region between the trench gate electrodes, and an n-type emitter layer connected to the emitter electrode is provided in a part of the upper layer portion of the p-type base layer.

In the IGBT, when a positive potential is applied to the trench gate electrode, a MOS channel is formed in the p-type base layer, electrons are introduced from the n-type emitter layer, and holes are introduced from the p-type collector layer. A current flows between the collector electrode and the emitter electrode.

Recently, the saturation voltage (Vce (sa
In order to reduce t)), a method for suppressing the discharge of accumulated carriers (for example, holes) in the vicinity of the device surface is disclosed (for example, see Patent Document 1). In this previous example, the n-type barrier layer is p
It is provided directly under the shape base layer to suppress the discharge of accumulated carriers in the vicinity of the element surface.

However, the concentration of the n-type barrier layer cannot be increased in order to suppress the breakdown between the n-type barrier layer and the p-type base layer. This allows saturation voltage (
Vce (sat)) has a limit, and there is a problem that the characteristics of the semiconductor device are not improved.

JP 2008-227251 A

The problem to be solved by the present invention is to provide a semiconductor device having good characteristics.

According to one aspect of the present invention, a first conductivity type base layer and a first conductivity type provided on the first conductivity type base layer and having a higher impurity concentration than the first conductivity type base layer. A barrier layer, a second conductivity type diffusion layer provided adjacent to the barrier layer, a second conductivity type base layer provided on the barrier layer, the barrier layer, the diffusion layer, and A trench provided in contact with the base layer of the second conductivity type and having a bottom portion located in the barrier layer and the diffusion layer;
A first conductive layer provided in the trench via an insulating film; a first electrode electrically connected to the first conductive type base layer; and a second conductive type base layer A semiconductor device having a second electrode that is electrically connected is provided.

It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 1st Embodiment. It is a principal part top schematic diagram of the semiconductor device which concerns on 1st Embodiment. FIG. 6 is a diagram for explaining the function and effect of the semiconductor device 1. It is a figure explaining the effect of the semiconductor device 100 concerning a comparative example. FIG. 5 is a relationship diagram between the concentration of an n-type barrier layer and a breakdown voltage (Vces). It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment. It is a principal part top schematic diagram of the semiconductor device which concerns on 3rd Embodiment. FIG. 6 is a diagram for explaining the function and effect of the semiconductor device 3. It is a principal part cross-sectional view of the semiconductor device which concerns on 4th Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 5th Embodiment. It is a principal part figure of the alternating current and direct current | flow conversion circuit containing an inverter circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of an essential part of the semiconductor device according to the first embodiment.

  FIG. 2 is a schematic plan view of an essential part of the semiconductor device according to the first embodiment.

FIG. 1 shows a cross section taken along line XX ′ of FIG. In FIG. 2, the emitter electrode 81 and the insulating layer 70 illustrated in FIG. 1 are not displayed.

A semiconductor device 1 shown in FIGS. 1 and 2 is a power semiconductor device (for example, IEGT (Injection
An Enhanced Gate Transistor)), a collector electrode 80 is a first main electrode, a p-type collector layer 11, n ^- and -type base layer 13, an n-type barrier layer 14, a p-type diffusion layer 15, p A type base layer 16, an n ⁺ -type emitter layer 17, trenches 20, 23, and 26, and an emitter electrode 81 that is a second main electrode are provided. Here, for "collector", "drain"
The “emitter” may be referred to as a “source”. As for the conductivity type of the impurity, the n-type is the first conductivity type and the p-type is the second conductivity type.

As shown in FIG. 1, in the semiconductor device 1, the p-type collector layer 11 is provided on the collector electrode 80 (first main electrode). An n-type buffer layer 12 is provided on the p-type collector layer 11. An n ^{− type} base layer 13 is provided on the n type buffer layer 12. The impurity concentration of the n ⁻ -type base layer 13 is lower than the impurity concentration of the n-type buffer layer 12. The n ^{− type} base layer 13 functions as a drift layer.

An n-type barrier layer 14 and a p-type diffusion layer 15 are provided on the n ⁻ -type base layer 13. The n-type barrier layers 14 and the p-type diffusion layers 15 are alternately arranged on the n ⁻ -type base layer 13. The impurity concentration of the n-type barrier layer 14 is higher than the impurity concentration of the n ⁻ -type base layer 13. The upper surface of the n-type barrier layer 14 is lower than the upper surface of the p-type diffusion layer 15. In other words, n
The shape barrier layer 14 is formed in a convex shape from the main surface of the n ⁻ -type base layer 13 toward the p-type diffusion layer 15 side. A p-type base layer 16 is provided on the n-type barrier layer 14. An n ⁺ -type emitter layer 17 and a p ^{+ -type} contact layer 18 are selectively provided on the surface of the p-type base layer 16. A plurality of trenches are formed from the surfaces of the p-type base layer 16 and the p-type diffusion layer 15 toward the collector electrode 80 side. The trench is formed by p-type base layer 16 and n
It is provided between the shape barrier layer 14 and the p-type diffusion layer 15.

For example, the n-type barrier layer 14 is sandwiched between the p-type diffusion layers 15. Thereby, two pn junction interfaces exist on both sides of the n-type barrier layer 14. One of the two pn junction interfaces is indicated by an arrow A in the drawing, and an pn junction interface opposite to the arrow A is indicated by an arrow B.

At the junction interface between the n-type barrier layer 14 and the p-type diffusion layer 15 indicated by the arrow A, the groove-like trench 20 is formed from the surface of the p-type base layer 16 and the n ⁺ -type emitter layer 17 toward the collector electrode 80 side. Is formed. A conductive layer 22 made of, for example, polysilicon is provided in the trench 20 via an insulating film 21 such as an oxide film. The bottom surfaces (lower surfaces) of the p-type diffusion layer 15 and the n-type barrier layer 14 are located closer to the collector electrode 80 than the lower end of the trench 20. The n-type barrier layer 14 and the p-type diffusion layer 15 form a super junction (superjunction) near the tip (near the lower end) of the trench 20.

Further, at the junction interface between the n-type barrier layer 14 and the p-type diffusion layer 15 indicated by the arrow B, the groove-shaped trench is formed from the surface of the p-type base layer 16 and the n ⁺ -type emitter layer 17 toward the collector electrode 80. 23 is formed. A conductive layer 25 made of, for example, polysilicon is provided in the trench 23 via an insulating film 24 such as an oxide film. The bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located on the collector electrode 80 side from the lower end of the trench 23. The n-type barrier layer 14 and the p-type diffusion layer 15 form a super junction near the tip of the trench 23.

In the semiconductor device 1, a groove-like trench 26 is provided between the trench 20 and the trench 23. The trench 26 penetrates the n ⁺ -type emitter layer 17 and the p-type base layer 16 and reaches the n-type barrier layer 14. A conductive layer 28 made of, for example, polysilicon is provided in the trench 26 via an insulating film 27 such as an oxide film. The trench 20, the trench 23, and the trench 26 have substantially the same depth.

Thus, in the semiconductor device 1, the bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located closer to the collector electrode 80 than the lower ends of the trenches 20, 23, and 26. The conductor layer 28 is a trench gate electrode (control electrode) of the semiconductor device 1 and is electrically connected to a gate wiring (not shown). The conductor layer 28 is a control electrode that controls energization between the n ⁺ -type emitter layer 17 and the n-type barrier layer 14.

The p ^{+ -type} contact layer 18 and the n ⁺ -type emitter layer 17 are electrically connected to the emitter electrode 81 (second main electrode). Furthermore, the conductor layer 22 in the trench 20 and the conductor layer 25 in the trench 23 are electrically connected to the emitter electrode 81. This
The potential of the conductor layer 28 that is a trench gate electrode is shielded by the conductor layers 22 and 25 provided on both sides of the conductor layer 28. That is, the conductor layer 22 and the conductor layer 25 function as an electrical shielding layer for the conductor layer 28. An insulating layer 70 is provided on the surfaces of the p-type diffusion layer 15, the p-type base layer 16, the n ⁺ -type emitter layer 17 and the trenches 20, 23 and 26.

As shown in FIG. 2, in the semiconductor device 1, the trenches 20, 23,
26 extend in stripes substantially in parallel. The extending direction is, for example, a direction substantially parallel to the main surface of the n ⁻ -type base layer 13. Further, the p ⁺ is adjacent to the n ⁺ -type emitter layer 17.
A shaped contact layer 18 is provided.

Referring to FIGS. 1 and 2, the n ⁺ -type emitter layer 17 is located on both sides of the trench 26 and is in contact with the side surface of the trench 26. The p-type base layer 16 is in contact with the side surface of the trench 20 or the side surface of the trench 23. The p-type base layer 16 includes an n ⁺ -type emitter layer 17 and a p ⁺
The contact layer 18 is provided on the lower side. The p-type base layer 16 is composed of the n ⁺ -type emitter layer 1
It is electrically connected to the emitter electrode 81 through the 7 or p ^{+ -type} contact layer 18.

In the semiconductor device 1, the “width” of each member is substantially perpendicular to the direction in which the trenches 20, 23, and 26 extend in a stripe shape, and in a direction substantially parallel to the main surface of the n ⁻ -type base layer 13. When defined in terms of width, the width of the n-type barrier layer 14 sandwiched between the p-type diffusion layers 15 is configured to be narrower than the width of the p-type diffusion layer 15.

For example, the region occupied by the n-type barrier layer 14 and the p-type base layer 16 on the collector electrode 80 is the main cell 90, and the region occupied by the p-type diffusion layer 15 on the collector electrode 80 is the subcell 9.
When it is 1, the width of the main cell 90 is narrower than the width of the subcell 91. For example, the width of the subcell 91 is adjusted to about 2 to 5 times the width of the main cell 90.

The main cell 90 and the subcell 91 extend in the direction in which the trenches 20, 23, and 26 extend, and are alternately arranged. Since the main cell 90 includes the conductor layer 28 as a gate electrode, the p-type base layer 16, the n ⁺ -type emitter layer 17, and the n-type barrier layer 14, the MOSFET
Functions as (Metal Oxide Semiconductor Field Effect Transistor). For this reason,
The impurity concentration and area of the p-type base layer 16 and the n ⁺ -type emitter layer 17 in the main cell 90 are determined according to the performance required for the MOSFET. On the other hand, the n-type barrier layer 14
The impurity concentration of is higher than the impurity concentration of the n ⁻ -type base layer 13. However, the impurity concentration is adjusted so that the depletion layer sufficiently spreads from the pn junction interface between the n-type barrier layer 14 and the p-type diffusion layer 15.

The p-type collector layer 11, the n-type buffer layer 12, the n ⁻ -type base layer 13, the n-type barrier layer 14, the p-type diffusion layer 15, the p-type base layer 16, the n ⁺ -type emitter layer 17, and the p ^{+ -type} contact. The material of the layer 18 is mainly composed of silicon (Si), for example. The material of the collector electrode 80 and the emitter electrode 81 is metal. The material of the insulating films 21, 24, and 27 is, for example, silicon oxide (SiO ₂ ).

  Next, functions and effects of the semiconductor device 1 will be described.

  FIG. 3 is a diagram for explaining the function and effect of the semiconductor device 1.

The potential of the emitter electrode 81 of the semiconductor device 1 shown in FIG. 3 is, for example, a ground potential, and a potential higher than the threshold is applied to the conductor layer 28 in a state where a potential higher than the ground potential is applied to the collector electrode 80. Then, a channel is formed in a region in contact with the insulating film 27 in the p-type base layer 16. As a result, the MOSFET formed in the main cell 90 is turned on, and n
Electrons flow from the ⁺ -type emitter layer 17 through the channel to the n-type barrier layer 14 (see arrow e (electron) in the figure). At this time, holes flow from the p-type collector layer 11 to the n ⁻ -type base layer 13 through the n-type buffer layer 12 (see arrow h (hole)). As a result, a current flows between the collector electrode 80 and the emitter electrode 81.

At this time, the emitter electrode 81 is connected only to the main cell 90, and the subcell 91
Not connected to. The holes in the n ⁻ -type base layer 13 are the p ^{+ -type} contact layer 1 described above.
8 is discharged outside the semiconductor device 1 only through the main cell 90. In the semiconductor device 1, in addition to the main cell 90, the subcell 91 that does not contribute to conduction is provided, so that a barrier against holes is formed. Furthermore, in the semiconductor device 1, an n-type barrier layer 14 is disposed below the p-type base layer 16. Thereby, the amount of holes flowing into the p-type base layer 16 is reduced. This effect becomes more prominent as the width of the main cell 90 becomes narrower or the concentration of the n-type barrier layer 14 increases. As a result, the amount of electrons injected through the n ⁺ -type emitter layer 17 is relatively increased, and the n-type barrier layer 1 below the p-type base layer 16 is.
4. The carrier concentration of the n ⁻ -type base layer 13 is increased.

In the semiconductor device 1, since the n-type barrier layer 14 having a higher impurity concentration than the n ⁻ -type base layer 13 is provided in the main cell 90 in a convex shape, a path of electrons flowing through the n-type semiconductor layer is provided. To increase.

  For this reason, in the semiconductor device 1, the on-resistance becomes low.

In the semiconductor device 1, the conductor layers 22 and 25 provided on both sides of the conductor layer 28 that is a trench gate electrode are connected to the emitter electrode 81. For this reason, at the time of switching, the potential of the conductor layer 28 is shielded by the conductor layers 22 and 25 provided on both sides of the conductor layer 28. That is, the conductor layer 28 of the semiconductor device 1 is
The gate mirror capacitance of the semiconductor device 1 is greatly reduced without being affected by the potential fluctuation of the p-type diffusion layer 15 of the subcell 91. For example, when the conductor layer 28 is driven in the range of 0 to 15V, undershooting in which the potential of the conductor layer 28 is lower than 0V is suppressed. As a result, the semiconductor device 1 can perform a faster switching operation.

On the other hand, when a potential lower than the threshold is applied to the conductor layer 28 of the semiconductor device 1, the channel disappears from the p-type base layer 16, and the MOSFET formed in the main cell 90 is turned off. As a result, the voltage between the collector electrode 80 and the emitter electrode 81 rises, and the n-type barrier layer 14 includes the collector electrode 80 to the p-type collector layer 11, the n-type buffer layer 12, and the n-type buffer layer 12.
^A positive potential is conducted through the shaped base layer 13. On the other hand, the p-type diffusion layer 15 includes the insulating films 21 and 2.
4 is coupled to the conductor layers 22 and 25 via the collector electrode 80.
The potential is lower than the voltage of. As a result, a positive potential is applied to the n ⁻ -type base layer 13 and the n-type barrier layer 14, and a negative potential is applied to the p-type diffusion layer 15.

In the semiconductor device 1, a super junction is formed by the n-type barrier layer 14 and the p-type diffusion layer 15 near the tips of the trenches 20 and 23. Therefore, trench 20,
A depletion layer expands in the main cell 90 from the pn junction interface near the tip of 23. As a result, avalanche breakdown at the junction interface between the p-type base layer 16 and the n-type barrier layer 14 is suppressed.
Further, since the depletion layer is expanded, the electric field strength in the vicinity of the tips of the trenches 20, 23, and 26 is alleviated, and avalanche breakdown that can occur in the vicinity of the trench tips is also suppressed. Further, by forming a super junction, the impurity concentration of the n-type barrier layer 14 can be increased,
The saturation voltage Vce (sat) between the collector electrode 80 and the emitter electrode 81 can be reduced.

The pitch of the trenches 20 and 23 in the subcell 91 is larger than the pitch of the trenches 20, 23 and 26 in the main cell 90.
Since it is formed deeper than 3, 26, the electric field concentration at the tip of the trench is alleviated. Thereby, the pressure | voltage resistant fall near a trench front-end | tip is suppressed.

On the other hand, FIG. 4 is a diagram for explaining the operational effect of the semiconductor device 100 according to the comparative example.
In the semiconductor device 100 according to the comparative example, the n-type barrier layer 140 having a higher impurity concentration than the n ⁻ -type base layer 130 is provided in the main cell 90. However, the n-type barrier layer 14
The bottom surfaces of the 0 and p-type diffusion layers 150 are higher than the lower ends of the trenches 20, 23, and 26. For this reason, the semiconductor device 100 has a configuration in which no super junction exists near the tips of the trenches 20 and 23.

In the configuration of the semiconductor device 100, the tips of the trenches 20, 23, and 26 are connected to the n ⁻ -type base layer 1.
Therefore, a high breakdown voltage equivalent to the case without the n-type barrier layer 140 can be obtained. However, in order to improve the characteristics (for example, to improve the barrier property of the n-type barrier layer 140), when the implantation dose of the n-type barrier layer 140 is further increased,
The n-type impurity diffuses, and the bottom surface of the n-type barrier layer 140 is located in the trenches 20, 23, 2
6 is located on the collector electrode 80 side from the lower end of the electrode 6. At that time, in the semiconductor device 100, the impurity concentration in the vicinity of the tips of the trenches 20, 23, and 26 is high, so that avalanche breakdown near the tip of the trench is more likely to occur than in the semiconductor device 1. In particular, since the n-type barrier layer 140 and the p-type diffusion layer 150 of the semiconductor device 100 do not form a super junction, the impurity concentration of the n-type barrier layer 140 is higher than the impurity concentration of the n-type barrier layer 14. Can't be high. Thus, in the semiconductor device 100, an upper limit is imposed on the impurity concentration of the n-type barrier layer 140 in order to suppress avalanche breakdown at the pn junction interface between the n-type barrier layer 140 and the p-type base layer 16. As a result, the saturation voltage Vce (sat) of the semiconductor device 100 becomes higher than the saturation voltage Vce (sat) of the semiconductor device 1.

FIG. 5 is a relationship diagram between the concentration of the n-type barrier layer and the breakdown voltage (Vces). The horizontal axis of FIG. 5 shows the impurity concentration (Qnb × 10 ¹³ cm ⁻² ) of the n-type barrier layers 14 and 140, and the vertical axis shows the breakdown voltage Vces (V).

For example, when the target breakdown voltage Vces (V) is set to 1050 V, in the semiconductor device 100, the impurity concentration of the n-type barrier layer 140 is 1.0 × 10 ¹³ cm ⁻² or more and is lower than the target value (1050 V). In contrast, in the semiconductor device 1, the impurity concentration of the n-type barrier layer 14 is 2.0 × 10 ¹³ cm ^{−2 to} 4.0 × 10 ¹³ cm ⁻² and the target value (1050 V).
) Is higher than Thus, the breakdown voltage of the semiconductor device 1 is higher than the breakdown voltage of the semiconductor device 100.

Next, another embodiment will be described. In the following description, the same members are denoted by the same reference numerals, and description of members once described is omitted as appropriate.

(Second Embodiment)
FIG. 6 is a schematic cross-sectional view of a relevant part of a semiconductor device according to the second embodiment.

A semiconductor device 2 shown in FIG. 6 is a reverse conduction type power semiconductor device (for example, RC (Reverse Co
nducting) -IEGT). In the semiconductor device 2, the p-type collector layer 11 is selectively provided on the collector electrode 80. For example, in the main cell 90, the p-type collector layer 11 is not provided on the collector electrode 80, and the n-type buffer layer 12 is directly connected to the collector electrode 80. That is, a part of the p-type collector layer 11 is removed, and there is a portion in which the collector electrode 80 as the first main electrode is electrically connected to the n ⁻ -type base layer 13 without passing through the p-type collector layer 11. .

The MOSFET in the main cell 90 of the semiconductor device 2 has the same effect as the semiconductor device 1. However, in the semiconductor device 2, since a part of the n-type buffer layer 12 is connected to the collector electrode 80, the potential of the collector electrode 80 is, for example, the ground potential, and the emitter electrode 81 is higher than the ground potential. Even when a potential is applied (forward bias), a current can flow from the emitter electrode 81 through the p-type base layer 16, the n-type barrier layer 14, the n ⁻ -type base layer 13, the n-type buffer layer 12, and the collector electrode 80. it can.

That is, the main cell 90 of the semiconductor device 2 includes a diode in addition to the MOSFET. For example, in the main cell 90, an n-type buffer layer 12 and an n ⁻ -type base layer 13 are provided on the collector electrode 80, and the n-type barrier layer 1 is provided on the n ⁻ -type base layer 13.
4, and a p-type base layer 16 is provided on the n-type barrier layer 14. An emitter electrode 81 is connected to the p-type base layer 16 via a p ^{+ -type} contact layer 18 or an n ⁺ -type emitter layer 17. That is, when the emitter electrode 81 is an anode and the collector electrode 80 is a cathode, a pn diode is formed between the anode and the cathode.

In the semiconductor device 2, the bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located closer to the collector electrode 80 than the lower ends of the trenches 20, 23, 26. n-type barrier layer 14
The p-type diffusion layer 15 forms a super junction near the tips of the trenches 20 and 23.

In the built-in diode, the area can be further reduced by making the width of the main cell 90 smaller than the width of the subcell 91. Further, the impurity concentration of the n-type barrier layer 14 can be increased as in the semiconductor device 1. For this reason, the barrier property with respect to the holes injected from the anode side is improved. Therefore, in the built-in diode of the semiconductor device 2,
Hole injection from the anode side can be further suppressed.

As a method for further suppressing hole injection from the anode side, He or H ⁺ is used as the p-type base layer 16.
There is a method of injecting into the lower n ⁻ -type base layer 13. When injected into -type base layer 13, n ^{- -} the He and H ⁺ is n lifetime of holes becomes short-lived at -type base layer 13, hole injection into the internal diode can be suppressed. However, in such a method, when the temperature is high, there is a problem that a leakage current when a reverse bias is applied becomes large and a cost becomes high.

In the semiconductor device 2, an He or H ⁺ implantation process can be omitted, and a built-in diode with high durability and low cost is formed. Further, in the built-in diode, since the hole injection from the anode side is suppressed by the n-type barrier layer 14, the reverse recovery current is reduced even when switching from the forward bias to the reverse bias, and the response of the diode (response) Will improve.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the third embodiment.

  FIG. 8 is a schematic plan view of an essential part of a semiconductor device according to the third embodiment.

FIG. 7 shows a cross section taken along line XX ′ of FIG. In FIG. 8, the emitter electrode 81 and the insulating layer 70 illustrated in FIG. 7 are not displayed.

A semiconductor device 3 shown in FIG. 7 is a power semiconductor device (for example, an IGBT (Insulated Gate).
Bipolar Transistor)), the first main electrode collector electrode 80, p-type collector layer 11, n ^{− type} base layer 13, n-type barrier layer 14, p-type diffusion layer 15, and p-type A base layer 16, an n ⁺ -type emitter layer 17, trenches 20, 23, and 26, and an emitter electrode 81 that is a second main electrode are provided. Here, “collector” may be referred to as “drain”, and “emitter” may be referred to as “source”. As for the conductivity type of the impurity, the n-type is the first conductivity type and the p-type is the second conductivity type.

As shown in FIG. 7, in the semiconductor device 3, the p-type collector layer 11 is provided on the collector electrode 80 (first main electrode). An n-type buffer layer 12 is provided on the p-type collector layer 11. An n ^{− type} base layer 13 is provided on the n type buffer layer 12. The impurity concentration of the n ⁻ -type base layer 13 is lower than the impurity concentration of the n-type buffer layer 12. The n ^{− type} base layer 13 functions as a drift layer.

An n-type barrier layer 14 and a p-type diffusion layer 15 are provided on the n ⁻ -type base layer 13. The n-type barrier layers 14 and the p-type diffusion layers 15 are alternately arranged on the n ⁻ -type base layer 13. The impurity concentration of the n-type barrier layer 14 is higher than the impurity concentration of the n ⁻ -type base layer 13. The upper surface of the n-type barrier layer 14 is lower than the upper surface of the p-type diffusion layer 15. In other words, n
The shape barrier layer 14 is formed in a convex shape from the main surface of the n ⁻ -type base layer 13 toward the p-type diffusion layer 15 side. A p-type base layer 16 is provided on the n-type barrier layer 14. An n ⁺ -type emitter layer 17 and a p ⁺ contact layer are selectively provided on the surface of the p-type base layer 16. A plurality of trenches are formed from the surfaces of the p-type base layer 16 and the p-type diffusion layer 15 toward the collector electrode 80 side. The trench is provided between the p-type base layer 16 and the n-type barrier layer 14 and the p-type diffusion layer 15.

For example, the n-type barrier layer 14 is sandwiched between the p-type diffusion layers 15. Thereby, two pn junction interfaces exist on both sides of the n-type barrier layer 14. One of the two pn junction interfaces is indicated by an arrow A in the drawing, and an pn junction interface opposite to the arrow A is indicated by an arrow B.

At the junction interface between the n-type barrier layer 14 and the p-type diffusion layer 15 indicated by an arrow A, a groove-like trench 30 is formed from the surface of the p-type base layer 16 and the n ⁺ -type emitter layer 17 toward the collector electrode 80 side. Is formed. A conductor layer 32 made of, for example, polysilicon is provided in the trench 30 via an insulating film 31 such as an oxide film. The bottom surfaces (lower surfaces) of the p-type diffusion layer 15 and the n-type barrier layer 14 are located on the collector electrode 80 side from the lower end of the trench 30. The n-type barrier layer 14 and the p-type diffusion layer 15 form a super junction (superjunction) near the tip (near the lower end) of the trench 30.

Further, at the junction interface between the n-type barrier layer 14 and the p-type diffusion layer 15 indicated by the arrow B, the groove-shaped trench is formed from the surface of the p-type base layer 16 and the n ⁺ -type emitter layer 17 toward the collector electrode 80. 33 is formed. A conductor layer 35 made of, for example, polysilicon is provided in the trench 33 via an insulating film 34 such as an oxide film. The bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located on the collector electrode 80 side from the lower end of the trench 23. The n-type barrier layer 14 and the p-type diffusion layer 15 form a super junction near the tip of the trench 33. The trench 30 and the trench 33 have substantially the same depth.

Thus, in the semiconductor device 3, the bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located closer to the collector electrode 80 than the lower ends of the trenches 30 and 33. The conductor layers 32 and 35 are trench gate electrodes of the semiconductor device 3 and are electrically connected to a gate wiring (not shown). The conductor layers 32 and 35 are control electrodes that control the conduction between the n ⁺ -type emitter layer 17 and the n-type barrier layer 14.

The p ^{+ -type} contact layer 18 and the n ⁺ -type emitter layer 17 are electrically connected to the emitter electrode 81 (second main electrode). An insulating layer 70 is provided on the surfaces of the p-type diffusion layer 15, the p-type base layer 16, the n ⁺ -type emitter layer 17, and the trenches 30 and 33.

Further, as shown in FIG. 8, in the semiconductor device 3, the respective trenches 30 and 33 extend in a stripe shape substantially in parallel. The extending direction is, for example, a direction substantially parallel to the main surface of the n ⁻ -type base layer 13. A p ^{+ -type} contact layer 18 is provided adjacent to the n ⁺ -type emitter layer 17. The n ⁺ -type emitter layer 17 is in contact with the side surface of the trench 30 or the side surface of the trench 33.

7 and 8, the p-type base layer 16 is in contact with the side surface of the trench 30 or the side surface of the trench 33 below the n ⁺ -type emitter layer 17. The p-type base layer 16 is provided below the n ⁺ -type emitter layer 17 and the p ^{+ -type} contact layer 18. The p-type base layer 16 is electrically connected to the emitter electrode 81 via the n ⁺ -type emitter layer 17 or the p ^{+ -type} contact layer 18.

When the region occupied by the n-type barrier layer 14 and the p-type base layer 16 on the collector electrode 80 is the main cell 90 and the region occupied by the p-type diffusion layer 15 on the collector electrode 80 is the subcell 91, the main cell 90 and the subcell 91 extends in the direction in which the trenches 30 and 33 extend, and is alternately arranged. The main cell 90 includes conductive layers 32, 35, which are gate electrodes.
Since the p-type base layer 16, the n ⁺ -type emitter layer 17, and the n-type barrier layer 14 are provided, the MOSF
Functions as ET (Metal Oxide Semiconductor Field Effect Transistor). Therefore, the impurity concentration and area of the p-type base layer 16 and the n ⁺ -type emitter layer 17 in the main cell 90 are determined according to the performance required for the MOSFET. On the other hand, the impurity concentration of the n-type barrier layer 14 is higher than the impurity concentration of the n ⁻ -type base layer 13. However, n
The impurity concentration is adjusted so that the depletion layer sufficiently spreads from the pn junction interface between the p-type barrier layer 14 and the p-type diffusion layer 15.

Incidentally, p-type collector layer 11, n-type buffer layer 12, n ^- -type base layer 13, n-type barrier layer 14, p-type diffusion layer 15, p-type base layer 16, ^{n +} -type emitter layer 17, ^{p +} -type contact The material of the layer 18 is mainly composed of silicon (Si), for example. The material of the collector electrode 80 and the emitter electrode 81 is metal. The material of the insulating films 31 and 34 is, for example, silicon oxide (SiO ₂ ).

  Next, functions and effects of the semiconductor device 3 will be described.

  FIG. 9 is a diagram for explaining the function and effect of the semiconductor device 3.

The potential of the emitter electrode 81 of the semiconductor device 3 shown in FIG. 9 is, for example, a ground potential, and a potential higher than the threshold is applied to the conductor layers 32 and 35 in a state where a potential higher than the ground potential is applied to the collector electrode 80. To do. As a result, a channel is formed in a region in contact with the insulating films 31 and 34 in the p-type base layer 16. As a result, the MOSFET formed in the main cell 90 is turned on, and electrons flow from the n ⁺ -type emitter layer 17 to the n-type barrier layer 14 through the channel (see arrow e (electron) in the figure). At this time, holes flow from the p-type collector layer 11 to the n ⁻ -type base layer 13 through the n-type buffer layer 12 (see arrow h (hole)). As a result, a current flows between the collector electrode 80 and the emitter electrode 81.

In the semiconductor device 3, since the n-type barrier layer 14 having a higher impurity concentration than the n ⁻ -type base layer 13 is provided in the main cell 90 in a convex shape, a path of electrons flowing through the n-type semiconductor layer is provided. To increase. For this reason, in the semiconductor device 3, the on-resistance becomes low.

On the other hand, when a potential lower than the threshold is applied to the conductor layers 32 and 35 of the semiconductor device 3, the channel disappears from the p-type base layer 16, and the MOSFET formed in the main cell 90 is turned off. As a result, the voltage between the collector electrode 80 and the emitter electrode 81 increases, and n
A positive potential is conducted from the collector electrode 80 through the p-type collector layer 11, the n-type buffer layer 12, and the n ⁻ -type base layer 13 to the type barrier layer 14. On the other hand, the p-type diffusion layer 15 includes the insulating film 3.
Since it is coupled to the conductor layers 32 and 35 via 1 and 34, the potential is relatively lower than the voltage of the collector electrode 80. As a result, a positive potential is applied to the n ⁻ -type base layer 13 and the n-type barrier layer 14, and a negative potential is applied to the p-type diffusion layer 15.

In the semiconductor device 3, a super junction is formed by the n-type barrier layer 14 and the p-type diffusion layer 15 near the tips of the trenches 30 and 33. Therefore, trench 20,
A depletion layer expands in the main cell 90 from the pn junction interface near the tip of 23. As a result, avalanche breakdown at the junction interface between the p-type base layer 16 and the n-type barrier layer 14 is suppressed.
Further, since the depletion layer is expanded, the electric field strength in the vicinity of the tips of the trenches 30 and 33 is relaxed, and avalanche breakdown that can occur in the vicinity of the tips of the trenches is suppressed. Further, by forming the super junction, the impurity concentration of the n-type barrier layer 14 can be increased, and the saturation voltage Vce (sat) between the collector electrode 80 and the emitter electrode 81 can be reduced.

(Fourth embodiment)
FIG. 10 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the fourth embodiment.

A semiconductor device 4 shown in FIG. 10 is a reverse conduction type power semiconductor device (for example, RC (Reverse
Conducting) -IGBT). In the semiconductor device 4, the p-type collector layer 11 is selectively provided on the collector electrode 80. For example, in the main cell 90, the p-type collector layer 11 is not provided on the collector electrode 80, and the n-type buffer layer 12 is directly connected to the collector electrode 80. That is, a part of the p-type collector layer 11 is removed, and there is a portion in which the collector electrode 80 as the first main electrode is electrically connected to the n ⁻ -type base layer 13 without passing through the p-type collector layer 11. .

The MOSFET in the main cell 90 of the semiconductor device 4 has the same effect as the semiconductor device 3. However, in the semiconductor device 4, since a part of the n-type buffer layer 12 is connected to the collector electrode 80, the potential of the collector electrode 80 is, for example, the ground potential, and the emitter electrode 81 is higher than the ground potential. Even when a potential is applied (forward bias), a current can flow from the emitter electrode 81 through the p-type base layer 16, the n-type barrier layer 14, the n ⁻ -type base layer 13, the n-type buffer layer 12, and the collector electrode 80. it can.

That is, the main cell 90 of the semiconductor device 4 includes a diode in addition to the MOSFET. For example, in the main cell 90, an n-type buffer layer 12 and an n ⁻ -type base layer 13 are provided on the collector electrode 80, and the n-type barrier layer 1 is provided on the n ⁻ -type base layer 13.
4, and a p-type base layer 16 is provided on the n-type barrier layer 14. An emitter electrode 81 is connected to the p-type base layer 16 via a p ^{+ -type} contact layer 18 or an n ⁺ -type emitter layer 17. That is, when the emitter electrode 81 is an anode and the collector electrode 80 is a cathode, a pn diode is formed between the anode and the cathode.

In the semiconductor device 4, the bottom surfaces of the p-type diffusion layer 15 and the n-type barrier layer 14 are located closer to the collector electrode 80 than the lower ends of the trenches 30 and 33. The n-type barrier layer 14 and the p-type diffusion layer 15 form a super junction near the tips of the trenches 30 and 33.

In the built-in diode, the area can be further reduced by providing the trenches 30 and 33 on both sides of the main cell 90. Further, the impurity concentration of the n-type barrier layer 14 can be increased similarly to the semiconductor device 3. For this reason, the barrier property with respect to the holes injected from the anode side is improved. Therefore, in the built-in diode of the semiconductor device 4,
Hole injection from the anode side can be further suppressed.

As a method for further suppressing hole injection from the anode side, He or H ⁺ is used as the p-type base layer 16.
There is a method of injecting into the lower n ⁻ -type base layer 13. When injected into -type base layer 13, n ^{- -} the He and H ⁺ is n lifetime of holes becomes short-lived at -type base layer 13, hole injection into the internal diode can be suppressed. However, in such a method, when the temperature is high, there is a problem that a leakage current when a reverse bias is applied becomes large and a cost becomes high.

In the semiconductor device 4, an He or H ⁺ implantation process can be omitted, and a built-in diode with high durability and low cost is formed. Further, in the built-in diode, since the hole injection from the anode side is suppressed by the n-type barrier layer 14, the reverse recovery current is reduced even when switching from the forward bias to the reverse bias, and the response of the diode (response) Will improve.

(Fifth embodiment)
Note that a modification of the structure shown in FIGS. 1 and 7 when the trench becomes shallow will be described.

  FIG. 11 is a schematic cross-sectional view of a relevant part of a semiconductor device according to the fifth embodiment.

In the semiconductor device 5 shown in FIG. 11, the trenches 40, 43, 60, 63 are configured to be shallower than the trenches 20, 23, 26 of the semiconductor device 1 and the trenches 30, 33 of the semiconductor device 3. A conductor layer 42 is formed in the trench 40 via an insulating film 41. A conductor layer 45 is formed in the trench 43 via an insulating film 44. A conductor layer 62 is formed in the trench 60 via an insulating film 61. In the trench 63, the insulating film 6
A conductor layer 65 is formed via 4. The p-type base layer 16 is located between the trenches 40 and 43, and the n ⁺ -type emitter layer 17 is in contact with each of the trenches 40 and 43. The conductor layers 62 and 65 are connected to the emitter electrode 81.

For example, when the trenches 20, 23, and 26 of the semiconductor device 1 shown in FIG. 1 are shallow, the distance between the p-type diffusion layer 15 and the p-type base layer 16 is apparently shortened.

Then, the p-type base layer 16, the n-type barrier layer 14, the p-type diffusion layer 15, and the n ⁻ -type base layer 13.
The parasitic pnpn thyristor constituted by the above becomes easy to operate, the turn-off during high current density operation cannot be controlled, and element destruction may occur.

However, in the semiconductor device 5, in order to avoid this phenomenon, the distance between the super junction formed by the n-type barrier layer 14 and the p-type diffusion layer 15 and the p-type base layer 16 is interposed between the trenches 40 and 43. This makes the length of the parasitic pnpn thyristor difficult to operate. Thereby, in the semiconductor device 5, it is possible to avoid element destruction due to turn-off failure.

Furthermore, with respect to the semiconductor device 3 shown in FIG. 7, the potentials of the conductor layers 42 and 45 that are gate electrodes are shielded from the p-type diffusion layer 15 by the conductor layers 62 and 65 that are emitter shield electrodes. Therefore, the conductor layers 42 and 45 that are gate electrodes are not easily affected by the potential fluctuation of the p-type diffusion layer 15.

Here, the p-type semiconductor layers 67 and 68 between the trench 40 and the trench 60 and between the trench 43 and the trench 63 can be made to have a floating potential, whereby the emitter-collector resistance can be lowered. However, at the time of switching, gate capacitance (capacitance between gate and drain) is caused by potential fluctuation of the p-type semiconductor layers 67 and 68 which are floating potential.
May increase. However, in the semiconductor device 5, the volume of the p-type semiconductor layers 67 and 68 is smaller than that of the p-type diffusion layer 15. Therefore, the gate capacitance can be further reduced.

Further, when the p-type semiconductor layers 67 and 68 are connected to the emitter electrode 81 through a resistance element, p
The potential fluctuations of the semiconductor layers 67 and 68 are suppressed, and the gate capacitance is further reduced. In addition,
The resistance between the emitter and the collector can be further reduced by reducing the volume of the p-type semiconductor layers 67 and 68.

The resistor connecting the p-type semiconductor layers 67 and 68 to the emitter electrode 81 may be formed of polysilicon, or a part of the p-type semiconductor layers 67 and 68 may be connected to the emitter electrode 81.

(Sixth embodiment)
FIG. 12 is a main part diagram of an AC / DC conversion circuit including an inverter circuit.

For example, as shown in FIG. 12, the AC voltage supplied from the AC power source 75 is converted into a converter 7.
6 is converted into a DC voltage. A positive voltage is output from the output terminal 95 of the converter 76, and a negative voltage is output from the output terminal 96. The output terminals 95 and 96 are connected to the inverter 50.

The inverter 50 is a three-phase inverter circuit having a so-called 6in1 structure (a structure in which six elements 51 to 56 are included in one circuit), and each of the switching elements 51t to 56t,
The diodes 51d to 55d are connected in reverse parallel. Switching elements 51t to 56
t is, for example, an IGBT, and the diodes 51d to 55d are, for example, FRD (First
Recovery Diode).

The switching element 51t and the switching element 52t are connected in series, the switching element 53t and the switching element 54t are connected in series, and the switching element 5
5t and the switching element 56t are connected in series. The switching elements 51t, 53t, 55t are connected to the output terminal 95, and the switching elements 52t, 54t are connected.
t and 56 t are connected to the output terminal 96. Further, an intermediate point between the switching element 51t and the switching element 52t is connected to the output terminal 97, and the switching element 53t
The intermediate point between the switching element 54 t and the switching element 54 t is connected to the output terminal 98, and the intermediate point between the switching element 55 t and the switching element 56 t is connected to the output terminal 99. From the output terminals 97, 98, 99, a three-phase AC voltage is obtained.

If the semiconductor device 2 described above is used, inverters that individually cite IGBTs and FRDs (First Recovery Diodes) can be integrated by one semiconductor device 2. Thereby, a circuit area and cost are reduced. In particular, when the semiconductor device 2 is used, the response of the built-in diode is improved. Therefore, the inverter 50 with high responsiveness is formed. In addition,
The same effect can be obtained by replacing the semiconductor device 2 with the semiconductor device 4.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the present invention as long as they have the characteristics of the present invention. For example, the elements included in each of the specific examples described above and their arrangement, materials, conditions, shapes, sizes, and the like are not limited to those illustrated, but can be changed as appropriate. For example, it can be diverted to a MOSFET from which the p-type collector layer 11 is removed.

In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. The structure is also included in the embodiment, and the same effect is obtained.

Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. This embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. This embodiment and its modifications are included in the scope and gist of the invention,
It is included in the scope of the invention described in the claims and the equivalents thereof.

1,2,3,4,5,100 semiconductor device 11 p-type collector layer 12 n-type buffer layer 13,130 n ^- -type base layer 14, 140 n-type barrier layer 15, 150 p-type diffusion layer 16 p-type base layer 17 n ^{+ type} emitter layer 18 p ^{+ type} contact layer 20, 23, 26, 30, 33, 40, 43, 60, 63 Trench 21, 24, 27, 31, 34, 41, 44, 61, 64 Insulating film 22 , 25, 28, 32, 35, 42, 45, 62, 65 Conductor layer 50 Inverter 51d Diode 51t, 52t, 53t, 54t, 55t, 56t Switching element 67, 68 P-type semiconductor layer 70 Insulating layer 75 AC power supply 76 Converter 80 Collector electrode 81 Emitter electrode 90 Main cell 91 Subcell 95, 96, 97, 98, 99 Output terminal

Claims (3)

A base layer of a first conductivity type;
A first conductivity type barrier layer provided on the first conductivity type base layer and having an impurity concentration higher than that of the first conductivity type base layer;
A diffusion layer of a second conductivity type provided adjacent to the barrier layer;
A second conductivity type base layer provided on the barrier layer;
A trench provided in contact with the barrier layer, the diffusion layer, and the base layer of the second conductivity type so that a bottom portion is positioned in the barrier layer and the diffusion layer;
A first conductor layer provided in the trench via an insulating film;
A first electrode electrically connected to the base layer of the first conductivity type;
A second electrode electrically connected to the second conductivity type base layer;
A semiconductor device. A control electrode provided in contact with the base layer of the second conductivity type and provided in the trench provided between the barrier layer and the second electrode via the insulating film;
A first conductivity type emitter layer that is in contact with the trench and is selectively provided on a surface of the second conductivity type base layer;
The semiconductor device according to claim 1, further comprising: 3. The semiconductor device according to claim 1, further comprising a collector layer of a second conductivity type between the first electrode and the base layer of the first conductivity type.

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