JP2007128926A - Semiconductor device for rectification and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the off characteristics of a semiconductor device for rectification in a structure, where a p<SP>+</SP>-type layer is provided at the bottom of a trench, an n-type layer is highly concentrated at a projection, and contact with an electrode material is allowed to be ohmic contact. <P>SOLUTION: In the semiconductor device for rectification, a first lightly doped conductive semiconductor layer is composed on a first heavily doped conductive semiconductor, a plurality of trenches are formed from the surface of the first lightly doped conductive semiconductor layer, and a second-conductive semiconductor layer is formed at the bottom of the trench of the first lightly doped conductive semiconductor layer. In the semiconductor device for rectification, the first heavily doped conductive semiconductor layer is provided within the surface of the first lightly doped conductive semiconductor layer at the projection of the trench. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a rectifying semiconductor device, and more particularly to a technique for improving off characteristics of a rectifying semiconductor device.

Conventionally, Schottky barrier semiconductor devices and the like are high-efficiency semiconductor devices for rectification. For example, as shown in FIG. 4, low resistance n ⁺ type layer 1 (n type semiconductor layer), n type layer 2 (n type semiconductor layer), p ⁺ type layer 3 (p type semiconductor layer), insulator layer 4 , Schottky contact metal layer 5, ohmic electrode 6, trench recess 7, channel 8 in n-type layer 2, Schottky contact surface e extending to n-type layer 2 side, depletion layer 9, n-type layer 2 side It consists of a depletion layer 10 and the like extending from the p ⁺ type layer 3. Then, a Schottky contact surface e is formed on the upper surface of the convex portion on the surface of the n ⁺ type layer 2 provided with the trench 7, and a p ⁺ type layer 3 is formed on the bottom of the concave portion. Further, the insulating layer 4 is formed on the convex side wall portion, and the p ⁺ -type layer 3 and the metal layer 5 forming the Schottky contact surface e are electrically connected to the same potential. Further, the depletion layer 9 and the depletion layer 10 are configured not to conduct at least at the time of zero voltage bias. Here, the depletion layers 9 and 10 are depletion layers when the anode A and the cathode K are set to zero voltage bias.

Patent Documents 1 and 2 are known as the structure described above. In these Patent Documents 1 and 2, a p-type layer is provided in the trench recess for the purpose of improving the characteristics of the Schottky diode. In particular, in Patent Document 1, a high-efficiency, high-speed rectifying semiconductor device that maintains a high electron potential in the reverse characteristics without increasing the channel series resistance of the forward characteristics and eliminates the voltage dependence of the reverse leakage current. Has been proposed to get. Patent Document 3 proposes an ohmic connection by providing an n ⁺ layer in a Schottky contact portion.
JP 05-63184 A JP 2000-216409 A JP-A-60-74582

However, with the configuration described with reference to FIG. 4, since holes are injected from the p ⁺ -type layer 3 in the on state, the forward voltage is lower than that of the Schottky diode, but the trench protrusion is not Schottky. In the process of changing from on to off because of contact, the efficiency of extracting electrons near the anode is lowered, and there is a problem that a surge current in the reverse direction is large at the time of transition from on to off.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device for rectification that improves the off-characteristic by making the contact with the electrode material ohmic contact.

  A low-concentration first conductive semiconductor layer is formed on a high-concentration first conductive semiconductor that is one embodiment of the present invention, and a plurality of trenches are formed from the surface of the low-concentration first conductive semiconductor layer. In the rectifying semiconductor device in which the second conductivity type semiconductor layer is formed at the bottom of the trench, the high concentration first conductivity type semiconductor layer is provided on the surface of the low concentration first conductivity type semiconductor layer of the convex portion of the trench. The configuration is as follows.

  Further, a low concentration n-type semiconductor layer is formed on a high concentration n-type substrate according to another aspect of the present invention, a plurality of trenches are formed from the surface of the low concentration n-type semiconductor layer, and a p-type semiconductor is formed at the bottom of the trench. In the rectifying semiconductor device in which a layer is formed, an anode n region formed on the surface of the low-concentration n-type semiconductor layer of the convex portion of the trench, an insulator layer formed on a side wall portion of the trench, and the trench The p-type semiconductor layer formed on the bottom, the anode that is a metal film connected to the anode n region and the p-type semiconductor layer through a contact hole, and the back surface on the high-concentration n-type substrate side. And a cathode having a metal film.

  With the above configuration, the configuration in which the n-type semiconductor is less likely to form an ohmic contact is improved, the ohmic contact is obtained by increasing the impurity concentration on the surface, and diode characteristics with a low forward voltage are obtained. Moreover, a high-speed diode can be obtained.

  In another aspect of the present invention, a low concentration n-type semiconductor layer is formed on a high concentration n-type substrate, a plurality of trenches are formed on the surface of the low concentration n-type semiconductor layer, and a p-type semiconductor is formed at the bottom of the trench. In the method of manufacturing a rectifying semiconductor device for forming a layer, an insulator layer is formed on a side wall portion of the trench, an anode n region is formed on the surface of the low concentration n-type semiconductor layer of the convex portion of the trench, and the trench A contact hole is formed on the surface of the low-concentration n-type semiconductor layer and the bottom of the trench, and the anode n region and the p-type semiconductor layer are connected to the anode metal by the contact hole, and the high-concentration n A metal film for cathode is connected to the back surface on the mold substrate side.

  The above manufacturing method improves the structure in which n-type semiconductors are less likely to form ohmic contact without increasing the number of manufacturing steps, obtains ohmic contact by increasing the impurity concentration on the surface, and provides high-speed diode characteristics with low forward voltage. Is obtained.

  According to the present invention, by providing an n-type electron extraction portion, it contributes to conduction in the on state, while in the process of changing from on to off, electrons in the vicinity of the anode are extracted, thereby reducing the carrier concentration in the vicinity of the anode. Thus, the off characteristics can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Example 1
1A and 1B show a manufacturing procedure of a diode as an example of a rectifying semiconductor device. In step S1, an n / n ⁺ substrate composed of an n ⁺ -type layer 101 (high-concentration n-type substrate) and an n-type layer 102 (low-concentration n-type semiconductor layer) as a first conductive semiconductor for manufacturing a diode. 100 is prepared. FIG. 1A (1-1) shows a state of the n / n ⁺ substrate 100 formed as described above. In addition, a figure is a schematic diagram and a dimension ratio differs from actual. For example, an impurity concentration of 2 × 10 ²⁰ (cm ⁻³ ) is diffused on the surface, and an impurity concentration of 7 × is formed on the n ⁺ type layer 101 (high concentration n-type substrate) which is an n-type low-resistance semiconductor substrate by an epitaxial growth method or the like. An n-type layer 102 (low-concentration n-type layer) having a thickness of 10 ¹³ (cm ⁻³ ) and a thickness of 30 to 40 (μm) is formed. At this time, the thickness of the n / n ⁺ substrate 100 is about 255 (μm). Here, phosphorus is used as the n-type impurity, but another impurity such as arsenic may be used. A plurality of impurities such as arsenic and phosphorus may be used at the same time.

In step S2, trenches 103a, 103b,... Are formed on the surface of the n-type layer 102 of the n / n ⁺ substrate 100 manufactured in S1 by dry etching or the like. FIG. 1A (1-2) shows the state of trench formation. For example, an oxide film A (SiO 2) is formed on the surface of the n-type layer 102. Thereafter, a resist is spin-coated on the surface of the oxide film A, and the resist is patterned by a photolithography technique. Then, trenches 103a, 103b,... May be formed by dry etching such as RIE (Reactive Ion Etching) using the patterned resist as an etching mask.

In step S3, for example, p-type impurities are introduced into the bottoms of the trenches 103a, 103b,... To form second conductivity type semiconductors, and anode p regions 104a, 104b,. FIG. 1A (1-3) shows a state after introduction of p-type impurities in the lower part of the trench. For example, a p-type impurity is introduced into the n-type layer 102 at the bottom of the trenches 103a, 103b,... And p-type impurities are introduced to selectively form anode p-type layers 104a, 104b,. The introduction of the p-type impurity forms an oxide film B inside the trenches 103a, 103b. Then, the oxide film B at the bottom of the trenches 103a, 103b... Is removed by anisotropic etching such as RIE. Thereafter, masking is performed with an ion implantation mask or the like, and selective ion implantation is performed at an appropriate position of the n-type layer 102 exposed at the bottom of the trenches 103a, 103b. For example, implantation is performed with the substrate temperature = room temperature to 700 (° C.), here, the acceleration energy = about 50 k (eV) and the total dose = about 1 × 10 ¹⁴ (cm ⁻² ). As a result, an injection layer is formed in a region near the bottom of the trench. Here, boron is used as the p-type impurity.

  In step S4, the anode p regions 104a, 104b,... Are diffused to have a desired spread, and the insulating film 105 is formed. FIG. 1A (1-4) shows a state after both the diffusion of the p-type impurity at the trench bottom and the formation of the insulating film 105 are completed. For example, the oxide films A and B and the ion implantation mask are removed, and the p-type impurities in the anode p-type regions 104a, 104b,... Are diffused by activation heat treatment at a substrate temperature of about 1000 to 1100 (° C.). To do. At this time, it is formed in a region having a depth of about 0.25 to 1.0 (μm) from the bottom of the trench.

  In step S5, openings are formed in the insulating film 105 on the surface of the n-type layer 102 sandwiched between the trenches 103a, 103b,... To form anode n regions 106a, 106b, 106c,. FIG. 1B (1-5) shows a state after the anode n region is formed on the surface of the n-type layer 102. For example, the removal of the insulating film 105 formed on the surface of the n-type layer 102 by the activation heat treatment is performed by directional etching such as RIE.

After that, masking is performed with an ion implantation mask or the like to expose the anode n regions 106 a, 106 b, 106 c... On the surface of the n-type layer 102, and selective ion implantation is performed at an appropriate position of the n-type layer 102. At this time, for example, arsenic is used as the ion type, and the acceleration energy is about 100 k (eV) and the total dose is about 1 × 10 ¹⁵ (cm ⁻² ). As a result, an injection layer is formed. Thereafter, the ion implantation mask is removed, and n-type impurities in the anode n-type regions 106a, 106b, 106c,... Are selectively diffused by activation heat treatment at a substrate temperature of about 1000 (° C.).

  In step S6, contact holes 107a, 107b, 107c, 107d... Are formed in the insulating film 105 on the anode p regions 104a, 104b... And the anode n regions 106a, 106b, 106c. FIG. 1B (1-6) shows a state after the contact hole is formed. For example, the oxide film C formed in the anode n-type regions 106a, 106b, 106c... On the surface of the n-type layer 102 by the activation heat treatment and the insulating film 105 formed in the trenches 103a, 103b. The removal is performed by anisotropic etching such as RIE to form contact holes 107a, 107b, 107c, 107, d107e,.

In step S7, a front electrode, a protective film, and a back electrode are formed. Although not described in detail here, as for the surface electrode, when a metal is embedded in the trenches 103a, 103b..., An Al film or the like is vapor-deposited with an appropriate thickness as a metal on the surface of the n-type layer 102. As the metal film, a metal such as Ti or Mo, or various metal silicides may be used. Next, for example, a metal film is deposited on the back surface of the n ⁺ -type layer 101 to form a back electrode (cathode electrode). Then, for example, a sintering process is performed at 400 (° C.) in a reducing atmosphere for about 30 minutes to further improve ohmic contact.

  With the above structure, the n-type electron extraction part also contributes to conduction in the on state, while in the process of changing from on to off, the electrons near the anode are extracted to reduce the carrier concentration near the anode and improve the off characteristics. ing.

When off, the n ⁺ -type layer of the trench protrusion and the n layer of the cathode are electrically cut off by a depletion layer extending from both anode p regions of the trench recess. In the on state, holes are injected from both anode p regions of the trench recess, and the diode between the anode p region and the cathode and the n ⁺ layer of the trench projection and the cathode are also conductive with low resistance.

In the process of switching from on to off, electrons in the vicinity of the anode are extracted from the n ⁺ layer of the trench protrusion, so that the amount of accumulated carriers is reduced, and as a result, a normal diode is injected with low injection (= small current). It becomes the same as the state in use, the surge current in the reverse direction is reduced, and the off time is also shortened.

  The electrical characteristics of the rectifying semiconductor device manufactured as described above, the conventional structure of FIG. 4 and the pn diode were evaluated by simulation. FIGS. 2A, 2B, and 2C show a structure at the time of simulation (one cell, 7 μm from the upper surface of the semiconductor main part). FIG. 2A shows the semiconductor device, which is a diode that obtains a rectifying action using a potential barrier generated between a p-type impurity layer and an n-type impurity layer. 2B shows a Schottky diode having the structure of FIG. 4, and FIG. 2C shows a pn diode.

(This semiconductor device)
The trench 103 has a width of 2 (μm), a pitch of 4 (μm), and a depth of 5 (μm). The anode p region 104 was diffused at the bottom of the trench 103 with a peak concentration of 2 × 10 ¹⁸ (cm ⁻³ ) and a depth of about 1 (μm). In the simulation, the inside of the trench 103 is a uniform p-type Si layer having a concentration of 2 × 10 ¹⁹ (cm ⁻³ ). The anode n region 106 has a peak concentration of 1 × 10 ¹⁹ (cm ⁻³ ) and a depth of about 0.3 (μm) on the surface of the n-type layer 102, and is in ohmic contact with the surface electrode. It was supposed to be. The concentration of the n-type layer 102 was 7 × 10 ¹³ (cm ⁻³ ).

(Schottky diode with the structure of FIG. 4)
The trench structure and the anode p region are the same as the above (rectifying semiconductor device of the present invention) except that the anode n region 106 is not provided and the surface electrode is in Schottky contact.

(Pn diode)
The pn diode was not provided with the trench 103, and was a uniform p-type Si layer having a concentration of 2 × 10 ¹⁹ (cm ⁻³ ) from the simulation surface to 5 (μm) (the trench depth of the structure of the semiconductor device). The anode p region has a peak concentration of 2 × 10 ¹⁸ (cm ⁻³ ) at a depth of 5 (μm) and an expansion of about 1 (μm) at an n-type layer deeper than the surface by 5 μm (the same concentration as the n-type layer 102). It was assumed that it was spreading. That is, the projecting portion of the structure of the semiconductor device is removed, and the inside of the trench 103 is spread over the whole.

FIG. 3 shows the result of comparison of reverse recovery characteristics at the power supply voltage = 300 V by simulation. The vertical axis shows current (A) and voltage (V), and the horizontal axis shows time (μsec). (A), (b), and (c) in the figure correspond to (a), (b), and (c) in the structure of FIG.
(A) The current value of this semiconductor device is about −25 (A) at a minimum value of about 0.35 (μsec) and about 0 (A) at about 0.55 (μsec). (B) The current value of the Schottky diode is about −40 (A) at a minimum value of about 0.5 (μsec) and about 0 (A) at about 0.8 (μsec). (C) The current value of the pn diode is about 0.69 (μsec), the minimum value is about −60 (A), and about 1.1 (μsec) is substantially 0 (A).

  In addition, (a) the voltage value of the semiconductor device converges to the power supply voltage in about 1 (μsec) time. (B) The voltage value of the Schottky diode is approximately 1.2 (μsec) and is generally converged to the power supply voltage. (C) It can be seen that the voltage value of the pn diode does not converge even after 1.6 (μsec).

  In the figure, an ellipse (A) and an arrow extending from the ellipse (A) indicate that the waveforms (a), (b), and (c) indicated by solid lines are current values having a scale on the left side of the graph. In the figure, an ellipse (B) and an arrow extending from the ellipse (B) indicate that the waveforms (a), (b), and (c) indicated by broken lines are voltage values having a scale on the right side of the graph.

  As is apparent from the simulation results, it can be seen that the semiconductor device of the present invention responds faster than a Schottky diode having a similar structure. It should be noted that it is the anode p region spacing rather than the trench spacing that is strongly related to the electrical characteristics. The narrower the spacing, the lower the leakage current, but the less effective the reverse recovery.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a figure which shows simulation conditions. (A) It is a figure which shows the structure of this semiconductor device. (B) It is a figure which shows the structure of a Schottky diode. (C) It is a figure which shows the structure of a pn diode. It is a figure which shows a simulation result. It is a figure which shows a prior art example.

Explanation of symbols

100 ... n / n ⁺ substrate 101 ... n ⁺ type layer,
102 ... n-type layer,
103 ... Trench 103a, 103b ...
104... Anode p region 104a, 104b.
105 ... Insulating film,
106 ... Anode n-type region 106a, 106b, 106c ...
107 ... contact holes 107a, 107b, 107c, 107d, 107e ...

Claims (3)

A low-concentration first conductive semiconductor layer is formed on the high-concentration first conductive semiconductor,
A plurality of trenches are formed from the surface of the low-concentration first conductive semiconductor layer,
In the rectifying semiconductor device in which the second conductivity type semiconductor layer is formed at the bottom of the trench,
A rectifying semiconductor device, wherein a high-concentration first conductive semiconductor layer is provided on a surface of the low-concentration first conductive semiconductor layer in a convex portion of the trench. A low-concentration n-type semiconductor layer is formed on a high-concentration n-type substrate;
A plurality of trenches are formed from the surface of the low-concentration n-type semiconductor layer,
In a rectifying semiconductor device in which a p-type semiconductor layer is formed at the bottom of the trench,
An anode n region formed on the surface of the low concentration n-type semiconductor layer of the convex portion of the trench;
An insulator layer formed on the sidewall of the trench;
The p-type semiconductor layer formed at the bottom of the trench, the anode which is a metal film connected to the anode n region and the p-type semiconductor layer through a contact hole,
A cathode that is a metal film formed on the back surface on the high-concentration n-type substrate side,
A semiconductor device for rectification characterized by the above. A low-concentration n-type semiconductor layer is formed on a high-concentration n-type substrate,
Forming a plurality of trenches on the surface of the low-concentration n-type semiconductor layer;
In the method of manufacturing a rectifying semiconductor device in which a p-type semiconductor layer is formed at the bottom of the trench,
Forming an insulator layer on the sidewall of the trench;
Forming an anode n region on the surface of the low concentration n-type semiconductor layer of the convex portion of the trench;
Forming a contact hole at the surface of the low concentration n-type semiconductor layer of the convex portion of the trench and at the bottom of the trench;
Connecting the anode n region and the p-type semiconductor layer to an anode metal through the contact hole;
A metal film for a cathode is connected to the back surface on the high-concentration n-type substrate side;
A method for manufacturing a rectifying semiconductor device.