CN101783345A - Grooved semiconductor rectifier and manufacturing method thereof - Google Patents
Grooved semiconductor rectifier and manufacturing method thereof Download PDFInfo
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- CN101783345A CN101783345A CN201010124526A CN201010124526A CN101783345A CN 101783345 A CN101783345 A CN 101783345A CN 201010124526 A CN201010124526 A CN 201010124526A CN 201010124526 A CN201010124526 A CN 201010124526A CN 101783345 A CN101783345 A CN 101783345A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 239000002184 metal Substances 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 84
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- 238000000034 method Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
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- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The invention relates to a grooved semiconductor rectifier and a manufacturing method thereof. The grooved semiconductor rectifier comprises a semiconductor baseplate, a first conduction type substrate and a first conduction type drift region, wherein one or more grooves extend from the first main plane to the first conduction type drift region, one or more mesa parts are limited at the upper part of the first conduction type drift region, and the upper part of the mesa part is provided with a first conduction type injection layer; the inner wall of the groove is covered with an insulation oxide layer, and a first electrode is deposited in the groove covered with the insulation oxide layer; the first conduction type drift region is provided with a second conduction type enclosure layer corresponding to the bottom of the groove, and the bottom of the groove is coated by the second conduction type enclosure layer; a first metal layer corresponding to the upper part of the first plane is deposited on the semiconductor baseplate; and the second plane of the semiconductor baseplate is covered with a second metal layer. The invention has the advantage of low manufacturing cost, and reduces the reverse leakage current and the forward conduction voltage drop of the Schottky rectifier.
Description
Technical field
The present invention relates to a kind of semiconductor rectifier and manufacture method thereof, especially a kind of grooved semiconductor rectifier and manufacture method thereof.
Background technology
When metal contacted with semiconductor, owing to the different contact potential differences that exist of the general and semi-conductive work function of the work function of metal, the result formed potential barrier near contact-making surface, be commonly referred to Schottky barrier.Contacting with the n N-type semiconductor N with metal is example, and when metal contacted with the n N-type semiconductor N, electronics will reach a heat balance by exchange between two kinds of materials, and the Fermi level of whole knot is equated everywhere.At first, the potential barrier height that electronics is escaped and run into than escaping from semiconductor from metal, thereby, in reaching thermally equilibrated process, there is clean electron stream to flow to metal, makes the metal tape negative electricity, semiconductor tape positive electricity from semiconductor, positive charge in the semiconductor is formed by the donor ion of remaining skim positively charged after the depleted of electrons at the interface, and a such dipole layer is similar to a p+n knot.So, when the metal-semiconductor forward bias (the relative n N-type semiconductor N of metal adds positive voltage), Schottky barrier rectifier forward conduction resistance is mainly determined by the series resistance of metal-semicroductor barrier height, semiconductor regions resistance and all the other contact resistances; When the metal-semiconductor reverse bias (the relative metal of n N-type semiconductor N adds positive voltage), the depletion layer at Schottky barrier rectifier metal-semiconductor junction place broadens, the blocking-up current flowing.
Schottky barrier rectifier promptly is this unidirectional on state characteristic that has utilized Schottky barrier.Normal conditions, when rectifier has both needed forward conduction lower forward conduction voltage drop to be arranged, very high reverse blocking resistance to be arranged when needing reverse blocking again, thereby can flow through bigger forward current, can when reverse blocking, reduce reverse leakage current as much as possible again with the lower power consumption loss.
Can influence comprising of Schottky barrier rectifier forward conduction voltage drop and reverse leakage current simultaneously: the semiconductor regions resistance of schottky barrier height and Schottky barrier rectifier.Schottky barrier height is reached by selected metal material, semi-conducting material and the doping content of the contacted semiconductor regions of metal decides, usually under the prerequisite of given metal and semi-conducting material, dense more with the semiconductor regions doping content of Metal Contact, the barrier height of metal-semiconductor junction is just low more, and is just more little thereby electric current flows through the pressure drop of knot; In order to keep high anti-blocking voltage partially and little anti-leakage current partially, it is higher and thickness is thicker that the semiconductor regions of Schottky barrier rectifier typically is chosen as resistivity, to such an extent as to when the device reverse bias, electric field can be not too high partially at the interface anti-of metal-semiconductor junction, yet higher resistivity of semiconductor regions and thicker thickness can increase the rectifier forward conduction voltage drop again.Therefore, should reduce the rectifier forward conduction voltage drop as much as possible, reduce the reverse leakage current of rectifier again as far as possible, just become the important development direction of rectifier.
A kind of structure of groove-shaped Schottky barrier rectifier is disclosed among the patent CN101114670A, shown in accompanying drawing 1 among the patent CN101114670A, described groove-shaped Schottky barrier rectifier comprises the semiconductor substrate with two relative interareas, its top is the first conduction type drift region of low doping concentration, its upper surface is first interarea, the bottom of described semiconductor substrate is the first conductivity type substrate layer of high-dopant concentration, its lower surface is second interarea, one or more grooves are extended into the described first conductivity type substrate layer and are limited one or more table top portion thus by described first surface, described grooved inner surface growth has insulating barrier, be filled with first electrode in the described groove, described groove and be coated with the first metal layer above the table top portion, the first metal layer and the described first electrode ohmic contact, simultaneously with the surperficial Schottky contacts of described table top portion, form the Schottky barrier of certain altitude, the first metal layer becomes the anode electrode of Schottky barrier semiconductor device, in the described second interarea surface coverage second metal level is arranged, and forming ohmic contact with second interarea, second metal level becomes the cathode electrode of Schottky barrier semiconductor.Because the existence of groove, and gash depth vertically stretches to the substrate layer of high-dopant concentration, therefore when rectifier applies reverse voltage, there is the electric charge coupling effect between adjacent trenches, the position of maximum field intensity is displaced downwardly to trenched side-wall near zone near channel bottom by the surperficial schottky junction place in the common plane Schottky junction structure, shown in the accompanying drawing 2 of patent CN101114670A.The reduction of schottky junction place electric field strength makes reverse leakage current significantly reduce than common plane Schottky barrier semiconductor device.
Yet, because using, many rectifiers all need oppositely can bear higher blocking voltage, lower conduction voltage drop is arranged during forward conduction again, therefore, resistivity is higher, thickness is thicker if be chosen as for the first conduction type drift region in the above-mentioned patent structure, then promptly be unfavorable for reducing forward conduction voltage drop, be unfavorable for realizing stretching to the etching groove of substrate layer again; If the first conduction type drift region is chosen as less, the thinner thickness of resistivity, then can't realize high reverse blocking voltage again.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of grooved semiconductor rectifier and manufacture method thereof are provided, it is cheap for manufacturing cost, reduced rectifier reverse leakage current and rectifier forward conduction voltage drop.
According to technical scheme provided by the invention, described grooved semiconductor rectifier, on the cross section of described rectifier, comprise semiconductor substrate with two relative interareas, be positioned at first conductivity type substrate of semiconductor substrate bottom and be positioned at the first conduction type drift region on semiconductor substrate top, described first conductivity type substrate is in abutting connection with the first conduction type drift region; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of the described first conduction type drift region is first interarea of semiconductor substrate; The doping content of the described first conduction type drift region is lower than the doping content of first conductivity type substrate; Its innovation is:
One or more grooves extend into to the first conduction type drift region from described first interarea, and limit one or more table top portion on top, the first conduction type drift region; The top of described table top portion is provided with the first conduction type implanted layer; The doping content of the described first conduction type implanted layer is greater than the doping content of the first conduction type drift region;
Be coated with insulating oxide on the described trench wall, deposit first electrode in the described groove that is coated with insulating oxide; The described first conduction type drift region is provided with the second conduction type embracing layer corresponding to the bottom land of groove, and the described second conduction type embracing layer coats the bottom land of described groove; The doping content of the described second conduction type embracing layer is lower than the doping content of the first conduction type implanted layer, and the doping content of the described second conduction type embracing layer is higher than the doping content of the first conduction type drift region; Described semiconductor substrate is deposited with the first metal layer corresponding to first interarea top, and described the first metal layer and first electrode be ohmic contact mutually; Described the first metal layer and table top portion are corresponding to the surperficial ohmic contact of the first conduction type implanted layer; Be coated with second metal level on second interarea of described semiconductor substrate, described second metal level and first conductivity type substrate be ohmic contact mutually.
Described first electrode comprises conductive polycrystalline silicon.Described trench wall forms insulating oxide by heat growth or deposit.Described the first metal layer is provided with anode tap.Described second metal level is provided with cathode terminal.
The manufacture method of described grooved semiconductor rectifier comprises the steps:
A, provide the first conductive type semiconductor substrate with two relative interareas, described two relative interareas comprise first interarea and second interarea; B, on above-mentioned first interarea, the deposit hard mask layer; C, optionally shelter and the etching hard mask layer, form the hard mask of etching groove, and etching forms groove on first interarea, described groove is coated with hard mask layer corresponding to the outer remainder of notch, forms table top portion between described adjacent trenches; D, inject the ion of second conduction type on first interarea of above-mentioned semiconductor substrate, form the second conduction type embracing layer in the first conduction type drift region, the described second conduction type embracing layer coats the bottom land of groove; Hard mask layer on e, described semiconductor substrate first interarea of removal; F, insulating oxide is arranged in above-mentioned trench wall superficial growth; G, in having the groove of insulating oxide, described growth forms first electrode; H, on first interarea of above-mentioned semiconductor substrate, inject the ion of first conduction type, form the first conduction type implanted layer on table top portion top; I, on first interarea of described semiconductor substrate deposited metal, by optionally sheltering and etching sheet metal, form the first metal layer; The described the first metal layer and the first electrode ohmic contact, corresponding surface, first conduction type injection region ohmic contact in described the first metal layer and the table top portion; J, on second interarea of described semiconductor substrate, cover second metal level, the first conductivity type substrate ohmic contact of described second metal level and semiconductor substrate.
Described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.Described second metal level covers on second interarea by deposit or evaporation, the first conductivity type substrate ohmic contact of second metal level and semiconductor substrate.
The material of described semiconductor substrate comprises silicon.The doping content of the described first conduction type implanted layer is greater than the doping content of the second conduction type embracing layer.
Described " first conduction type " and " second conduction type " are among both, and for the N type semiconductor rectifier, first conduction type refers to the N type, and second conduction type is the P type; For the P type semiconductor rectifier, first conduction type is just in time opposite with the type and the N type semiconductor rectifier of the second conduction type indication.
Advantage of the present invention: 1, utilize the first highly doped conductive type layer of table top portion top and the ohmic contact of the first metal layer, greatly reduce the forward conduction voltage drop of rectifier.2, utilize second conductive type layer below the channel bottom, greatly reduce the reverse leakage current of rectifier, improved reverse blocking voltage.3, reduced the requirement of gash depth, manufacturing process is simple, and is with low cost.
Description of drawings
Fig. 1～7 are the cutaway view of the concrete implementing process of the present invention, wherein:
Fig. 1 is the cutaway view of semiconductor substrate.
Fig. 2 is the cutaway view behind the formation groove in the first conduction type drift region.
Fig. 3 is the cutaway view behind the formation second conduction type embracing layer in the first conduction type drift region.
Fig. 4 is the cutaway view that forms in groove behind the insulating oxide and first electrode.
Fig. 5 is the cutaway view after the first conduction type injection region is formed at table top portion top.
Fig. 6 is the cutaway view after forming the first metal layer on first interarea.
Fig. 7 is the cutaway view after forming second metal level on second interarea.
Fig. 8 is in the metal-semiconductor contact, and doping content of semiconductor is crossed the schematic diagram of potential barrier influence to electronics.
Embodiment
Shown in Fig. 1～7: with the N type semiconductor rectifier is example, the present invention includes N type drift region 1, N+ substrate 2, second metal level 3, cathode terminal 4, P type embracing layer 5, hard mask layer 6, anode tap 7, the first metal layer 8, insulating oxide 9, first electrode 10, groove 11, table top portion 12 and N type implanted layer 13.
Fig. 7 is the structure cutaway view of described grooved semiconductor rectifier.As shown in Figure 7: on the cross section of described semiconductor rectifier, described semiconductor rectifier comprises semiconductor substrate; Semiconductor substrate comprises N+ substrate 2 and N type drift region 1, and N type drift region 1 is in abutting connection with N+ substrate 2, and the doping content of described N type drift region 1 is lower than the doping content of N+ substrate 2.Described semiconductor substrate has two relative interareas, and semiconductor substrate is first interarea corresponding to the surface of N type drift region 1; Semiconductor substrate is second interarea corresponding to the surface of N+ substrate 2, and described second interarea is corresponding with the position of first interarea.Be provided with one or more grooves 11 in the described N type drift region 1, described groove 11 extends into N type drift region 1 from first interarea of semiconductor substrate, described groove 11 limits one or more table top portion 12 on 1 top, N type drift region, the top of described table top portion 12 is provided with N type implanted layer 13; 11 of adjacent trenches utilize the N type implanted layer 13 on table top portion 12 and described table top portion 12 tops isolated, and the doping content of described N type implanted layer 13 is higher than the doping content of described N type drift region 1.Groove 11 extends into to N type drift region 1 vertically downward from first interarea, and limits the table top portion 12 with " Wm " sectional width on 1 top, N type drift region thus, and the exemplary depth of groove 11 has 0.8 μ m-2.5 μ m approximately; The representative width of " Wm " has 1.0 μ m-2.0 μ m approximately.Groove 11 extends on three-dimensional towards periphery, and extensible be parallel striped, grid-shaped or other similar geometry, thus on three-dimensional, extend to parallel striped by the table top portion 12 that groove 11 limits, rectangle or other similar geometry.
The bottom land of described groove 11 is provided with P type embracing layer 5, and described P type embracing layer 5 coats the bottom land of groove 11.The inwall of described groove 11 is provided with insulating oxide 9, and the method that described insulating oxide 9 utilizes high temperature furnace pipe growth, chemical vapor deposition or high temperature furnace pipe growth to combine with chemical vapor deposition is grown in the inwall of groove 11.The insulating oxide that groove 11 inwalls cover is typically the heat growth and forms the insulating oxide 9 with low relatively oxide-interface defect concentration, and its typical thickness has approximately
In having the groove 11 of insulating oxide 9, the growth of described inwall forms first electrode 10 by the deposit conductive polycrystalline silicon.Deposit the first metal layer 8 on first interarea of described semiconductor substrate, described the first metal layer 8 and first electrode, 10 ohmic contact; The first metal layer 8 and table top portion are corresponding to N type implanted layer 13 surperficial ohmic contact; The first metal layer 8 forms the anode electrode of rectifier; Anode tap 7 is set on the first metal layer 8, is used to connect the power supply that needs rectification.
Be coated with second metal level 3 on the N+ substrate 2 of described semiconductor substrate, described second metal level 3 covers on the N+ substrate 2 by deposit or evaporation process, forms the cathode electrode of semiconductor rectifier; On second metal level 3 cathode terminal 4 is set, is used to connect the power end that needs rectification.The material of described semiconductor substrate comprises silicon.
The structure of above-mentioned grooved semiconductor rectifier adopts following processing step to realize:
A, provide the first conductive type semiconductor substrate with two relative interareas, described two relative interareas comprise first interarea and second interarea; Described semiconductor substrate is second interarea corresponding to the bottom surface of N+ substrate 2, and semiconductor substrate is first interarea corresponding to the upper surface of N type drift region 1, as shown in Figure 1;
B, on above-mentioned first interarea, the deposit hard mask layer; Described hard mask layer can adopt LPTEOS (plasma-enhanced tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter;
C, optionally shelter and the etching hard mask layer, form the hard mask of etching groove, and etching forms groove 11 on first interarea, covers by hard mask layer 6 corresponding to the outer remainder of groove 11 notches on described first interarea, and 11 of described adjacent trenches form table top portion; Described etching groove adopts plasma anisotropic etching, form the trenched side-wall (angle of trenched side-wall and semiconductor substrate is not less than 88 degree) of near vertical, groove 11 degree of depth need be considered the needs of component characteristic parameter, described groove 11 degree of depth are generally 0.8 μ m～2 μ m, and through behind the etching groove, hard mask layer between groove above the table top portion also keeps certain thickness, and concrete thickness need be considered follow-up injection technology condition, as shown in Figure 2;
D, on first interarea of above-mentioned semiconductor substrate, inject P type ion (as the boron ion), the concentration of described injection P type ion is greater than the concentration of N type drift region 1, owing to be coated with hard mask layer 6 corresponding to the outer remainder of groove 11 notches on first interarea, thereby only the bottom land at groove 11 forms P type embracing layer 5, described P type embracing layer 5 coats the bottom land of groove 11, as shown in Figure 3;
Hard mask layer 6 on e, described semiconductor substrate first interarea of removal is so that he operates in the enterprising Xingqi of first interarea of semiconductor substrate;
F, the method that has insulating oxide 9, described insulating oxide 9 can adopt high temperature furnace pipe growth, chemical vapor deposition or high temperature furnace pipe growth to combine with chemical vapor deposition in above-mentioned groove 11 inner wall surface growth are grown on the inwall of groove 11;
G, in described growth has the groove 11 of insulating oxide 9 the deposit conductive polycrystalline silicon, described conductive polycrystalline silicon is boiler tube growth or chemical vapour deposition (CVD) heavily doped polysilicon, remove the conductive polycrystalline silicon of semiconductor substrate by etching corresponding to first interarea, obtain being positioned at the conductive polycrystalline silicon of groove 11, thereby form first electrode 10, as shown in Figure 4;
In certain embodiments, also can be when the operation of etch polysilicon, the polysilicon except removing groove 11 is also removed the polysilicon of groove 11 internal upper parts, thereafter and remove the insulating oxide 9 that groove 11 internal upper parts do not have groove 11 sidewalls of polysilicon segment;
H, on first interarea of above-mentioned semiconductor substrate, inject the ion (as arsenic element) of N type, in table top portion 12, form N type implanted layer 13, as shown in Figure 5;
Inject ion impurity concentration greater than the aforementioned doping content that flows into the P type embracing layer 5 of below, groove 11 bottoms, form N type implanted layer 13 on table top portion 12 tops by the high temperature knot, the conduction type that is table top portion 12 tops is identical with the conduction type of N type drift region 1, and the doping content of described N type implanted layer 13 is greater than the doping content of N type drift region 1;
I, on first interarea of described semiconductor substrate deposited metal, by optionally sheltering and etching sheet metal, form the first metal layer 8; Described the first metal layer 8 and first electrode, 10 ohmic contact, N type implanted layer 13 ohmic contact on described the first metal layer 8 and table top portion 12 tops; Described the first metal layer 8 contacts with first electrode 10, forms the anode electrode of rectifier, by anode tap 7 is set on the first metal layer 8, is convenient to the first metal layer 8 and is connected with the power end that needs rectification, as shown in Figure 6;
J, on second interarea of described semiconductor substrate, cover second metal level 3, N+ substrate 2 ohmic contact of described second metal level 3 and semiconductor substrate, form the cathode electrode of rectifier, by on second metal level 3, cathode terminal 4 being set, be convenient to second metal level 3 and be connected, as shown in Figure 7 with the power end that needs rectification.
During N type semiconductor rectifier forward conduction, promptly the anode of rectifier adds forward voltage, has electrical potential difference between the anode of rectifier and negative electrode; The barrier height that contacts between metal and semiconductor is one of key factor of decision forward conduction voltage drop, and barrier height is low more, and it is just easy more that charge carrier is crossed potential barrier, and forward conduction voltage drop is also just low more.And the principal element of decision barrier height comprises: metal species, semiconductor species and with the contacted semiconductor regions doping content of metal.Fig. 8 be " modem semi-conductor devices physics " (Shi Minzhu) in 67 pages accompanying drawing, represented the energy band diagram of N type GaAs schottky barrier junction among the figure, wherein Fig. 8 (a) expression N type doping content is N
D=10
15/ cm
3, Fig. 8 (b) expression N type doping content is N
D=10
17/ cm
3, Fig. 8 (c) expression N type doping content is N
D=10
18/ cm
3, arrow has provided the shift direction when electronics is by schottky junction under the forward bias among the figure; Accompanying drawing has disclosed different levels of doping passes through potential barrier to charge carrier influence.When metal and semiconductor species are selected, just become key with the contacted semiconductor regions doping content of metal; Shown in Fig. 8 (a), under the very low situation of mixing, electronics is mainly crossed potential barrier by the mode of crossing the potential barrier top, and this situation is called thermionic emission; Shown in Fig. 8 (b), under the medium-doped situation, electronics mainly is to pass through potential barrier in the enough thin place of potential barrier in the mode of tunnelling with certain energy, and this process is called the emission of thermion field; Shown in Fig. 8 (c), in highly doped degenerate semiconductor, depletion layer is extremely thin, can tunneling barrier near the electronics at Fermi level place, and this process is known as an emission.Under the very high limiting case of mixing, the contact resistance between metal-semiconductor is very low, and it is linear that its I-E characteristic is actually, and becomes ohmic contact so contact between metal and semiconductor.
As shown in Figure 7, the forward conduction working mechanism of grooved semiconductor rectifier of the present invention is: contacting of 13 of the N type implanted layers on described the first metal layer 8 and table top portion top is ohmic contact.During forward conduction, be anode tap 7 and 4 electrical potential differences of cathode terminal of grooved semiconductor rectifier with forward, because the first metal layer 8 and 13 of N type implanted layers are ohmic contact, the contact resistance that the first metal layer 8 and N type implanted layer are 13 is very low, and N type implanted layer 13 is same conduction type with N type drift region 1, and forward conduction voltage drop contrasts in the past that rectifier reduces greatly.
As shown in Figure 7, the reverse blocking working mechanism of grooved semiconductor rectifier of the present invention is: when the anode tap 7 of rectifier and 4 of cathode terminals apply reverse voltage, the P type embracing layer 5 of N type drift region 1 below groove 11 bottoms constitutes back-biased PN junction, because P type embracing layer 5 concentration are greater than the concentration of N type drift region 1, therefore 1 extension in the N type drift region around the PN junction that anti-depletion layer can be most partially, described bearing of trend comprises horizontal direction.When the depletion layer that PN junction produced below adjacent two groove 11 bottoms contacts in the horizontal direction, the depletion layer that is connected has promptly been blocked the top of N type drift region 1 and the bottom of N type drift region 1, has also blocked simultaneously the reverse leakage circulation flow path of 4 of the anode tap 7 of rectifier and cathode terminals.Because when the P type embracing layer 5 below not having described groove 11 bottoms, the depletion layer that the electric charge coupling that reverse withstand voltage main dependence adjacent trenches is 11 produces bears, so trench semiconductor rectifier of the present invention can reduce the size of reverse leakage current greatly on the basis of above-mentioned common trench semiconductor rectifier.
The present invention is by being provided with N type implanted layer 13 on table top portion 12 tops, and described N type implanted layer 13 doping contents are bigger, makes contacting of 8 of N type implanted layer 13 and the first metal layers form ohmic contact, the pressure drop when having reduced the semiconductor rectifier forward conduction.The bottom land of groove 11 is provided with P type embracing layer 5, reduced Xiao's semiconductor rectifier anti-leakage current and forward conduction voltage drop partially, improved the puncture voltage of semiconductor rectifier, reduced groove 11 degree of depth requirements, manufacture method is simple, easy to operate, cheap for manufacturing cost.
Claims (10)
1. grooved semiconductor rectifier, on the cross section of described rectifier, comprise semiconductor substrate with two relative interareas, be positioned at first conductivity type substrate of semiconductor substrate bottom and be positioned at the first conduction type drift region on semiconductor substrate top, described first conductivity type substrate is in abutting connection with the first conduction type drift region; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of the described first conduction type drift region is first interarea of semiconductor substrate; The doping content of the described first conduction type drift region is lower than the doping content of first conductivity type substrate; It is characterized in that:
One or more grooves extend into to the first conduction type drift region from described first interarea, and limit one or more table top portion on top, the first conduction type drift region; The top of described table top portion is provided with the first conduction type implanted layer; The doping content of the described first conduction type implanted layer is greater than the doping content of the first conduction type drift region;
Be coated with insulating oxide on the described trench wall, deposit first electrode in the described groove that is coated with insulating oxide; The described first conduction type drift region is provided with the second conduction type embracing layer corresponding to the bottom land of groove, and the described second conduction type embracing layer coats the bottom land of described groove; The doping content of the described second conduction type embracing layer is lower than the doping content of the first conduction type implanted layer, and the doping content of the described second conduction type embracing layer is higher than the doping content of the first conduction type drift region; Described semiconductor substrate is deposited with the first metal layer corresponding to first interarea top, and described the first metal layer and first electrode be ohmic contact mutually; Described the first metal layer and table top portion are corresponding to the surperficial ohmic contact of the first conduction type implanted layer; Be coated with second metal level on second interarea of described semiconductor substrate, described second metal level and first conductivity type substrate be ohmic contact mutually.
2. grooved semiconductor rectifier according to claim 1 is characterized in that: described first electrode comprises conductive polycrystalline silicon.
3. grooved semiconductor rectifier according to claim 1 is characterized in that: described trench wall forms insulating oxide by heat growth or deposit.
4. grooved semiconductor rectifier according to claim 1 is characterized in that: described the first metal layer is provided with anode tap.
5. grooved semiconductor rectifier according to claim 1 is characterized in that: described second metal level is provided with cathode terminal.
6. the manufacture method of a grooved semiconductor rectifier is characterized in that, described manufacture method comprises the steps:
(a), the first conductive type semiconductor substrate with two relative interareas is provided, described two relative interareas comprise first interarea and second interarea;
(b), on above-mentioned first interarea, the deposit hard mask layer;
(c), optionally shelter and the etching hard mask layer, form the hard mask of etching groove, and etching forms groove on first interarea, described groove is coated with hard mask layer corresponding to the outer remainder of notch, forms table top portion between described adjacent trenches;
(d), on first interarea of above-mentioned semiconductor substrate, inject the ion of second conduction type, in the first conduction type drift region, form the second conduction type embracing layer, the described second conduction type embracing layer coats the bottom land of groove;
(e), the hard mask layer on described semiconductor substrate first interarea of removal;
(f), in above-mentioned trench wall superficial growth insulating oxide is arranged;
(g), in having the groove of insulating oxide, described growth forms first electrode;
(h), on first interarea of above-mentioned semiconductor substrate, inject the ion of first conduction type, form the first conduction type implanted layer on table top portion top;
(i), on first interarea of described semiconductor substrate deposited metal, by optionally sheltering and etching sheet metal, form the first metal layer; The described the first metal layer and the first electrode ohmic contact, corresponding surface, first conduction type injection region ohmic contact in described the first metal layer and the table top portion;
(j), on second interarea of described semiconductor substrate, cover second metal level, the first conductivity type substrate ohmic contact of described second metal level and semiconductor substrate.
7. according to the manufacture method of the described grooved semiconductor rectifier of claim 6, it is characterized in that: described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
8. according to the manufacture method of the described grooved semiconductor rectifier of claim 6, it is characterized in that: described second metal level covers on second interarea by deposit or evaporation, the first conductivity type substrate ohmic contact of second metal level and semiconductor substrate.
9. according to the manufacture method of the described grooved semiconductor rectifier of claim 6, it is characterized in that: the material of described semiconductor substrate comprises silicon.
10. according to the manufacture method of the described grooved semiconductor rectifier of claim 6, it is characterized in that: the doping content of the described first conduction type implanted layer is greater than the doping content of the second conduction type embracing layer.
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