CN109192786A - A kind of groove-shaped diode and preparation method thereof with the island floating P - Google Patents
A kind of groove-shaped diode and preparation method thereof with the island floating P Download PDFInfo
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- CN109192786A CN109192786A CN201810961259.0A CN201810961259A CN109192786A CN 109192786 A CN109192786 A CN 109192786A CN 201810961259 A CN201810961259 A CN 201810961259A CN 109192786 A CN109192786 A CN 109192786A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000007667 floating Methods 0.000 title claims description 11
- 238000000407 epitaxy Methods 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 238000010276 construction Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 67
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 description 4
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- -1 and when initial Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention relates to a kind of groove-shaped diode and preparation method thereof, groove anode construction includes groove, contact hole and position anode metal layer, forms the side wall for being used for spaced trenches and contact hole by groove, contact hole on the top of N-type epitaxy layer；The island P is set in N-type epitaxy layer, and the island P is located at the underface of groove slot bottom and the island P is contacted with the slot bottom of groove；The anode metal layer is filled in groove and contact hole, anode metal layer is dielectrically separated from by the side wall and bottom wall of trench oxide layer and groove in groove, anode metal layer is dielectrically separated from by the side wall and bottom wall of contact hole oxide layer and contact hole in contact hole hole wall, covers the N-type epitaxy layer Ohmic contact immediately below the anode metal layer and the anode metal layer at the top of side wall.Structure of the invention is compact, compatible with prior art, is able to achieve lower conduction voltage drop, improves reliability when high temperature, and reverse recovery time is short.
Description
Technical field
It is especially a kind of with the groove-shaped of the island floating P the present invention relates to a kind of groove-shaped diode and preparation method thereof
Diode and preparation method thereof belongs to the technical field of groove-shaped diode.
Background technique
Power rectifier is usually applied to power electronic circuit to control current direction, according to its on state characteristic and blocks energy
Power takes corresponding device often to realize rectification.When for high pressure field, the forward conduction voltage drop one of traditional PIN diode
As be higher than 0.7V (on state current density be 100A/cm2), and cut-in voltage is higher, reverse recovery time is longer.It is led in low pressure
Domain, planer schottky diode are leaked electricity larger at high temperature, and power consumption is higher, and breakdown voltage is generally in 200V or less.
TMBS rectifier was initially put forward for the first time in 1993 by B.J.Baliga, although which effectively improves plane Xiao
Problem of both the reverse leakage and breakdown voltage of special based diode, but the high temperature reliability of schottky junction undesirable is still
An existing problem, especially during hot operation.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of groove-shaped two with the island floating P are provided
Pole pipe and preparation method thereof, it is compact-sized, it is compatible with prior art, it is able to achieve lower conduction voltage drop, when improving high temperature
Reliability, reverse recovery time are short.
According to technical solution provided by the invention, the groove-shaped diode with the island floating P, including it is semiconductor-based
Plate, the semiconductor substrate include the N-type epitaxy layer of N-type substrate and the adjacent N-type substrate, and the N-type epitaxy layer is located at N
The surface of type substrate；Groove anode construction is set on the top of the N-type epitaxy layer, setting and institute at the back side of N-type substrate
State the cathode metal layer of N-type substrate Ohmic contact；
The groove anode construction includes the groove being set in N-type epitaxy layer, the contact hole positioned at the groove outer ring
And the anode metal layer above N-type epitaxy layer, between the top of N-type epitaxy layer is used for by groove, contact hole formation
Every the side wall of groove and contact hole；The island P is set in N-type epitaxy layer, the island P be located at the underface of groove slot bottom and the island P and
The slot bottom of groove contacts；
The anode metal layer is filled in groove and contact hole, and anode metal layer passes through the trench oxide layer in groove
It is dielectrically separated from the side wall and bottom wall of groove, anode metal layer passes through the contact hole oxide layer and contact hole in contact hole hole wall
Side wall and bottom wall be dielectrically separated from, cover side wall at the top of anode metal layer and the anode metal layer immediately below N-type outside
Prolong a layer Ohmic contact.
The transverse width on the island P is greater than the groove width of groove.
A kind of preparation method of the groove-shaped diode with the island floating P, the preparation method packet of the groove-shaped diode
Include following steps:
Step 1, provide semiconductor substrate, the semiconductor substrate include N-type substrate and be located at the N-type substrate just on
The N-type epitaxy layer of side, the adjacent N-type substrate of N-type epitaxy layer；
Mask layer is arranged in step 2 in the N-type epitaxy layer, and selectively shelters and etch the mask layer, with benefit
N-type epitaxy layer is performed etching with the mask layer after etching, to obtain required groove and contact hole, the contact hole is located at
The outer ring of groove；
Step 3 carries out p type impurity ion implanting above above-mentioned N-type epitaxy layer, to obtain the island P immediately below groove,
The island P is contacted with the slot bottom of groove；
Insulating oxide, the bottom of the insulating oxide covering contact hole is arranged in step 4 in above-mentioned N-type epitaxy layer
And the bottom wall and side wall of side wall, groove, and oxide layer is covered on mask layer；
Step 5, the above-mentioned mask layer of removal, to obtain trench oxide layer, the covering contact of covering groove side wall and bottom wall
The contact hole oxide layer of hole bottom hole and side wall, and the side wall of spaced trenches and contact hole is obtained after removing mask layer；
Step 6 is arranged anode metal layer above above-mentioned N-type epitaxy layer, the anode metal layer be filled in groove and
In contact hole, anode metal layer is dielectrically separated from by the side wall and bottom wall of trench oxide layer and groove in groove, anode gold
Belong to layer to be dielectrically separated from by the side wall and bottom wall of contact hole oxide layer and contact hole in contact hole hole wall, at the top of covering side wall
Anode metal layer and the anode metal layer immediately below N-type epitaxy layer Ohmic contact；
Cathode metal layer is arranged at the back side of the N-type substrate in step 7, and the cathode metal layer connects with N-type substrate ohm
Touching.
In step 1, N-type epitaxy layer is grown in N-type substrate by N-type epitaxy technique.
The material of the semiconductor substrate includes silicon, and the doping concentration of N-type substrate is greater than the doping concentration of N-type epitaxy layer.
Advantages of the present invention: groove is set in N-type epitaxy layer and contact hole, anode metal layer are filled in groove, connect
In contact hole, anode metal layer is dielectrically separated from by the side wall and bottom wall of trench oxide layer and groove, and anode metal layer is by connecing
Contact hole oxide layer is dielectrically separated from contact hole；When adding positive voltage in anode metal layer, aoxidized in contact hole oxide layer and groove
The accumulation layer of layer is formed between layer, electronics reaches bottom by N-type epitaxy layer top by the conducting channel, due to accumulation
The electron concentration of layer is higher, and mobility is bigger, thus lower forward conduction voltage drop may be implemented compared to tradition TMBS diode.
When anode metal layer is grounded, when cathode metal layer adds positive pressure, N-type epitaxy layer and the island P form space-charge region, constitute one
The potential barrier of electronics, direction of an electric field are thus to block electronics from N-type epitaxy layer to the island P and reach bottom at the top of the N-type epitaxy layer,
As cathode metal layer voltage constantly increases, depletion region is constantly extended to the N-type epitaxy layer side being lightly doped, to enable device
Bear higher pressure resistance.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention.
Fig. 2~Fig. 8 is specific implementation process step cross-sectional view of the present invention, wherein
Fig. 2 is the cross-sectional view of N-type substrate of the present invention.
Fig. 3 is the cross-sectional view that the present invention obtains N-type epitaxy layer in N-type substrate.
Fig. 4 is that the present invention obtains the cross-sectional view behind the island P.
Fig. 5 is that the present invention obtains the cross-sectional view after insulating oxide.
Fig. 6 is that the present invention obtains the cross-sectional view after side wall.
Fig. 7 is that the present invention obtains the cross-sectional view after anode metal layer.
Fig. 8 is that the present invention obtains the cross-sectional view after cathode metal layer.
Description of symbols: 1- anode metal layer, 2- side wall, the island 3-P, 4-N type epitaxial layer, 5-N type substrate, 6- cathode gold
Belong to layer, 7- contact hole oxide layer, 8- groove, 9- mask layer, 10- contact hole, 11- insulating oxide and 12- trench oxide layer.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
As illustrated in figures 1 and 8: in order to be able to achieve lower conduction voltage drop, improving reliability when high temperature, the present invention includes
Semiconductor substrate, the semiconductor substrate include the N-type epitaxy layer 4 of N-type substrate 5 and the adjacent N-type substrate 5, the N-type
Epitaxial layer 4 is located at the surface of N-type substrate 5；Groove anode construction is set on the top of the N-type epitaxy layer 4, in N-type substrate 5
Back side setting and the cathode metal layer 6 of 5 Ohmic contact of N-type substrate；
The groove anode construction includes the groove 8 being set in N-type epitaxy layer 4, the contact positioned at 8 outer ring of groove
Hole 10 and the anode metal layer 1 above N-type epitaxy layer 4 pass through groove 8, contact hole 10 on the top of N-type epitaxy layer 4
Form the side wall 2 for being used for spaced trenches 8 and contact hole 10；The island P 3 is set in N-type epitaxy layer 4, and the island P 3 is located at 8 slot of groove
The underface and the island P 3 at bottom are contacted with the slot bottom of groove 8；
The anode metal layer 1 is filled in groove 8 and contact hole 10, and anode metal layer 1 passes through the groove in groove 8
Oxide layer 12 and the side wall and bottom wall of groove 8 are dielectrically separated from, and anode metal layer 1 passes through the contact hole oxygen in 10 hole wall of contact hole
Change layer 7 and the side wall and bottom wall of contact hole 10 are dielectrically separated from, the anode metal layer 1 and anode gold at 2 top of covering side wall
Belong to 4 Ohmic contact of N-type epitaxy layer immediately below layer 1.
Specifically, semiconductor substrate can use existing common material, such as silicon, specifically can according to need and selected
It selects, details are not described herein again.N-type epitaxy layer 4 is located at the surface of N-type substrate 5, and the thickness of N-type epitaxy layer 4 is greater than N-type substrate 5
Thickness, the doping concentration of N-type epitaxy layer 4 are lower than the doping concentration of N-type substrate 5.Generally, the upper surface of N-type epitaxy layer 4 is half
The front of conductor substrate, the lower surface of N-type substrate 5 are the back side of semiconductor substrate.
Groove anode construction is set to the top of N-type epitaxy layer 4, and cathode metal layer 6 is set to the back side of N-type substrate 5, yin
Pole metal layer 6 and 5 Ohmic contact of N-type substrate cooperate the cathode that can form diode using cathode metal layer 6 and N-type substrate 5
End.Cathode metal layer 6, anode metal layer 1 can use existing common material, specifically can according to need and selected,
Details are not described herein again.
Groove 8 is located at the top of N-type epitaxy layer 4, and the notch of groove 8 is located at the upper surface of N-type epitaxy layer 4, the depth of groove 8
Degree is less than the thickness of N-type epitaxy layer 4, and contact hole 10 is located at the outer ring of groove 8, and the island P 3 is in N-type epitaxy layer 4 and the island P 3 is located at ditch
The underface of 8 slot bottom of slot, the island P 3 are contacted with the slot bottom of groove 8.Groove 8 and contact is prepared on the top of N-type epitaxy layer 4
Behind hole 10, the side wall of groove 8 forms side wall 2, and side wall 2 is a part of N-type epitaxy layer 4, using side wall 2 can by groove 8 with connect
Contact hole 10 is isolated.Anode metal layer 1 is filled in groove 8 and contact hole 10, and from section, contact hole 10 is L-shaped,
The bottom hole and side wall of the covering contact hole of contact hole oxide layer 7, the side wall and bottom wall of 12 covering groove 8 of trench oxide layer, when
It after anode metal layer 1 is filled in groove 8, can be dielectrically separated from the side wall and bottom wall of groove 8 by trench oxide layer 12, sun
Pole metal layer 1 is dielectrically separated from by contact hole oxide layer 7 and the side wall and bottom wall of contact hole 10.The depth and ditch of contact hole 10
The depth of slot 8 can be identical, and trench oxide layer 12 and contact hole oxide layer 7 are same processing step layer.
Anode metal layer 1 also covers the top of side wall 2, and anode metal layer 1 realizes sun by the Ohmic contact with side wall 2
Ohmic contact between pole metal layer 1 and N-type epitaxy layer 4.In addition, the transverse width on the island P 3 is greater than the groove width of groove 8.
When specific works, in anode metal layer 1 plus when positive voltage, contact hole oxide layer 7 and trench oxide layer 12 it
Between formed layer accumulation layer, electronics by the conducting channel by reaching bottom at the top of N-type epitaxy layer 4, due to accumulation layer
Electron concentration it is higher, mobility is bigger, thus lower forward conduction voltage drop may be implemented compared to tradition TMBS diode.When
Anode metal layer 1 is grounded, and when cathode metal layer 6 adds positive pressure, N-type epitaxy layer 4 and the island P 3 form space-charge region, constitutes one
The potential barrier of a electronics, direction of an electric field are thus to block electronics from N-type epitaxy layer 4 to the island P 3 and reach at the top of N-type epitaxy layer 4
Bottom, as 6 voltage of cathode metal layer constantly increases, depletion region is constantly extended to 4 side of N-type epitaxy layer being lightly doped, thus
Device is set to bear higher pressure resistance.
As shown in Fig. 2~Fig. 8, the groove-shaped diode of above structure can be prepared by following processing steps, tool
Body, the preparation method of the groove-shaped diode includes the following steps:
Step 1 provides semiconductor substrate, and the semiconductor substrate includes N-type substrate 5 and is located at the N-type substrate 5 just
The N-type epitaxy layer 4 of top, the adjacent N-type substrate 5 of N-type epitaxy layer 4；
Specifically, the material of semiconductor substrate includes silicon, and when initial, semiconductor substrate is only N-type substrate 5, such as Fig. 2 institute
Show, is using common growth technology means, N-type epitaxy layer 4, the doping of N-type epitaxy layer 4 can be obtained in N-type substrate 5
Concentration is less than the concentration of N-type substrate 5, and the thickness of N-type epitaxy layer 4 is generally higher than the thickness of N-type substrate 5, as shown in Figure 3.
Mask layer 9 is arranged in the N-type epitaxy layer 4, and selectively shelters and etch the mask layer 9 for step 2,
It is described to obtain required groove 8 and contact hole 10 to be performed etching using the mask layer 9 after etching to N-type epitaxy layer 4
Contact hole 10 is located at the outer ring of groove 8；
Specifically, the mask layer 9 can form the position of groove 8, contact hole 10 using materials such as photoresists as needed
It sets, mask layer 9 is performed etching, and the masking using mask layer 9 to 4 upper surface of N-type epitaxy layer, thus to N-type epitaxy layer 4
After etching, obtain groove 8 and contact hole 10, the process that specifically mask layer 9 is sheltered and etched, and using etching after
The process that mask layer 9 etches N-type epitaxy layer 4 is known to those skilled in the art, and details are not described herein again.The depth of groove 8
Degree can be identical with the depth of contact hole 10, certainly, groove 8, contact hole 10 specific depth can carry out according to actual needs
Selection, details are not described herein again.
Step 3 carries out p type impurity ion implanting above above-mentioned N-type epitaxy layer 4, obtains P with the underface in groove 8
Island 3, the island P 3 are contacted with the slot bottom of groove 8；
Specifically, p type impurity ion implanting is carried out using existing common technological means, the type of p type impurity ion with
And implantation dosage etc. can carry out selection determination according to actual needs, specially known to those skilled in the art, herein no longer
It repeats.After carrying out p type impurity ion implanting, the island P 3 is obtained in the underface of groove 8, the island P 3 is contacted with the slot bottom of groove 8, such as
Shown in Fig. 4.
Insulating oxide 11 is arranged in step 4 in above-mentioned N-type epitaxy layer 4, and the insulating oxide 11 covers contact hole 10
Bottom and side wall, groove 8 bottom wall and side wall, and oxide layer 11 is covered on mask layer 9；
Specifically, insulating oxide 11 can be silicon dioxide layer, will be exhausted using the common technological means of the art
Edge oxide layer 11 be arranged in N-type epitaxy layer 4 so that insulating oxide 11 cover contact hole 10 bottom and side wall,
The bottom wall and side wall of groove 8, and oxide layer 11 is covered on mask layer 9, as shown in Figure 5.
Step 5, the above-mentioned mask layer 9 of removal, to obtain trench oxide layer 12, the covering of 8 side wall of covering groove and bottom wall
The contact hole oxide layer 7 of 10 bottom hole of contact hole and side wall, and spaced trenches 8 and contact hole 10 are obtained after removing mask layer 9
Side wall 2；
Specifically, mask layer 9 is removed using the art common technological means, when removing mask layer 9, contact
Insulating oxide 11 between hole 10 and groove 8 removes, to obtain the side wall 2 of spaced trenches 8 Yu contact hole 10.Meanwhile it obtaining
To 8 side wall of covering groove and the trench oxide layer 12 of bottom wall, and the contact hole oxygen of covering 10 bottom hole of contact hole and side wall
Change layer 7, as shown in Figure 6.
Anode metal layer 1 is arranged in step 6 above above-mentioned N-type epitaxy layer 4, and the anode metal layer 1 is filled in groove 8
And in contact hole 10, anode metal layer 1 is insulated by the side wall and bottom wall of trench oxide layer 12 and groove 8 in groove 8
Isolation, anode metal layer 1 are insulated by the side wall and bottom wall of contact hole oxide layer 7 and contact hole 10 in 10 hole wall of contact hole
Isolation, the anode metal layer 1 and 4 Ohmic contact of N-type epitaxy layer immediately below the anode metal layer 1 at 2 top of covering side wall；
Specifically, Metal deposition is carried out using the common technological means of the art, to obtain anode metal layer 1, sun
Pole metal layer 1 is filled in groove 8 and contact hole 10, and anode metal layer 1 is covered on the top of side wall 2.Anode metal layer 1
With 2 Ohmic contact of side wall, so that the anode tap of diode can be obtained using anode metal layer 1.
Cathode metal layer 6, the cathode metal layer 6 and 5 Europe of N-type substrate is arranged at the back side of the N-type substrate 5 in step 7
Nurse contact.
Specifically, Metal deposition is carried out using the common technological means of the art, is obtained with the back side in N-type substrate 5
To cathode metal layer 6, cathode metal layer 6 and 5 Ohmic contact of N-type substrate can obtain the cathode of diode using cathode metal layer 6
End.
In addition, in the specific implementation, after obtaining N-type epitaxy layer 4, the island P 3 can be first prepared in present N-type epitaxy layer 4,
After obtaining the island P 3, required groove 8 is prepared in N-type epitaxy layer 4 according to the position on the island P 3 and is located at 8 outer ring of groove
Contact hole 10, after groove 8, contact hole 10 and the island P 3 is prepared, subsequent technique is consistent with above-mentioned technique, tool
Body can refer to above description, and details are not described herein again.As shown in the above description, the concrete technology and prior art of diode are prepared
Compatible, the diode being prepared belongs to majority carrier device, and reverse recovery time is short.
Claims (5)
1. a kind of groove-shaped diode with the island floating P, including semiconductor substrate, the semiconductor substrate include N-type substrate
(5) and the N-type epitaxy layer (4) of the adjacent N-type substrate (5), the N-type epitaxy layer (4) be located at N-type substrate (5) just on
Side；Groove anode construction is set on the top of the N-type epitaxy layer (4), setting is served as a contrast with the N-type at the back side of N-type substrate (5)
The cathode metal layer (6) of bottom (5) Ohmic contact；It is characterized in that:
The groove anode construction includes the groove (8) being set in N-type epitaxy layer (4), is located at connecing for the groove (8) outer ring
Contact hole (10) and the anode metal layer (1) being located above N-type epitaxy layer (4), pass through groove on the top of N-type epitaxy layer (4)
(8), contact hole (10) forms the side wall (2) for being used for spaced trenches (8) and contact hole (10)；P is set in N-type epitaxy layer (4)
Island (3), the island P (3) is located at the underface of groove (8) slot bottom and the island P (3) are contacted with the slot bottom of groove (8)；
The anode metal layer (1) is filled in groove (8) and contact hole (10), and anode metal layer (1) passes through in groove (8)
Trench oxide layer (12) and the side wall and bottom wall of groove (8) be dielectrically separated from, anode metal layer (1) pass through contact hole (10) hole
The side wall and bottom wall of contact hole oxide layer (7) and contact hole (10) in wall are dielectrically separated from, the anode at the top of covering side wall (2)
N-type epitaxy layer (4) Ohmic contact immediately below metal layer (1) and the anode metal layer (1).
2. the groove-shaped diode according to claim 1 with the island floating P, it is characterized in that: the transverse direction on the island P (3)
Width is greater than the groove width of groove (8).
3. a kind of preparation method of the groove-shaped diode with the island floating P, characterized in that the preparation of the groove-shaped diode
Method includes the following steps:
Step 1 provides semiconductor substrate, and the semiconductor substrate includes N-type substrate (5) and is located at the N-type substrate (5) just
The N-type epitaxy layer (4) of top, the adjacent N-type substrate (5) of N-type epitaxy layer (4)；
Step 2 is arranged mask layer (9) on the N-type epitaxy layer (4), and selectively shelters and etch the mask layer
(9), to be performed etching using the mask layer (9) after etching to N-type epitaxy layer (4), to obtain required groove (8) and contact
Hole (10), the contact hole (10) are located at the outer ring of groove (8)；
Step 3 carries out p type impurity ion implanting above above-mentioned N-type epitaxy layer (4), to obtain P immediately below groove (8)
Island (3), the island P (3) contact with the slot bottom of groove (8)；
Insulating oxide (11) are arranged on above-mentioned N-type epitaxy layer (4) in step 4, and the insulating oxide (11) covers contact hole
(10) bottom wall and side wall of bottom and side wall, groove (8), and oxide layer (11) is covered on mask layer (9)；
Step 5, the above-mentioned mask layer (9) of removal, to obtain the trench oxide layer (12) of covering groove (8) side wall and bottom wall, cover
The contact hole oxide layer (7) of lid contact hole (10) bottom hole and side wall, and spaced trenches (8) are obtained after removing mask layer (9)
With the side wall (2) of contact hole (10)；
Anode metal layer (1) is arranged above above-mentioned N-type epitaxy layer (4) in step 6, and the anode metal layer (1) is filled in groove
(8) and in contact hole (10), anode metal layer (1) passes through the trench oxide layer (12) and the side wall of groove (8) in groove (8)
And bottom wall is dielectrically separated from, anode metal layer (1) passes through the contact hole oxide layer (7) and contact hole in contact hole (10) hole wall
(10) side wall and bottom wall is dielectrically separated from, anode metal layer (1) and the anode metal layer (1) at the top of covering side wall (2)
N-type epitaxy layer (4) Ohmic contact of underface；
Cathode metal layer (6) are arranged at the back side of the N-type substrate (5) in step 7, the cathode metal layer (6) and N-type substrate
(5) Ohmic contact.
4. the preparation method of the groove-shaped diode with the island floating P according to claim 3, characterized in that in step 1, N
Type epitaxial layer (4) is grown on N-type substrate (5) by N-type epitaxy technique.
5. the preparation method of the groove-shaped diode according to claim 3 or 4 with the island floating P, characterized in that described half
The material of conductor substrate includes silicon, and the doping concentration of N-type substrate (5) is greater than the doping concentration of N-type epitaxy layer (4).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783345A (en) * | 2010-03-04 | 2010-07-21 | 无锡新洁能功率半导体有限公司 | Grooved semiconductor rectifier and manufacturing method thereof |
| CN101800252A (en) * | 2010-03-04 | 2010-08-11 | 无锡新洁能功率半导体有限公司 | Groove-shaped Schottky barrier rectifier and manufacture method thereof |
| US20120181652A1 (en) * | 2009-08-05 | 2012-07-19 | Ning Qu | Semiconductor system and method for manufacturing same |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
-
2018
- 2018-08-22 CN CN201810961259.0A patent/CN109192786A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120181652A1 (en) * | 2009-08-05 | 2012-07-19 | Ning Qu | Semiconductor system and method for manufacturing same |
| CN101783345A (en) * | 2010-03-04 | 2010-07-21 | 无锡新洁能功率半导体有限公司 | Grooved semiconductor rectifier and manufacturing method thereof |
| CN101800252A (en) * | 2010-03-04 | 2010-08-11 | 无锡新洁能功率半导体有限公司 | Groove-shaped Schottky barrier rectifier and manufacture method thereof |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
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