CN108183134A - Groove-shaped diode with floating P islands and preparation method thereof - Google Patents
Groove-shaped diode with floating P islands and preparation method thereof Download PDFInfo
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- CN108183134A CN108183134A CN201711442524.6A CN201711442524A CN108183134A CN 108183134 A CN108183134 A CN 108183134A CN 201711442524 A CN201711442524 A CN 201711442524A CN 108183134 A CN108183134 A CN 108183134A
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- 238000007667 floating Methods 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000000407 epitaxy Methods 0.000 claims abstract description 85
- 238000010276 construction Methods 0.000 claims abstract description 13
- 230000000903 blocking effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 71
- 239000002184 metal Substances 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 description 9
- 238000009825 accumulation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- -1 and when initial Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The present invention relates to a kind of groove-shaped diodes with floating P islands and preparation method thereof, it is used to form the floating P islands of space-charge region when being additionally arranged at reverse blocking in the N-type epitaxy layer, the floating P islands include the secondth area of the firstth area of p-type and p-type in N-type epitaxy layer, the firstth area of p-type is in N-type epitaxy layer in vertical distribution, the lower part in the firstth area of p-type is contacted with the secondth area of p-type, the top in the firstth area of p-type is located in support connector, the transverse width in the firstth area of p-type is less than the transverse width of support connector, the secondth area of p-type is located at the lower section of groove anode construction, and the transverse width in the secondth area of p-type is more than the transverse width of support connector.The present invention is compact-sized, can obtain the forward conduction voltage drop lower under uniform current density, improves the reliability of device at high temperature, preparation process is compatible with prior art, securely and reliably.
Description
Technical field
It is especially a kind of groove-shaped with floating P islands the present invention relates to a kind of groove-shaped diode and preparation method thereof
Diode and preparation method thereof belongs to the technical field of power semiconductor.
Background technology
Power rectifier is usually applied to control current direction in Power Electronic Circuit, according to its on state characteristic and blocking
Ability often takes corresponding device to realize rectification.During for high pressure field, the forward conduction voltage drop of traditional PIN diode
(on state current density is 100A/cm to generally greater than 0.7V2), and cut-in voltage is higher, reverse recovery time is longer.It is led in low pressure
Domain, planer schottky diode are leaked electricity larger at high temperature, and power consumption is higher, and breakdown voltage is generally in below 200V.
TMBS (Trench MOS Barrier Schottky Trench) rectifier initially in 1993 by
B.J.Baliga is put forward for the first time, although which effectively improves the reverse leakage of planer schottky diode and breakdown voltage two
The problem of aspect, but schottky junction high temperature reliability it is undesirable be still an existing problem, especially in the hot operation phase
Between.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, provide it is a kind of with floating P islands groove-shaped two
Pole pipe and preparation method thereof, it is compact-sized, the forward conduction voltage drop lower under uniform current density can be obtained, device is improved and exists
Reliability under high temperature, preparation process is compatible with prior art, securely and reliably.
According to technical solution provided by the invention, the groove-shaped diode with floating P islands, including semiconductor-based
Plate, the semiconductor substrate include the N-type epitaxy layer of N-type substrate and the adjacent N-type substrate, and the N-type epitaxy layer is located at N
The surface of type substrate；Groove anode construction is set on the top of the N-type epitaxy layer, and the groove anode construction includes setting
Groove in N-type epitaxy layer top, the support connector that N-type epitaxy layer top is formed in by groove and connect with the support
The anode metal layer of junctor Ohmic contact；Setting and the cathodic metal of the N-type substrate Ohmic contact at the back side of N-type substrate
Layer；
The floating P islands of space-charge region are used to form when being additionally arranged at reverse blocking in the N-type epitaxy layer, it is described floating
Empty P islands include the secondth area of the firstth area of p-type and p-type in N-type epitaxy layer, and the firstth area of p-type is in N-type epitaxy layer in vertical point
Cloth, the lower part in the firstth area of p-type are contacted with the secondth area of p-type, and the top in the firstth area of p-type is located in support connector, the firstth area of p-type
Transverse width is less than the transverse width of support connector, and the secondth area of p-type is located at the lower section of groove anode construction, and the secondth area of p-type
Transverse width be more than support connector transverse width.
On the cross section of groove-shaped diode, oxide layer is set in the trench, the oxide layer is covered in the side of groove
Wall and bottom wall, oxide layer are symmetrically distributed in the both sides of support connector；Anode metal layer also fills up in the trench, anode metal
Layer is dielectrically separated from by the side wall and bottom wall of oxide layer and groove.
A kind of preparation method of the groove-shaped diode with floating P islands, the preparation method include the following steps：
Step 1, provide semiconductor substrate, the semiconductor substrate include N-type substrate and positioned at the N-type substrate just on
The N-type extension base of side, N-type extension base abut the N-type substrate；
Step 2, the injection that p type impurity ion is carried out above above-mentioned N-type extension base, to be obtained in N-type extension base
To the secondth area of p-type；
Step 3, the injection for carrying out p type impurity ion again in above-mentioned N-type extension base, in N-type extension base
The firstth area of p-type is obtained, the lower part in firstth area of p-type is contacted with the secondth area of p-type, horizontal stroke of the firstth area of p-type in N-type extension base
It is less than transverse width of the secondth area of p-type in N-type extension base to width；
Step 4 carries out N-type epitaxial growth in above-mentioned N-type extension base, to obtain being located at the N-type right over N-type substrate
Epitaxial layer, the firstth area of p-type, the secondth area of p-type are respectively positioned in N-type epitaxy layer；
Step 5 sets mask layer on the surface of above-mentioned N-type epitaxy layer, selectively shelters and etch the mask layer, with
Photoetching is carried out to N-type epitaxy layer using the mask layer after etching, to obtain required groove, groove is from the upper table of N-type epitaxy layer
Face extends vertically downward, and N-type epitaxy layer top forms support connector by groove；
Step 6 carries out growth of gate oxide layer on above-mentioned N-type epitaxy layer upper surface, to obtain the oxygen of covering N-type epitaxy layer
Change layer body；
Step 7 carries out photoetching to above-mentioned oxide layer body, with the mask layer and oxide layer on removal support connector
Body obtains the oxide layer of covering groove side wall and bottom wall；
Step 8 sets anode metal layer in above-mentioned N-type epitaxy layer, and the anode metal layer is covered in support connector
And in oxide layer, anode metal layer and support connector Ohmic contact；
Step 9 sets cathode metal layer, the cathode metal layer and N-type substrate Ohmic contact at the back side of N-type substrate.
In step 1, N-type extension base is grown in by N-type epitaxy technique in N-type substrate.
The material of the semiconductor substrate includes silicon, and the doping concentration of N-type substrate is more than the doping concentration of N-type epitaxy layer.
Advantages of the present invention：Floating P islands are formed in N-type epitaxy layer, groove anode construction is set in N-type epitaxy layer,
Anode metal layer-oxide layer of anode channels structure-N-type epitaxy layer forms MOS structure, and floating P islands form PN with N-type epitaxy layer
Knot by electron accumulation layer conduction when forward direction is opened, can realize lower forward voltage drop under same current density；Pass through PN junction
Pressure resistance, the better reliability of device at high temperature is compact-sized, compatible with prior art, securely and reliably.
Description of the drawings
Fig. 1 is the structural diagram of the present invention.
Fig. 2~Figure 10 is specific implementation process step sectional view of the present invention, wherein,
Fig. 2 is the sectional view of N-type substrate of the present invention.
Fig. 3 obtains the sectional view of N-type extension base for the present invention.
Fig. 4 obtains the sectional view behind the secondth area of p-type for the present invention.
Fig. 5 obtains the sectional view behind the firstth area of p-type for the present invention.
Fig. 6 obtains the sectional view after N-type epitaxy layer for the present invention.
Fig. 7 obtains the sectional view after groove for the present invention.
Fig. 8 obtains the sectional view after oxide layer body for the present invention.
Fig. 9 obtains the sectional view after oxide layer for the present invention.
Figure 10 obtains the sectional view after cathode metal layer for the present invention.
Reference sign：1- anode metal layers, 2- oxide layers, the firstth area of 3-P types, 4-N types epitaxial layer, 5-N types substrate,
6- cathode metal layers, the secondth area of 7-P types, 8- mask layers, 9- grooves, 10- oxide layers body, 11- support connectors and 12-N types
Extension base.
Specific embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Fig. 1 and Figure 10：In order to obtain forward conduction voltage drop lower under same uniform current density, improve device and exist
Reliability under high temperature, the present invention include semiconductor substrate, and the semiconductor substrate includes N-type substrate 5 and the adjacent N-type
The N-type epitaxy layer 4 of substrate 5, the N-type epitaxy layer 4 are located at the surface of N-type substrate 5；It is set on the top of the N-type epitaxy layer 4
Groove anode construction is put, the groove anode construction includes being set to the groove 9 on 4 top of N-type epitaxy layer, be formed by groove 9
In 4 top of N-type epitaxy layer support connector 11 and with it is described support 11 Ohmic contact of connector anode metal layer 1；In N
The back side setting of type substrate 5 and the cathode metal layer 6 of 5 Ohmic contact of N-type substrate；
The floating P islands of space-charge region are used to form when being additionally arranged at reverse blocking in the N-type epitaxy layer 4, it is described
Floating P islands include the firstth area of p-type 3 and the secondth area of p-type 7 in N-type epitaxy layer 4, and the firstth area of p-type 3 is in N-type epitaxy layer 4
In vertical distribution, the lower part in the firstth area of p-type 3 is contacted with the secondth area of p-type 7, and the top in the firstth area of p-type 3 is located at support connector 11
Interior, the transverse width in the firstth area of p-type 3 is less than the transverse width of support connector 11, and the secondth area of p-type 7 is located at groove anode construction
Lower section, and the transverse width in the secondth area of p-type 7 be more than support connector 11 transverse width.
Specifically, existing common material, such as silicon may be used in semiconductor substrate, can specifically be selected as needed
It selects, details are not described herein again.N-type epitaxy layer 4 is located at the surface of N-type substrate 5, and the thickness of N-type epitaxy layer 4 is more than N-type substrate 5
Thickness, the doping concentration of N-type epitaxy layer 4 are less than the doping concentration of N-type substrate 5.Usually, the upper surface of N-type epitaxy layer 4 is half
The front of conductor substrate, the lower surface of N-type substrate 5 are the back side of semiconductor substrate.
Groove anode construction is set to the top of N-type epitaxy layer 4, wherein, groove 9 is vertical from the upper surface of N-type epitaxy layer 4
It extending downwardly, the depth of groove 9 is less than the thickness of N-type epitaxy layer 4, after etching obtains groove 9, remaining remaining formation support
Connector 11, the outer diameter of support connector 11 are less than the width of N-type epitaxy layer 4, and when groove 9 is square or is annular, support connects
Junctor 11 is located in groove 9.Anode metal layer 1 is covered in the top of support connector 11, with supporting 11 Ohmic contact of connector
Afterwards, the anode tap of diode can be formed.Cathode metal layer 6 is covered in the lower surface of N-type substrate 5, and cathode metal layer 6 is served as a contrast with N-type
After 5 Ohmic contact of bottom, the cathode terminal of diode can be formed, i.e., it can be with external electricity by anode metal layer 1, cathode metal layer 6
Pressure connection, so that diode is on or off state.
In the embodiment of the present invention, floating P islands are located in N-type epitaxy layer 4, and the firstth area of p-type 3 is in vertical distribution, the firstth area of p-type
The direction that 3 length direction is directed toward N-type epitaxy layer 4 with N-type substrate 5 is consistent.The firstth area of p-type 3 is in support connector 11
Length is less than the height of support connector 11, and usually, the firstth area of p-type 3 is in coaxial distribution with support connector 11.P-type second
Area 7 is located at the lower section in the firstth area of p-type 3, and the secondth area of p-type 7 is located at the lower section of support connector 11, and the transverse direction in the secondth area of p-type 7 is long
Degree is more than the lateral length of support connector 11.
In addition, on the cross section of groove-shaped diode, setting oxide layer 2, the oxide layer 2 are covered in groove 9
The side wall and bottom wall of groove 9, oxide layer 2 are symmetrically distributed in the both sides of support connector 11；Anode metal layer 1 is also filled up in ditch
In slot 9, anode metal layer 1 is dielectrically separated from by oxide layer 2 and the side wall and bottom wall of groove 9.
In the embodiment of the present invention, oxide layer 2 can be silicon dioxide layer, and oxide layer 2 is covered in inner wall and the bottom of groove 9
On wall, anode metal layer 1 is also filled up in groove 9, and anode metal layer 1 can form MOS by oxide layer 2 and N-type epitaxy layer 4 and tie
Structure can form PN junction between floating P islands and N-type epitaxy layer 4.
When specifically used, when anode metal layer 1 plus positive voltage, formed in oxide layer 2 and the engaging portion of N-type epitaxy layer 4
The accumulation layer of layer, electronics by 4 top of N-type epitaxy layer by the conducting channel that the accumulation layer is formed by reaching bottom (N
The surface far from N-type substrate 5 is specifically referred at the top of type epitaxial layer, the bottom of N-type epitaxy layer 4 refers to what is abutted with N-type substrate 5
Surface), due to the electron concentration higher of accumulation layer, mobility bigger, thus can realize compared to tradition TMBS diodes lower
Forward conduction voltage drop.When anode metal layer 1 is grounded, and cathode metal layer 6 adds positive pressure, N-type epitaxy layer 4 and floating P islands are formed
Space-charge region, constitutes the potential barrier of an electronics, thus blocks electronics and reach bottom from 4 top of N-type epitaxy layer, with
6 voltage of cathode metal layer constantly increases, and depletion region is constantly extended to 4 side of N-type epitaxy layer being lightly doped, so as to which device be enable to hold
By higher pressure resistance.So as to, forward direction open when by electron accumulation layer conduction, can be realized under same current density it is lower just
To pressure drop；Pass through PN junction pressure resistance, the better reliability of device at high temperature.The groove-shaped diode of the present invention belongs to most current-carrying
Sub- device, reverse recovery time are short.
As shown in Fig. 2~Figure 10, the groove-shaped diode of above structure may be used following processing steps and be prepared, tool
Body, the preparation method includes the following steps：
Step 1, provide semiconductor substrate, the semiconductor substrate include N-type substrate 5 and positioned at the N-type substrate 5 just
The N-type extension base 12 of top, N-type extension base 12 abut the N-type substrate 5；
Specifically, the material of semiconductor substrate includes silicon, and when initial, semiconductor substrate is only N-type substrate 5, such as Fig. 2 institutes
Show, using common growth technology means, N-type extension base 12, N-type extension base 12 can be obtained in N-type substrate 5
Doping concentration be less than the concentration of N-type substrate 5, the thickness of N-type extension base 12 is generally higher than the thickness of N-type substrate 5, such as Fig. 3
It is shown.
Step 2, the injection that p type impurity ion is carried out above above-mentioned N-type extension base 12, in N-type extension base 12
Inside obtain the secondth area of p-type 7；
Specifically, p type impurity ion can be B ions, and ion can be realized using the common technological means of the art
Injection, the secondth area of p-type 7 is located in N-type extension base 12, as shown in figure 4, the specific technique mistake that the secondth area of p-type 7 is prepared
Journey is known to those skilled in the art, and details are not described herein again.
Step 3, the injection for carrying out p type impurity ion again in above-mentioned N-type extension base 12, in N-type extension base
The firstth area of p-type 3 is obtained in 12, the lower part in firstth area of p-type 3 is contacted with the secondth area of p-type 7, and the firstth area of p-type 3 is in N-type epitaxial base
Transverse width in floor 12 is less than transverse width of the secondth area of p-type 7 in N-type extension base 12；
In the embodiment of the present invention, P is carried out after the secondth area of p-type 7 is obtained, then using the common technological means of the art
Type foreign ion injection, to obtain the firstth area of p-type 3, the firstth area of p-type 3 prolongs vertically downward from the upper surface of N-type extension base 12
It stretches, the lower part in the firstth area of p-type 3 is contacted with the secondth area of p-type 7, and the longitudinal direction height in the firstth area of p-type 3 is more than the longitudinal direction in the secondth area of p-type 7
Highly, as shown in Figure 5.
Step 4 carries out N-type epitaxial growth in above-mentioned N-type extension base 12, to obtain being located at right over N-type substrate 5
N-type epitaxy layer 4, the firstth area of p-type 3, the secondth area of p-type 7 are respectively positioned in N-type epitaxy layer 4；
Specifically, epitaxial growth is realized using the common epitaxial growth means of the art, to obtain N-type epitaxy layer 4,
I.e. the thickness of N-type epitaxy layer 4 is more than the thickness of N-type extension base 12, as shown in Figure 6.
Step 5 sets mask layer 8 on the surface of above-mentioned N-type epitaxy layer 4, selectively shelters and etch the mask layer
8, to carry out photoetching to N-type epitaxy layer 4 using the mask layer 8 after etching, to obtain required groove 9, groove 9 is from N-type extension
The upper surface of layer 4 extends vertically downward, and 4 top of N-type epitaxy layer forms support connector 11 by groove 9；
In the embodiment of the present invention, mask layer 8 can be silicon dioxide layer, real using the common technological means of the art
The now masking to mask layer 8 and etching, can be in N-type by groove 9 so as to obtaining required groove 9 after 4 photoetching of epitaxial layer
Be supported connector 11 on epitaxial layer 4, as shown in Figure 7.
Step 6 carries out growth of gate oxide layer on above-mentioned 4 upper surface of N-type epitaxy layer, to obtain covering N-type epitaxy layer 4
Oxide layer body 10；
Specifically, oxide layer body 10 is obtained using the common technological means of the art, such as using thermal oxide growth
Mode, oxide layer body 10 are covered on the side wall and bottom wall of the above-mentioned mask layer 8 not etched and groove 9, as shown in Figure 8.
Step 7 carries out photoetching to above-mentioned oxide layer body 10, with the mask layer 8 and oxygen on removal support connector 11
Change layer body 10, obtain the oxide layer 2 of 9 side wall of covering groove and bottom wall；
Specifically, after photoetching is carried out to oxide layer body 10, the mask layer 8 on support connector 11 and oxidation can be removed
Layer 10, obtains the oxide layer 2 of 9 side wall of covering groove and bottom wall, as shown in Figure 9.
Step 8 sets anode metal layer 1 in above-mentioned N-type epitaxy layer 4, and the anode metal layer 1 is covered in support connection
On body 11 and oxide layer 2, anode metal layer 1 and support 11 Ohmic contact of connector；
In the embodiment of the present invention, anode metal layer 1 is set to using modes such as deposits in N-type epitaxy layer 4, anode metal layer
1 may be used the common material of the art, and anode metal layer 1 is covered with support 11 Ohmic contact of connector, anode metal layer 1
It covers in oxide layer 2, so as to which the structure of MOS can be formed using anode metal layer 1- oxide layer 2-N types epitaxial layer 4.
Step 9 sets cathode metal layer 6 at the back side of N-type substrate 5, and the cathode metal layer 6 connects for 5 ohm with N-type substrate
It touches.
In the embodiment of the present invention, cathode metal layer 6 is arranged on by N-type substrate using the common technological means of the art
On 5, cathode metal layer 6 and 5 Ohmic contact of N-type substrate, as shown in Figure 10.It is normal that the art may be used in cathode metal layer 6
Material can specifically be selected as needed, and details are not described herein again.
In addition, in the specific implementation, N-type epitaxy layer 4 can also first be prepared, groove is first carried out in N-type epitaxy layer 4
After groove 9 is obtained, the firstth area of p-type 3 and the secondth area of p-type 7 or other sequences are being formed by ion implanting mode for etching
Mode obtains required structure type, can specifically be adjusted, no longer repeat one by one herein as needed.
The present invention forms floating P islands in N-type epitaxy layer 4, and groove anode construction is set in N-type epitaxy layer 4, anode ditch
The anode metal layer 1- oxide layer 2-N types epitaxial layer 4 of slot structure forms MOS structure, and floating P islands form PN with N-type epitaxy layer 4
Knot by electron accumulation layer conduction when forward direction is opened, can realize lower forward voltage drop under same current density；Pass through PN junction
Pressure resistance, the better reliability of device at high temperature is compact-sized, compatible with prior art, securely and reliably.
Claims (5)
1. a kind of groove-shaped diode with floating P islands, including semiconductor substrate, the semiconductor substrate includes N-type substrate
(5) and the N-type epitaxy layer (4) of the adjacent N-type substrate (5), the N-type epitaxy layer (4) positioned at N-type substrate (5) just on
Side；Groove anode construction is set on the top of the N-type epitaxy layer (4), and the groove anode construction includes being set to N-type extension
The groove (9) on layer (4) top, the support connector (11) for being formed in by groove (9) N-type epitaxy layer (4) top and with institute
State the anode metal layer (1) of support connector (11) Ohmic contact；Setting and the N-type substrate at the back side of N-type substrate (5)
(5) cathode metal layer (6) of Ohmic contact；It is characterized in that：
The floating P islands of space-charge region are used to form when being additionally arranged at reverse blocking in the N-type epitaxy layer (4), it is described floating
Empty P islands are included in the firstth area of p-type (3) and the secondth area of p-type (7) in N-type epitaxy layer (4), and the firstth area of p-type (3) is in N-type extension
It is contacted in layer (4) in vertical distribution, the lower part in the firstth area of p-type (3) with the secondth area of p-type (7), the top in the firstth area of p-type (3) is located at
It supports in connector (11), the transverse width in the firstth area of p-type (3) is less than the transverse width of support connector (11), the secondth area of p-type
(7) positioned at the lower section of groove anode construction, and the transverse width in the secondth area of p-type (7) is more than the laterally wide of support connector (11)
Degree.
2. the groove-shaped diode according to claim 1 with floating P islands, it is characterized in that：In groove-shaped diode
On cross section, setting oxide layer (2), the oxide layer (2) are covered in the side wall and bottom wall of groove (9), oxygen in groove (9)
Change the both sides that layer (2) is symmetrically distributed in support connector (11)；Anode metal layer (1) is also filled up in groove (9), anode metal
Layer (1) is dielectrically separated from by oxide layer (2) and the side wall and bottom wall of groove (9).
3. a kind of preparation method of the groove-shaped diode with floating P islands, it is characterized in that, the preparation method includes following step
Suddenly：
Step 1, provide semiconductor substrate, the semiconductor substrate include N-type substrate (5) and positioned at the N-type substrate (5) just
The N-type extension base (12) of top, the adjacent N-type substrate (5) of N-type extension base (12)；
Step 2, the injection that p type impurity ion is carried out above above-mentioned N-type extension base (12), in N-type extension base (12)
Inside obtain the secondth area of p-type (7)；
Step 3, the injection for carrying out p type impurity ion again on above-mentioned N-type extension base (12), in N-type extension base
(12) the firstth area of p-type (3) is obtained in, the lower part of firstth area of p-type (3) is contacted with the secondth area of p-type (7), the firstth area of p-type (3)
Transverse width in N-type extension base (12) is less than transverse width of the secondth area of p-type (7) in N-type extension base (12)；
Step 4 carries out N-type epitaxial growth on above-mentioned N-type extension base (12), to obtain being located at right over N-type substrate (5)
N-type epitaxy layer (4), the firstth area of p-type (3), the secondth area of p-type (7) are respectively positioned in N-type epitaxy layer (4)；
Step 5 sets mask layer (8) on the surface of above-mentioned N-type epitaxy layer (4), selectively shelters and etch the mask layer
(8), to carry out photoetching to N-type epitaxy layer (4) using the mask layer (8) after etching, to obtain required groove (9), groove (9)
Extend vertically downward from the upper surface of N-type epitaxy layer (4), N-type epitaxy layer (4) top forms support connector by groove (9)
(11)；
Step 6 carries out growth of gate oxide layer on above-mentioned N-type epitaxy layer (4) upper surface, to obtain covering N-type epitaxy layer (4)
Oxide layer body (10)；
Step 7 carries out photoetching to above-mentioned oxide layer body (10), with the mask layer (8) on removal support connector (11) and
Oxide layer body (10) obtains the oxide layer (2) of covering groove (9) side wall and bottom wall；
Step 8 sets anode metal layer (1) in above-mentioned N-type epitaxy layer (4), and the anode metal layer (1) is covered in support and connects
On junctor (11) and oxide layer (2), anode metal layer (1) and support connector (11) Ohmic contact；
Step 9 sets cathode metal layer (6), the cathode metal layer (6) and N-type substrate (5) Europe at the back side of N-type substrate (5)
Nurse contacts.
4. the preparation method of the groove-shaped diode with floating P islands according to claim 3, it is characterized in that, in step 1, N
Type extension base (12) is grown in by N-type epitaxy technique in N-type substrate (5).
5. the preparation method of the groove-shaped diode with floating P islands according to claim 3 or 4, it is characterized in that, described half
The material of conductor substrate includes silicon, and the doping concentration of N-type substrate (5) is more than the doping concentration of N-type epitaxy layer (4).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116454138A (en) * | 2023-06-15 | 2023-07-18 | 西安电子科技大学 | Silicon carbide floating junction diode with columnar P channel and preparation method |
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| CN104393055A (en) * | 2014-11-10 | 2015-03-04 | 电子科技大学 | Grooved diode with floating island structure |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| KR20170075289A (en) * | 2015-12-23 | 2017-07-03 | 서강대학교산학협력단 | Trench MOS Barrier Schottky(TMBS) with using trench filling |
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| CN104393055A (en) * | 2014-11-10 | 2015-03-04 | 电子科技大学 | Grooved diode with floating island structure |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
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