CN116072710A - Double-groove type SiC MOSFET cell structure, device and preparation method - Google Patents
Double-groove type SiC MOSFET cell structure, device and preparation method Download PDFInfo
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Abstract
The invention relates to a double-groove SiC MOSFET cell structure, a device and a preparation method, belonging to the technical field of semiconductor devices, wherein the cell structure comprises: the semiconductor device comprises an N+ type SiC substrate, a first N-type SiC drift layer, a plurality of floating P+ type shielding rings arranged in the first N-type SiC drift layer, a second N-type SiC drift layer, source P+ type shielding layers arranged at two side positions in the second N-type SiC drift layer, a gate trench, a gate dielectric layer, a gate electrode, a plurality of gate P+ type shielding rings arranged in the second N-type SiC drift layer, a P-type base region, an N+ type source region, a source trench, a source ohmic contact electrode, an interlayer dielectric layer, a source metal layer and a drain ohmic contact electrode. The double-groove type SiC MOSFET cell structure, the device and the preparation method provided by the invention can ensure that the double-groove type SiC MOSFET can be used in an electric power electronic system without being connected in anti-parallel with an external diode, thereby reducing the chip area and the packaging cost.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a double-groove type SiC MOSFET cell structure, a device and a preparation method.
Background
SiC is used as a third generation semiconductor material, the forbidden bandwidth is 3 times of that of the first generation semiconductor material, the critical breakdown electric field strength is 10 times of that of Si, the electron saturation drift rate is 2 times of that of Si, and the thermal conductivity is 3 times of that of Si, so that the SiC power semiconductor device, particularly the SiC MOSFET, has the remarkable performance advantages of high temperature, high voltage, high frequency, high efficiency and the like, and has wide application prospect in a power electronic system.
In power electronics systems, it is often necessary to use external diodes in anti-parallel with the SiC MOSFETs, which play a role in freewheeling when the SiC MOSFETs are turned off, but this increases chip area and packaging costs.
Disclosure of Invention
The invention aims to provide a double-groove type SiC MOSFET cell structure, a device and a preparation method, so as to solve the defects in the prior art.
The invention provides a double-groove type SiC MOSFET cell structure, which comprises the following components:
an n+ type SiC substrate;
a first N-type SiC drift layer disposed over the N+ type SiC substrate;
a plurality of floating p+ -type shield rings disposed in the first N-type SiC drift layer;
a second N-type SiC drift layer disposed over the first N-type SiC drift layer;
source P+ type shielding layers arranged at two side positions in the second N-type SiC drift layer;
a gate trench disposed at an intermediate position in the second N-type SiC drift layer;
the gate dielectric layer is arranged at the bottom and on the inner side wall of the gate groove;
the gate electrode is arranged on the gate dielectric layer;
a plurality of gate p+ -type shield rings disposed in the second N-type SiC drift layer, the intermediate positions of the gate trenches partially covering the plurality of gate p+ -type shield rings;
the P-type base region is arranged between the source electrode P+ type shielding layer and the grid electrode P+ type shielding ring;
the N+ type source region is arranged above the source P+ type shielding layer and the P type base region;
and the source electrode groove, the source electrode ohmic contact electrode, the interlayer dielectric layer, the source electrode metal layer and the drain electrode ohmic contact electrode.
In the above scheme, the width of each shielding ring included in the grid p+ type shielding ring gradually decreases from the middle to the two sides, and the sum of the total width of the grid p+ type shielding ring and the total width of the floating p+ type shielding ring is equal to the width of the grid trench.
In the above scheme, the number of the shielding rings included in the floating p+ type shielding ring is an even number, the number of the shielding rings included in the grid p+ type shielding ring is an odd number, and the number of the shielding rings included in the floating p+ type shielding ring is one more than the number of the shielding rings included in the grid p+ type shielding ring.
In the above scheme, the width of the single shielding ring included in the floating p+ type shielding ring and the width of the single shielding ring included in the grid p+ type shielding ring are both not smaller than 0.1 μm.
In the above scheme, the doping concentration of the second N-type SiC drift layer is greater than the doping concentration of the first N-type SiC drift layer.
In the above scheme, the doping concentrations of the source p+ type shielding layer and the gate p+ type shielding ring are the same, and the doping concentrations of the source p+ type shielding layer and the gate p+ type shielding ring are greater than the doping concentration of the second N-type SiC drift layer.
In the above-mentioned scheme, the source trench is disposed at a left side position of the n+ type source region located at the left side, the source p+ type shielding layer located under the n+ type source region located at the left side, and a right side position of the source p+ type shielding layer located under the n+ type source region located at the right side; the source ohmic contact electrode is arranged at the bottom and the side wall of the source groove and in a partial area above the N+ type source area; the interlayer dielectric layer is arranged above the grid electrode, above the exposed N+ type source region and above the source ohmic contact electrode above the N+ type source region; the source electrode metal layer is arranged on the exposed source electrode ohmic contact electrode and above the interlayer dielectric layer; the drain ohmic contact electrode is arranged on the back surface of the N+ type SiC substrate.
The double-groove type SiC MOSFET device provided by the invention comprises the double-groove type SiC MOSFET cell structure.
The preparation method of the double-groove type SiC MOSFET cell structure provided by the invention comprises the following steps:
providing an N+ type SiC substrate, and forming a first N-type SiC drift layer on the N+ type SiC substrate;
preparing a plurality of floating P+ type shielding rings with set widths and intervals in the first N-type SiC drift layer;
forming a second N-type SiC drift layer with higher doping concentration than the first N-type SiC drift layer on the first N-type SiC drift layer, and forming a source P+ type shielding layer and a plurality of grid P+ type shielding rings with the widths of the shielding rings gradually decreasing from the middle to the two sides in the second N-type SiC drift layer;
forming a P-type base region between the source P+ type shielding layer and the grid P+ type shielding ring;
forming an N+ type source region on the second N-type SiC drift layer;
and forming a gate electrode, a source ohmic contact electrode, an interlayer dielectric layer, a source metal layer and a drain ohmic contact electrode respectively.
In the above-described aspect, forming the gate electrode, the source ohmic contact electrode, the interlayer dielectric layer, the source metal layer, and the drain ohmic contact electrode, respectively, includes:
etching the N+ type source region and the source P+ type shielding layer below the N+ type source region to form a source groove penetrating into the source P+ type shielding layer, and etching the P type base region below the N+ type source region, the second N-type SiC drift layer and the grid P+ type shielding ring in the second N-type SiC drift layer to form a grid groove penetrating into the region where the grid P+ type shielding ring is located;
forming a gate dielectric layer on the bottom and the inner side wall of the gate trench, and forming a gate electrode on the gate dielectric layer through a polysilicon deposition process;
forming a source ohmic contact electrode at the bottom and the side wall of the source groove and a partial area above the N+ type source area, and forming a drain ohmic contact electrode at the back of the N+ type SiC substrate;
forming an interlayer dielectric layer above the gate electrode, above the exposed N+ type source region and above the source ohmic contact electrode above the N+ type source region;
a source metal layer is formed on the exposed source ohmic contact electrode and over the interlayer dielectric layer.
The embodiment of the invention has the following advantages:
according to the double-groove type SiC MOSFET cell structure, the device and the preparation method provided by the embodiment of the invention, the floating P+ type shielding ring is used to be equivalent to adding the back hole injection control structure, holes are injected in the later reverse recovery stage of the body diode, and the rapid extraction of excessive carriers is restrained, so that the turn-off softness and dynamic robustness of the body diode are improved, and the floating P+ type shielding ring is used to enable the double-groove type SiC MOSFET to be used in an anti-parallel mode with an external diode in a power electronic system, so that the chip area and the packaging cost are reduced.
Drawings
Fig. 1 is a block diagram of a dual trench SiC MOSFET cell structure according to the present invention.
Fig. 2 is a step diagram of a method for fabricating a dual trench SiC MOSFET cell structure according to the present invention.
Fig. 3 is a schematic process diagram of forming a first N-type SiC drift layer on an n+ type SiC substrate according to the present invention.
Fig. 4 is a schematic process diagram of the invention for preparing a floating p+ shield ring.
Fig. 5 is a schematic process diagram of growing a second N-type SiC drift layer.
Fig. 6 is a schematic process diagram of preparing a source p+ type shield layer and a gate p+ type shield ring.
Fig. 7 is a schematic diagram of a process for forming a P-type base region according to the present invention.
Fig. 8 is a schematic diagram of a process for forming an n+ type source region according to the present invention.
Fig. 9 is a schematic diagram of a process of forming a source trench and a gate trench in accordance with the present invention.
Fig. 10 is a schematic diagram of a process for forming a gate dielectric layer and a gate electrode according to the present invention.
Fig. 11 is a schematic view of a process of forming a source ohmic contact electrode and a drain ohmic contact electrode according to the present invention.
Fig. 12 is a schematic view of a process for forming an interlayer dielectric layer according to the present invention.
Fig. 13 is a schematic view of a process for forming a source metal layer according to the present invention.
Fig. 14 is an electric field profile of the present invention.
Fig. 15 is a plot of drain voltage versus drain current density for the present invention.
Fig. 16 is a time-drain current density plot of the present invention.
Fig. 17 is an enlarged view of a portion of the time-drain current density curve of the present invention.
Reference numerals: the semiconductor device comprises an N+ type SiC substrate 1, a first N-type SiC drift layer 2, a floating P+ type shielding ring 3, a second N-type SiC drift layer 4, a source P+ type shielding layer 5, a grid P+ type shielding ring 6, a P type base region 7, an N+ type source region 8, a grid dielectric layer 9, a grid electrode 10, a source ohmic contact electrode 11, an interlayer dielectric layer 12, a source metal layer 13 and a drain ohmic contact electrode 14.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
As shown in fig. 1, the present invention provides a dual trench SiC MOSFET cell structure, comprising:
an n+ type SiC substrate 1;
a first N-type SiC drift layer 2 disposed above the n+ -type SiC substrate 1;
the floating P+ type shielding rings 3 are arranged in the first N-type SiC drift layer 2, wherein the floating P+ type shielding rings 3 are formed in the first N-type SiC drift layer 2, the effective shielding area for drain voltage is increased, the width and the interval of the floating P+ type shielding rings 3 can be set according to actual needs, when forward conduction can be ensured, current can flow between the shielding rings, the influence on-resistance is reduced, meanwhile, the first N-type SiC drift layer 2 between the shielding rings under high voltage is exhausted, the protection on a grid groove is not influenced, in addition, for a parasitic body diode of the SiC MOSFET, the floating P+ type shielding rings 3 are equivalent to the addition of a back hole injection control structure, holes are injected in the later stage of reverse recovery of the body diode, the rapid extraction of surplus carriers is restrained, the turn-off softness and the dynamic robustness of the body diode are improved, the floating P+ type shielding rings are optimized, the SiC MOSFET can be used in an anti-parallel connection with an external diode in a power electronic system, the chip and the packaging area is reduced;
a second N-type SiC drift layer 4 disposed above the first N-type SiC drift layer 2, wherein a doping concentration of the second N-type SiC drift layer 4 is greater than a doping concentration of the first N-type SiC drift layer 2, specifically, a doping concentration of the second N-type SiC drift layer 4 is at least 5 times that of the first N-type SiC drift layer 2, so that the combination thereof can reduce a conduction loss;
source p+ -type shield layers 5 provided at both side positions in the second N-type SiC drift layer 4;
a gate trench disposed at an intermediate position in the second N-type SiC drift layer 4, wherein, in a specific implementation process, a depth of the gate trench is 1-2 micrometers;
a gate dielectric layer 9 disposed on the bottom and inner sidewalls of the gate trench;
a gate electrode 10 disposed on the gate dielectric layer 9;
the grid P+ type shielding rings 6 are arranged in the second N-type SiC drift layer 4, the middle positions of the grid grooves partially cover the grid P+ type shielding rings 6, the grid P+ type shielding rings 6 and the floating P+ type shielding rings 3 are not overlapped, in the vertical direction, the grid P+ type shielding rings 6 and the floating P+ type shielding rings 3 are complementary, the floating P+ type shielding rings 3 are vertically and upwardly translated to be right below the grid grooves, gaps between the grid P+ type shielding rings 6 can be filled, enough flow paths for conduction current are ensured, the widths of the shielding rings included by the grid P+ type shielding rings 6 are gradually reduced from the middle to the two sides, the sum of the total widths of the grid P+ type shielding rings 6 and the total width of the floating P+ type shielding rings 3 is equal to the width of the grid grooves, the protection effect on the grid grooves is enhanced, the peak value and the drain capacitance of an electric field of a grid dielectric layer 9 are reduced, the electric field concentration effect existing at the bottom of the grid grooves is reduced, the reliability of the grid grooves is improved, the service life of a MOSFET is prolonged, and the service life of a switching medium device is prolonged; meanwhile, in the implementation process, the number of shielding rings included in the floating p+ type shielding ring 3 is even, the number of shielding rings included in the grid p+ type shielding ring 6 is odd, and the number of shielding rings included in the floating p+ type shielding ring 3 is one more than the number of shielding rings included in the grid p+ type shielding ring 6; in addition, in the implementation process, the width of the single shielding ring included in the floating p+ type shielding ring 3 and the width of the single shielding ring included in the grid p+ type shielding ring 6 are not smaller than 0.1 μm, which can avoid that different rings of the floating p+ type shielding ring 3 and different rings of the grid p+ type shielding ring 6 are connected due to the lateral diffusion effect in ion implantation;
the P-type base region 7 is arranged between the source P+ type shielding layer 5 and the grid P+ type shielding ring 6;
the N+ type source region 8 is arranged above the source P+ type shielding layer 5 and the P type base region 7, wherein in the implementation process, the sum of the depths of the N+ type source region 8 and the P type base region 7 is not greater than the depth of the gate trench;
a source trench, disposed at a left side position of the n+ type source region 8 on the left side, the source p+ type shielding layer 5 under the n+ type source region 8 on the left side, and disposed at a right side position of the n+ type source region 8 on the right side, the source p+ type shielding layer 5 under the n+ type source region 8 on the right side, wherein in a specific implementation process, a depth of the source trench and a depth of the gate trench are the same, and are 1-2 micrometers;
a source ohmic contact electrode 11 disposed at the bottom and side walls of the source trench and in a partial region above the n+ type source region 8;
an interlayer dielectric layer 12 arranged above the gate electrode 10, above the exposed n+ type source region 8 and above the source ohmic contact electrode 11 above the n+ type source region 8;
a source metal layer 13 disposed on the exposed source ohmic contact electrode 11 and above the interlayer dielectric layer 12;
and a drain ohmic contact electrode 14 provided on the back surface of the n+ type SiC substrate 1.
In this embodiment, the doping concentrations of the source p+ type shielding layer 5 and the gate p+ type shielding ring 6 are the same, and the doping concentrations of the source p+ type shielding layer 5 and the gate p+ type shielding ring 6 are greater than the doping concentration of the second N-type SiC drift layer 4, specifically, the doping concentrations of the source p+ type shielding layer 5 and the gate p+ type shielding ring 6 are at least two orders of magnitude greater than the doping concentration of the second N-type SiC drift layer 4.
In this embodiment, the depth of the source p+ type shielding layer 5 and the gate p+ type shielding ring 6 is smaller than the thickness of the second N-type SiC drift layer 4.
In this embodiment, since the bottom corner of the gate trench may be protected by the space charge region near the source trench, but the space charge region cannot cover the middle position of the bottom of the gate trench, the middle position below the gate trench is provided with the gate p+ type shielding ring, and the corner is not provided.
In this embodiment, relevant parameters of the cell structure of the dual trench SiC MOSFET provided by the present invention are shown in table 1:
TABLE 1
In another embodiment of the present invention, the present invention provides a dual trench SiC MOSFET device comprising a dual trench SiC MOSFET cell structure as described above, wherein the dual trench SiC MOSFET device is formed from a plurality of identical dual trench SiC MOSFET cell structures arranged periodically.
As shown in fig. 2, the preparation method of the dual-trench SiC MOSFET cell structure provided by the present invention includes:
step S1: an n+ -type SiC substrate 1 is provided, and a first N-type SiC drift layer 2 is formed on the n+ -type SiC substrate 1.
As shown in fig. 3, an n+ -type SiC substrate 1 is provided, and a first N-type SiC drift layer 2 is grown on the n+ -type SiC substrate 1 by an epitaxial process.
Step S2: a plurality of floating p+ -type shield rings 3 having a set width and pitch are prepared in the first N-type SiC drift layer 2.
As shown in fig. 4, a plurality of floating p+ -type shield rings 3 having a set width and pitch are prepared in the first N-type SiC drift layer 2 by a local ion implantation method.
Step S3: a second N-type SiC drift layer 4 having a higher doping concentration than the first N-type SiC drift layer 2 is formed on the first N-type SiC drift layer 2, and a source p+ -type shield layer 5 and a plurality of gate p+ -type shield rings 6 each having a shield ring width gradually decreasing from the middle to both sides are formed in the second N-type SiC drift layer 4.
As shown in fig. 5, a second N-type SiC drift layer 4 is grown on the first N-type SiC drift layer 2 by an epitaxial process.
As shown in fig. 6, a local ion implantation method is adopted to prepare a source p+ type shielding layer 5 at two side positions in the second N-type SiC drift layer 4, and a plurality of gate p+ type shielding rings 6 are prepared at intermediate positions in the second N-type SiC drift layer 4, specifically, since the source p+ type shielding layer 5 and the gate p+ type shielding rings 6 are formed by adopting the local ion implantation method, no additional process steps are required, and the process steps are simplified.
Step S4: a P-type base region 7 is formed between the source p+ -type shield layer 5 and the gate p+ -type shield ring 6.
As shown in fig. 7, a P-type base region 7 is formed between the source p+ -type shield layer 5 and the gate p+ -type shield ring 6 by a local ion implantation method.
Step S5: an n+ -type source region 8 is formed on the second N-type SiC drift layer 4.
As shown in fig. 8, an n+ type source region 8 is formed on the second N-type SiC drift layer 4 by a local ion implantation method.
Step S6: a gate electrode 10, a source ohmic contact electrode 11, an interlayer dielectric layer 12, a source metal layer 13, and a drain ohmic contact electrode 14 are formed, respectively.
As shown in fig. 9, a local etching method is adopted to etch the n+ type source region 8 and the source p+ type shielding layer 5 below the n+ type source region 8 to form a source trench penetrating into the source p+ type shielding layer 5, and etch the P type base region 7 below the n+ type source region 8, the second N-type SiC drift layer 4 and the gate p+ type shielding ring 6 in the second N-type SiC drift layer 4 to form a gate trench penetrating into the region where the gate p+ type shielding ring 6 is located.
As shown in fig. 10, a gate dielectric layer 9 is formed on the bottom and inner sidewalls of the gate trench by a thermal oxidation process, and a gate electrode 10 is formed on the gate dielectric layer 9 by a polysilicon deposition process.
As shown in fig. 11, a source ohmic contact electrode 11 is formed at the bottom, side walls, and upper partial region of the n+ -type source region 8 of the source trench, and a drain ohmic contact electrode 14 is formed at the back surface of the n+ -type SiC substrate 1.
As shown in fig. 12, an interlayer dielectric layer 12 is formed over the gate electrode 10, over the exposed n+ type source region 8, and over the source ohmic contact electrode 11 located over the n+ type source region 8 by a deposition process.
As shown in fig. 13, a deposition process is used to form a source metal layer 13 on the exposed source ohmic contact electrode 11 and over the interlayer dielectric layer 12.
In the first embodiment of the present invention, the floating p+ type shield ring 3 is made to include 2 shield rings, denoted as n=2, in the process of preparing the cell structure of the double trench type SiC MOSFET, wherein the doping concentration of the second N-type SiC drift layer 4 is 8e16cm -3 The doping concentration of the floating P+ type shielding ring 3 is5e17cm -3 The depth of the floating P+ type shielding ring 3 is 0.9 mu m.
In the second embodiment of the present invention, the floating p+ type shield ring 3 is made to include 4 shield rings in the number of n=4 in the process of preparing the cell structure of the double trench type SiC MOSFET, wherein the doping concentration of the second N-type SiC drift layer 4 is 7e16cm -3 The doping concentration of the floating P+ type shielding ring 3 is 5e17cm -3 The depth of the floating P+ type shielding ring 3 is 0.6 mu m.
Comparing the double-groove type SiC MOSFET cell structure obtained in the two embodiments with the traditional double-groove type SiC MOSFET cell structure without the grid electrode P+ type shielding ring, the floating P+ type shielding ring and the second N-type SiC drift layer with the doping concentration higher than that of the first N-type SiC drift layer, wherein the doping concentration of the source electrode P+ type shielding layer of the traditional double-groove type SiC MOSFET cell structure is 5e18cm -3 The remaining conditions are the same as those in the acquisition process of the above two embodiments.
As shown in fig. 14, when the drain voltage is 1200V, since the gate p+ type shielding ring and the floating p+ type shielding ring are used to enhance the protection of the gate trench, the peak value of the electric field in the gate dielectric layer in the first embodiment of the present invention is reduced to half of the peak value of the electric field in the gate dielectric layer of the conventional dual trench SiC MOSFET cell structure, which means that the reliability of the gate dielectric layer is improved, and the service life of the device is advantageously prolonged.
As shown in fig. 15, comparing the drain voltage-drain current density curves corresponding to the dual-trench SiC MOSFET cell structure obtained in the first embodiment of the present invention, the dual-trench SiC MOSFET cell structure obtained in the second embodiment, and the conventional dual-trench SiC MOSFET cell structure at a gate voltage of 20V, respectively, it can be concluded that the dual-trench SiC MOSFET cell structure obtained in the first embodiment and the dual-trench SiC MOSFET cell structure obtained in the second embodiment have higher drain currents due to the use of the second N-type SiC drift layer having a higher doping concentration than the first N-type SiC drift layer under the same drain voltage, meaning lower on-resistance, which is advantageous for reducing the static loss of the SiC MOSFET.
As shown in fig. 16 and 17, the reverse recovery current curves in the turn-off process of the body diode corresponding to the double-trench SiC MOSFET cell structure obtained in the first embodiment, the double-trench SiC MOSFET cell structure obtained in the second embodiment, and the conventional double-trench SiC MOSFET cell structure are compared, and the current oscillation amplitude in the turn-off process of the body diode corresponding to the double-trench SiC MOSFET cell structure obtained in the first embodiment and the double-trench SiC MOSFET cell structure obtained in the second embodiment is lower, so that the probability of damaging the device by current overshoot can be reduced, and electromagnetic interference is reduced; and the turn-off speed of the current is faster, which is beneficial to reducing the switching loss of the system and improving the working frequency of the system.
It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.
In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A dual trench SiC MOSFET cell structure, the cell structure comprising:
an N+ type SiC substrate (1);
a first N-type SiC drift layer (2) provided above the N+ type SiC substrate (1);
a plurality of floating p+ -type shield rings (3) provided in the first N-type SiC drift layer (2);
a second N-type SiC drift layer (4) provided above the first N-type SiC drift layer (2);
source p+ -type shield layers (5) provided at both side positions in the second N-type SiC drift layer (4);
a gate trench provided at an intermediate position in the second N-type SiC drift layer (4);
a gate dielectric layer (9) arranged on the bottom and the inner side wall of the gate trench;
a gate electrode (10) disposed on the gate dielectric layer (9);
a plurality of gate p+ -type shield rings (6) provided in the second N-type SiC drift layer (4), the intermediate positions of the gate trenches partially covering the plurality of gate p+ -type shield rings (6);
a P-type base region (7) arranged between the source P+ type shielding layer (5) and the grid P+ type shielding ring (6);
an N+ type source region (8) arranged above the source P+ type shielding layer (5) and the P type base region (7);
and a source trench, a source ohmic contact electrode (11), an interlayer dielectric layer (12), a source metal layer (13) and a drain ohmic contact electrode (14).
2. The double trench type SiC MOSFET cell structure according to claim 1, characterized in that the gate p+ -type shield ring (6) includes respective shield ring widths that gradually decrease from the middle to the both sides, and the sum of the total width of the gate p+ -type shield ring (6) and the total width of the floating p+ -type shield ring (3) is equal to the width of the gate trench.
3. The double trench type SiC MOSFET cell structure according to claim 2, characterized in that the floating p+ -type shield ring (3) includes an even number of shield rings, the gate p+ -type shield ring (6) includes an odd number of shield rings, and the floating p+ -type shield ring (3) includes one more shield rings than the gate p+ -type shield ring (6).
4. A double trench SiC MOSFET cell structure according to claim 3, characterized in that the floating p+ -type shield ring (3) comprises a single shield ring width and the gate p+ -type shield ring (6) comprises a single shield ring width of not less than 0.1 μm.
5. The double trench SiC MOSFET cell structure according to claim 1, characterized in that the doping concentration of the second N-type SiC drift layer (4) is greater than the doping concentration of the first N-type SiC drift layer (2).
6. The double trench SiC MOSFET cell structure according to claim 1, characterized in that the doping concentration of the source p+ -type shield layer (5) and the gate p+ -type shield ring (6) is the same, the doping concentration of the source p+ -type shield layer (5) and the gate p+ -type shield ring (6) being greater than the doping concentration of the second N-type SiC drift layer (4).
7. The double trench SiC MOSFET cell structure according to claim 1, characterized in that the source trench is provided at a left position of the n+ -type source region (8) located on the left, a source p+ -type shield layer (5) located under the n+ -type source region (8) located on the left, and a right position of the source p+ -type shield layer (5) located under the n+ -type source region (8) located on the right; the source ohmic contact electrode (11) is arranged at the bottom and the side wall of the source trench and in a partial area above the N+ type source region (8); the interlayer dielectric layer (12) is arranged above the gate electrode (10), above the exposed N+ type source region (8) and above the source ohmic contact electrode (11) above the N+ type source region (8); the source metal layer (13) is arranged on the exposed source ohmic contact electrode (11) and above the interlayer dielectric layer (12); the drain ohmic contact electrode (14) is provided on the back surface of the n+ type SiC substrate (1).
8. A double trench SiC MOSFET device comprising a double trench SiC MOSFET cell structure according to any one of claims 1 to 7.
9. A method for fabricating a dual trench SiC MOSFET cell structure according to any one of claims 1 to 7, comprising:
providing an N+ type SiC substrate (1), and forming a first N-type SiC drift layer (2) on the N+ type SiC substrate (1);
preparing a plurality of floating P+ type shielding rings (3) with set widths and intervals in the first N-type SiC drift layer (2);
forming a second N-type SiC drift layer (4) with higher doping concentration than the first N-type SiC drift layer (2) on the first N-type SiC drift layer (2), and forming a source P+ type shielding layer (5) and a plurality of grid P+ type shielding rings (6) with the widths of the shielding rings gradually reduced from the middle to the two sides in the second N-type SiC drift layer (4);
a P-type base region (7) is formed between the source P+ type shielding layer (5) and the grid P+ type shielding ring (6);
forming an n+ type source region (8) on the second N-type SiC drift layer (4);
a gate electrode (10), a source ohmic contact electrode (11), an interlayer dielectric layer (12), a source metal layer (13), and a drain ohmic contact electrode (14) are formed, respectively.
10. The method of manufacturing a dual trench SiC MOSFET cell structure according to claim 9, wherein forming the gate electrode (10), the source ohmic contact electrode (11), the interlayer dielectric layer (12), the source metal layer (13) and the drain ohmic contact electrode (14) respectively includes:
etching the N+ type source region (8) and the source P+ type shielding layer (5) below the N+ type source region (8) to form a source trench penetrating into the source P+ type shielding layer (5), and etching a P type base region (7) below the N+ type source region (8), a second N-type SiC drift layer (4) and a grid P+ type shielding ring (6) in the second N-type SiC drift layer (4) to form a grid trench penetrating into the region where the grid P+ type shielding ring (6) is located;
forming a gate dielectric layer (9) on the bottom and the inner side wall of the gate trench, and forming a gate electrode (10) on the gate dielectric layer (9) through a polysilicon deposition process;
forming a source ohmic contact electrode (11) at the bottom and side walls of the source trench and in a partial region above the N+ type source region (8), and forming a drain ohmic contact electrode (14) at the back surface of the N+ type SiC substrate (1);
forming an interlayer dielectric layer (12) above the gate electrode (10), above the exposed N+ type source region (8) and on a source ohmic contact electrode (11) above the N+ type source region (8);
a source metal layer (13) is formed on the exposed source ohmic contact electrode (11) and above the interlayer dielectric layer (12).
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