GB2592928A - Insulated gate switched transistor - Google Patents

Insulated gate switched transistor Download PDF

Info

Publication number
GB2592928A
GB2592928A GB2003442.7A GB202003442A GB2592928A GB 2592928 A GB2592928 A GB 2592928A GB 202003442 A GB202003442 A GB 202003442A GB 2592928 A GB2592928 A GB 2592928A
Authority
GB
United Kingdom
Prior art keywords
layer
base layer
trench
semiconductor device
drift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB2003442.7A
Other versions
GB202003442D0 (en
Inventor
Rahimo Munaf
Nistor Iulian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MQSemi AG
Original Assignee
MQSemi AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MQSemi AG filed Critical MQSemi AG
Priority to GB2003442.7A priority Critical patent/GB2592928A/en
Publication of GB202003442D0 publication Critical patent/GB202003442D0/en
Publication of GB2592928A publication Critical patent/GB2592928A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Thyristors (AREA)

Abstract

A semiconductor device comprises a drift layer 4 (e.g. silicon or silicon carbide), source region 7, first, second and third base layers, trench gate electrode 11, and trench insulating layer 12. The second base layer 8 is higher doped than the first base layer 9, and the peak dopant concentration of the third base layer 1 is lower than 5x1017/cm3. The third base layer may extend deeper than the depth of the trench gate recess. This Insulated Gate Switched Transistor (IGST) differs from an Insulated Gate Bipolar Transistor (IGBT) in that the N+ doped source regions are not connected to the N-doped drift layer only through a MOS inversion channel. Instead, the conduction path of electrons includes (a) a highly P-doped base layer forming an inversion channel similar to a classical IGBT, and (b) a lightly P-doped third base layer 1 acting as the latched-up part of a thyristor base region conduction. The design provides higher blocking capability and protection from high peaks of the electric field in blocking mode. A trench planar gate structure (Figures 7, 8) is also provided.

Description

DESCRIPTION
INSULATED GATE SWITCHED TRANSISTOR
FIELD OF THE INVENTION
The invention relates to the field of power semiconductor devices. Power semiconductor devices that are able to withstand a blocking voltage of several hundred Volts at high current rating are typically implemented as vertical or lateral structures, wherein the semiconductor substrate is based for example on a semiconducting material such as silicon (Si) or silicon carbide (SiC) or diamond or gallium oxide (Ga203) or gallium nitride (GaN) or zinc oxide (Zn0).
TECHNICAL BACKGROUND
Planar and Trench MOS transistor cell designs exhibit a number of advantages and disadvantages for IGBT and MOSFET designs. For IGBTs, typical Planar and Trench designs are shown in FIGS. 1 and 2. Both designs can incorporate a hole barrier or enhancement layer of N-type doping for improved excess carrier storage and lower on-state conduction losses (not shown in Figures).
FIG. 1 shows a prior art IGBT with planar gate electrodes in accordance to U.S. Patent No. 5,795,793, for example. The IGBT 100 is a device with a four-layer structure, which are arranged between an emitter electrode (3) on an emitter side (31) and a collector electrode (2) on a collector side (21), which is arranged opposite of the emitter side (31). An (N-) doped drift layer (4) is arranged between the emitter side (31) and the collector side (21). A P-doped planar base layer (9) is arranged between the drift layer (4) and the emitter electrode (3). A planar N-doped source region (7) is arranged on the emitter side (31) embedded into the planar base layer (9) and contact opening (14) to the emitter electrode (3). In addition, a planar P-doped layer (8) is arranged on the emitter side (31) below region (7) and embedded into the planar base layer (9), and a contact opening (14) through region (7) and extending to region (8) is formed for the emitter electrode (3) A planar gate electrode (10) is arranged on top of the emitter side (31). The planar gate electrode (10) is electrically insulated from the planar base layer (9), the planar source region (7) and the drift layer (4) by a planar insulating layer (12). There is a further insulating layer (13) arranged between the planar gate electrode (10) and the emitter electrode (3). On the collector side (21), and at the surface of the drift layer (4), an N-doped buffer or field stop layer (5) can also be used in Punch-Through designs. Finally, to ensure the bipolar operating regime, a P-doped collector layer is further formed on the buffer layer.
The Planar design in general provides good blocking capability due to low peak fields at the cell and in between the cells. The Planar design can also provide good controllability and low switching losses and the cell densities in planar designs are easily adjusted for the required short circuit currents. Due to the fact that there exist few high peak electric fields in the gate oxide regions, the planar design offers good reliability with respect to parameter shifting during operation under high voltages.
The trench cell concept for the IGBT 200 shown in FIG. 2 offers a vertical MOS channel (16) which provides enhanced injection of electrons in the vertical direction and suffer from no drawbacks from charge spreading (WET effect) near the cell. Therefore, the IGBT with trench gate (11) cells show much improved carrier enhancement for lower conduction losses. Due to the vertical channel design, the trench offers also less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel. Modern Trench designs adopting mesa widths (trench to trench distance) below lp.m achieve very low conduction losses since closely packed trenches can provide a strong barrier to hole drainage. Matching such a performance with less complex processes can be of a great advantage. The accumulation layer at the bottom of the trench gate (11) offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches show optimum performance.
Furthermore, the Trench design offers large cell packing density for reduced channel resistance. In the vast majority of prior art, during the conduction mode, the MOS channel (16) connects directly to the source region (7) and the drift layer (4). One significant limitation of traditional Trench MOS designs is the high electric field developing in blocking mode at the bottom corners of the trench gate (11). The U.S. Patent Application No. 2019/0006496 describes an approach for Trench designs by using a floating layer of low P-doped semiconductor material having a maximum peak concentration of 1elcm5 formed adjacently to a hole barrier or enhancement layer, and interposed between the enhancement layer and the drift layer. The floating layer fully envelops the bottom regions of the gate trenches, and therefore reduces the electric field intensity at the gate corners, but also at the junction between the first base layer and the enhancement layer.
In the prior art shown in the Japanese Patent Application No. 2019/145836, the first base layer has a convex protrusion that extends deeper than the gate trenches. It is specifically claimed that the vertical depth of the first base layer in the regions away from the convex protrusion must be shallower by about 0.1 to 0.2pm compared to the position of the bottom of the gate trenches, i.e. the trench gates clearly reach into the drift region. Thus, the semiconductor device maintains a MOS channel region along the trench gates, which during conduction mode, will directly connect the source region with the drift layer.
Another approach in prior art combines Planar and Trench cell designs for example the paper "A Trench Planar MOSFET cell" (Solid State Electronics, V38, No 4, page 821-828, 1995) represents the first publication of a Trench Planar MOS cell design. A similar design was published as a Trench Planar IGBT (IEEE Electron Device Letters, Vol 20, No.11, Nov.
1999, page 580). The Trench Planar IGBT 300 design shown in FIG. 3 consist only of a planar channel and proposes a trench structure to improve carrier accumulation. The concept proposed the use of shallow trenches for improved blocking capability. The use of enhancement layers has been also proposed in connection with Trench Planar designs. For example, U.S. Patent No. 9,093,522, describes a Trench Planar design IGBT 400 having a single planar channel (15) and an enhancement layer (17), as shown in FIG. 4A. In the same patent, a further embodiment is described where the channel (15) extends to include a trench section (16) as shown in FIG. 4B.
In related prior art, for example U.S. Patent No. 6,380,586 and U.S. Patent No. 8,441,046 describe a trench IGBT 450 where planar channels (15) are orthogonally positioned in relation to trench regions as shown in FIG. 5A for an embodiment having a discontinued trench at the emitter electrode (3). A continuous trench cutting through the emitter electrode (3) was also described. The main feature of this structure is the trench channel (16) which will provide electron injection in both lateral and vertical dimensions at the trench wall as shown in the cross-section along the cutline B-B' as shown in FIG. 513. Such a power transistor will have different MOS parameters for the vertical and lateral channels, such as the threshold voltage. Furthermore, for the discontinued version, the trench MOS channel (16) at the trench periphery near (10') can become critical due to the sharp trench curvature in that region.
It is needed to find a new MOS cell design concept that can benefit from advanced trench gate structures, but without generating high electric fields in critical regions during blocking mode. This will enable a semiconductor device with improved on-state losses in conduction mode, while keeping the breakdown voltage practically unchanged.
DISCLOSURE OF THE INVENTION
It may be an object of the present invention to provide a cell design for a new power semiconductor device category offering reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking capability, and good controllability, such as an Insulated Gate Switched Transistor (IGST) with improved electrical characteristics compared to a classical Insulated Gate Bipolar Transistor (IGBT) These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent claims.
The problem is solved by the semiconductor device with the characteristics of claim I. The inventive power semiconductor cell design includes layers of different conductivity types, which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side, which can be arranged opposite of the emitter side in the case of a vertical power semiconductor, but can also be arranged on the same emitter side in the case of lateral power semiconductors. The layers comprise, at a minimum: - a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side, and - a first base layer of a second conductivity type, which is arranged between the drift layer and the emitter electrode, which first base layer is in direct electrical contact to the emitter electrode, and is structured according to a stripe or cellular layout (i.e. hexagonal, round, square shapes arranged in various configurations), and - a source region of the first conductivity type, which is arranged at the emitter side embedded into the first base layer and contacts the emitter electrode; wherein, the source region has a higher dopant concentration than the drift layer, and is structured according to the same cellular or stripe layout as the first base layer, and - a second base layer of the second conductivity type, which is arranged at the emitter side embedded into the first base layer and is situated vertically deeper than the source region and in direct contact with the emitter electrode through a contact opening; wherein, the second base layer has a higher dopant concentration than the first base layer, and can also be structured according to the same cellular layout as the first base layer, and - a third base layer of the second conductivity type, arranged directly adjacent to the first base layer, and interposed between the first base layer, the trench insulating layer, and the drift layer, wherein, the peak dopant concentration of the third base layer is lower than 5x1017cm3 and preferably lower than lx1017/cm3, and more preferably lower than 5x1016/cm3, and - a trench gate electrode, embedded in a trench recess, which trench gate electrode is electrically insulated from the first base layer, the source region, and the third base layer by a trench insulating layer, and -optionally, planar gate electrodes, where each of the planar gate electrodes is electrically insulated from the first base layer, source region, third base layer, and the drift layer by a planar insulating layer.
The third base layer is formed at a depth larger than the bottom of the trench recesses embedding the trench gate electrodes. As such, an inversion channel directly connecting the source regions to the drift layer, as in previous art IGBTs, is not present anymore. Instead of reaching into the drift layer, in this novel concept, the trench gates and the vertical MOS channel in the inverted region of the first base layer, will connect to the third base layer. This is to our knowledge a new type of power semiconductor device. The conduction path from the source regions to the drift layer includes a highly doped first base layer forming a MOS inversion channel and a lightly doped third base layer acting as the latched-up part of a thyristor base region conduction. The latch up occurs due to the presence of an inverted channel in the first base layer and the low doped narrow size of the third base layer especially under the bottom of the gate electrode trenches, combined with the high electron concentration in those regions.
The third base layer is an important structure not only in conduction mode, but also in blocking mode, wherein the third base layer shields the electric field from the corner regions of the trench gates.
In the region between two directly adjacent trench cells, the third base layer can be formed as a contiguous layer, or as a combination of the distinct third base layers of the two cells.
The third base layer extending between two adjacent trench cells is also a key feature in reducing the stored charge between the cells. The input capacitance of the semiconductor device is reduced, leading to improved and controllable switching behaviour during turn-on and short circuit conditions The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and ease of processing, with the potential of applying sub-micron trench technologies, while maintaining or even increasing the breakdown voltage capability.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which: FIG. 1: shows the cross section of a Planar MOS IGBT structure (prior art).
FIG. 2: shows the cross section of a Trench MOS IGBT structure (prior art).
FIG. 3: shows the cross section of a Trench Planar MOS IGBT structure with single channel (prior art).
FIG. 4A shows the cross section of a Trench Planar MOS IGBT structure with enhancement layer and only the planar MOS channel (prior art).
FIG. 4B: shows the cross section of a Trench Planar MOS IGBT structure with enhancement layer and both planar and vertical MOS channels (prior art).
FIG. 5A: shows a 3D view of Trench Planar MOS IGBT structure with trench gate electrodes orthogonal to the planar cells (prior art).
FIG. 5B: shows the cross section along the cut line B-B' in FIG. 5A. (prior art) FIG. 6: shows a cross section of a first exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 7: shows a cross section of a second exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 8: shows a cross section of a third exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 9: shows a 3D view of a fourth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 9B: shows a cross section of the fourth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention, along the cut line A-A' in FIG. 9A.
FIG. 9C: shows a cross section of the fourth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention, along the cut line B-B' in FIG. 25 9A.
FIG. 10A: shows a 3D view of a fifth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 10B: shows a cross section of the fifth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention, along the cut line B-B' in FIG. 30 10A.
FIG. IOC: shows a cross section of a sixth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 11A: shows a cross section of a seventh exemplary embodiment of an Insulated Gate Switched Transistor IGST cell with charge compensation structures according to the invention.
FIG. 11B: shows a cross section of an eight exemplary embodiment of an Insulated Gate Switched Transistor IGST cell with charge compensation structures according to the invention.
FIG. 12: shows a cross section of a ninth exemplary embodiment of an Insulated Gate Switched Transistor IGST cell according to the invention.
FIG. 13: shows the doping concentration of the first exemplary embodiment of an Insulated Gate Switched Transistor IGST cell along the A-A' cutline in FIG. 6 according to the invention.
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
MODES FOR CARRYING OUT THE INVENTION
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure (s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e. g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein.
In this specification, N -doped is referred to as first conductivity type while P -doped is referred to as second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be P -doped and the second conductivity type can be N -doped It will be understood that when an element is referred to as being connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. -between" versus "directly between", "adjacent" versus "directly adjacent" etc.).
The first embodiment is shown in FIG. 6, depicted as trench Insulated Gate Switched Transistor cell 500 (only half of the transistor cell is depicted) consisting of the following layers arranged between an emitter electrode (3) on an emitter side (31) and a collector electrode (2) on a collector side (21), arranged opposite of the emitter side: - a drift layer (4) of a first conductivity type, which is arranged between the emitter side (31) and the collector side (21), and - a first base layer (9) of a second conductivity type, which is arranged on the top of the emitter side (31) between the drift layer (4) and the emitter electrode (3), which first base layer (9) is structured according to a stripe or cell layout, and - a source region (7) of the first conductivity type, which is arranged at the emitter side (31) embedded into the first base layer (9) and in direct contact with the emitter electrode (3), which source region (7) has a higher dopant concentration than the drift layer (4), and is structured according to the same stripe or cell layout as the first base layer (9), and - a second base layer (8) of the second conductivity type, which is arranged at the top of the emitter side (31) embedded into the first base layer (9) and is situated vertically deeper than the source region (7) and in direct contact with the emitter electrode (3), which second base layer (8) has a higher dopant concentration than the first base layer (9), and can also be structured according to the same stripe or cell layout as the first base layer (9), and - a third base layer (1) of the second conductivity type, arranged directly adjacent to the first base layer (9), and interposed between the first base layer (9), the trench insulating layer (12'), and the drift layer (4), and -a trench gate electrode (11), which is arranged on top of the emitter side (31) in a trench recess, which trench gate electrode is electrically insulated from the first base layer (9), the source region (7), and the third base layer (1), by a trench insulating layer (12'), a carrier flow path is formable under positive gate bias voltage between the emitter electrode (3), the source region (7), the MOS channel (16) thru the inverted region of first base layer (9), the non-inverted regions of the third base layer (1), and the drift layer (4).
The third base layer (1) is formed with a maximum depth that is larger than the maximum depth of the bottom of the trench gate electrodes (11) when referenced to the position of the emitter side (31) Thus, the third base layer (1) fully surrounds the trench gate electrodes (11) That is to say that the inversion MOS channel does not directly connect anymore with both the source regions, and the drift layer, as in previous art IGBTs. Instead of reaching into the drift layer (4), in this novel concept, the trench gates (11) and the vertical MOS channel (16) end in the third base layer (1).
The dopant concentration of the third base layer (1) is selected 5x1017/cm1 and preferably lower than 1x1017/cm3, and more preferably lower than 5x1016/cm3. This corresponds to a sheet density of carrier concentration substantially lower than 5x 1012/cm2 within the third base layer (1) on a plane whose distance from the surface on the emitter side (31) is substantially constant. Because the dopant concentration in the third base layer (1) is lowered, this layer does not interfere with the flow of electrons in conduction mode. More specifically, when a voltage bias is applied on the trench gate electrode (11), an inverted MOS channel (16) is formed in the regions of the first base layer (9) and the third base layer (1) right under the insulating layer (12'). However, other regions of the third base layer (1) further away from the insulating layer (12') and the trench gate electrodes (11) will not be inverted, for example the portion of the layer (1) located directly below first base layer (9).
Nonetheless, the inventors confirmed by simulations that electrons will pass through the non -inverted regions of the third base layer (1), and will follow a carrier path that includes: the source regions (7) , the MOS inversion channel (16) in the highly doped first base layer (9) and the lightly doped third base layer (1) acting as the latched-up part of a thyristor base region conduction. The latch up occurs due to the presence of an inverted channel in the first base layer (9) which acts as a thyristor cathode and the low doped narrow size of the third base layer (1) especially under the bottom of the trench gate electrodes (11), combined with the high electron concentration in those regions.
In addition, due to the presence of the third base layer (1) around the trench gate electrode (11), the high electric fields at the corners of the trench recesses embedding the first gate electrodes (11) are significantly reduced, and the breakdown voltage capability of the device is further improved compared to the device without the third base layer (1). This advantageous feature can be further used in the manufacturing process by reducing the thickness of the drift layer (4) for example, without reducing the breakdown voltage capability of the device. A further advantageous feature of the third base layer (1) is that it reduces the high peak electric fields in the MOS cell, leading to improved robustness against cosmic ray related failures As a significant difference to prior art, in the IGST cell 500, the third base layer (1) is electrically biased by design through the contact with the second base layer (8) and emitter electrode (3) via the first base layer (9).
Two adjacent IGST cells as those depicted in FIG. 6 (also called "active transistor cells") can be directly adjacent, or can be separated by additional regions that may include additional trench electrodes spaced, for example, at a wider distance that in the active transistor cells region. In these additional regions, the third base layer (1) could be formed as a contiguous layer, or as a combination of the distinct third base layers of the two transistor cells. This arrangement provides further advantageous benefits of using the third base layer (1) related to the increased controllability of the device during turn-off/on operation or in short-circuit conditions. By adjusting the peak dopant concentration of the third base layer (1), the amount of excess minority carriers (i.e. holes) is reduced in the device, and in some instances the turn-off/on process can be slowed down for better controllability.
The following embodiments include structures comprising also planar gate electrodes (10) which are arranged on top of the emitter side (31). Such inventive IGST cell designs integrate a trench gate with a planar MOS cell in order to gain the advantages of both designs in terms of reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking and good controllability. The planar gate electrodes (10) arc arranged in a manner that their longitudinal direction in a top/plane view of the emitter side (31) is the same as the longitudinal direction of the source regions (7) and of the first base layer (9) in the same plane view (also designated as "the longitudinal direction of the MOS cells"). The longitudinal direction of the trench gate electrodes (11) can be any angle between 0 degrees to 90 degrees (selected depending on the design) with respect to the longitudinal direction of the planar gate electrodes (10) in a top/plane view of the emitter side (31). For example, when the angle is chosen to be 00, the trench recesses of gate electrodes (11) are formed parallel with the longitudinal direction of the planar gate electrodes (10) on the surface of the emitter side (31). When the angle is selected to be 900, the trench gate electrodes (II) will be formed orthogonally to the longitudinal direction of the planar gate electrodes (10) on the surface of the emitter side (31).
The second and third embodiments shown in FIGS. 7 and 8 refer to the use of the third base layer (1) in trench planar structures with a single MOS channel (15), where the trench recesses of the gate electrodes (11) are formed as stripes parallel to the longitudinal direction of the MOS cell as described in the above paragraph. More specifically, in the IGST 501 depicted in FIG. 7, the first base layer (9) is not extending as far as directly contacting the insulating layer (12') portion along the vertical wall of the trench recesses of the gate electrodes (11). In the IGST 502 depicted in FIG. 8, the first base layer (9) is directly adjacent to the insulating layer (12') portion along the vertical wall of the trench recesses of the gate electrodes (11).
FIGS. 9A and 10A depict the fourth and fifth embodiments, referring to the case where the trench recesses of the gate electrodes (11) are formed orthogonally (at an angle of 90°) to the longitudinal direction of the MOS cell as described above. These embodiments are more easily understood in a three-dimensional description. In FIG. 9A, the orthogonal trench gate electrode (11) is shown to reach into the source region (7). The pitch of the trench recesses in the direction -X" can be very narrow, even below I um, without having the challenge of structuring source regions or base layers in between trenches. In addition, the source region (7) and the second base layer (8) have the same lateral spreading in the direction "Z", i.e. the lateral edges of the corresponding doping profiles further away from the contact opening (14) are at the same Z coordinate. This can be better observed in FIG. 9B, which represents the cross section of the IGST 503 along the cut line A-A' in FIG. 9A. The cross section represents the planar part of the IGST 503 and the alignment between the lateral edges of the source region (7) and of the second layer (8) is more easily understood.
The cross section along the cut line B-B' in FIG. 9A (along the vertical wall of the second gate trench) is depicted in FIG. 9C. In this case, a vertical channel through the highly doped second base layer (8) is not formable in conduction mode. The electrons will flow horizontally in the MOS channel (15), and then towards the drift layer (4), along the vertical walls of the trench recesses and thru the third base layer (1). As discussed previously, because the third base layer (1) is low doped, it does not prevent the flow of electrons, i.e. it will latch-up FIG. 10A depicts the fifth embodiment, as the JUST structure 504, where the main modification to the structure IGST 503 is related to the difference of alignment between the lateral edges of the source region (7) and that of the second base layer (8). This can be better seen in FIG. 10B, which shows the cross section of the IGST 504 along the cut line B-B' in FIG. 10A. In this case, the trench gate electrodes (11) reach into the source region (7), and a vertical MOS channel (16) is formable in conduction mode, by inverting the regions of the first base layer (9) directly adjacent to the insulating layer (12'). It is also possible to have a similar three-dimensional arrangement of layers, with the exception that the trench gate electrodes (11) do not reach into the source region (7), as depicted in the IGST 505 from FIG. IOC. Such a structure will have a horizontal MOS channel (15) and a vertical MOS channel (16).
In further embodiments, the drift layer (4) consists of super-junction structures. Specifically, in FIG. 11A, the JUST cell 506 has a drift layer comprising a plurality of pillars of first (4) and second (4') conductivity types arranged in an alternating manner. The physical width of each of the first and second conductivity type pillars and dopant concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type of up to 20% (with the second conductivity type being higher). An advantageous feature of using the third base layer (1) in connection with a drift layer super-junction structure is that a difficult alignment between the pillars (4) and (4') with respect to the MOS cell features, as in prior art, is not needed. The IGST cell 507 depicted in FIG. 11B shows a further embodiment where the drift layer (4) is arranged as a pillar of first conductivity type, and the third base layer (1) is arranged as a pillar of second conductivity type. The third base layer (1) extends below the gate electrode (11) towards the buffer layer (5), and can be directly contacting the buffer layer (5). The same rule mentioned above applies in this case to the physical dimension and dopant concentration of the two conductivity type pillars (4) and (1).
In embodiments described until now, it was possible that the first base layer (9), the second base layer (8), and the third base layer (1) are formed independently of each other. In practice, this means that each of these three base layers will be formed using separate dopant implantation and diffusion manufacturing steps. This provides the ultimate level of flexibility in achieving any desired combination of parameters (e.g. depth, peak dopant concentration) for each of the three base layers. However, in a further embodiment depicted in FIG. 12, it may be possible that, for example, the first base layer (9) and the third base layer (1) are formed together, i.e. using a single dopant implantation manufacturing step, followed by a single diffusion manufacturing step. In other words, the first base layer (9) and the third base layer (1) will jointly represent a single dopant profile, as follows: (a) the first base layer (9) will represent the first, highly doped portion of the dopant profile, and (b) the third base layer (1) will represent the second, lower doped portion of the same dopant profile.
In this case, the manufacturing process can be simplified compared to previous embodiments, but the parameters of the first base layer (9) and of the third base layer (1) cannot be modified independently anymore.
In all embodiments presented herein, the third layer (1) has a depth that is larger than the bottom of the trench gate electrode (11). This means that directly below the bottom of the trench gate electrode (11) there will be a region of second conductivity type dopant, and the position of the PN junction between the third base layer (1), and the drift layer (4) is located some distance away from the bottom of the trench gate (11) and its insulating layer portion (12'). This can be seen in FIG. 13, which depicts the dopant concentration distribution along the cutline A-A' in FIG. 6. When considering the optimal design parameters for an IGST device, one needs to consider in particular the dopant concentration of the third layer (1) at the position of the bottom of the gate trench (11). If the dopant concentration is too high at this point, the electrons from the inversion layer (16) will not latch the third base layer (1) up, and the electrons will not flow unconstrained in the drift layer (4), as described previously. Therefore, based on the simulation results, the dopant concentration of the third base layer (1) at the bottom of the trench gate electrode (11) should be lower than 5x1015/cm1, and preferably lower than 2x1015/cm3.
It is possible to apply the invention to semiconductor devices in which the conductivity type of all layers is reversed, i.e. with a lightly P-doped drift layer. Or semiconductors in which the drift layer is formed of a wide bandgap semiconductor material such as SiC, GaN, Gallium Oxide, ZnO, Aluminium Oxide, Diamond, etc Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof Reference list 1 * third base layer 2: collector metallization (electrode) 21: collector side 3: emitter metallization (electrode) 31: emitter side 4 drift layer, substrate 4' : charge compensation region 5 buffer layer 6 collector layer 7 source regions 8 second base layer 9 first base layer 10: planar gate electrode, electrically conductive layer 10': uncovered trench gate electrode 11 trench gate electrode, electrically conductive layer 12: insulating gate oxide for electrode 10 12' : insulating gate oxide for electrode 11 13 insulation layer for planar cell and trench cell 14 emitter contact opening horizontal channel for planar gate 17: carrier enhancement layer 100: planar MOS cell power semiconductor device (prior art) 200: trench MOS cell power semiconductor device (prior art) 300: trench planar MOS cell power semiconductor device (prior art) 400: trench planar MOS cell power semiconductor device with enhancement layer and
single planar MOS channel (prior art)
401: trench planar MOS cell power semiconductor device with enhancement layer with
planar and trench MOS channels (prior art)
450: trench planar NIOS cell power semiconductor device with gate trenches orthogonal to the longitudinal direction of the planar cells (prior art) 500 to 502: IGST cells according to various embodiments 503 to 505: IGST cells with gate trenches orthogonal to the longitudinal direction of the planar cells, according to various embodiments 506, 507: IGST cells with super-junction type structures 508: IGST cells according to another embodiment

Claims (1)

  1. CLAIMS1 A semiconductor device consisting of multiple transistor cells, each cell comprising: a drift layer of a silicon, silicon carbide (SiC), or any other wide bandgap semiconductor material, having a first conductivity type and two main surfaces; wherein the main surfaces can be on opposite sides of the drift layer or on the same side of the drift layer; a first base layer having a second conductivity type, disposed at the first main surface of the drift region, and extending into the drift region; one or more source regions having the first conductivity type disposed at the first surface of the drift region, directly adjacent to the first base layer and surrounded by the first base layer; a second base layer having the second conductivity type formed independently from the first base layer, higher doped than the first base layer, and disposed over a portion of the first base layer, wherein the second base layer is disposed substantially in the centre of a plane of the source region defined by the first surface; an electrical contact formed on the first surface of the drift layer in direct contact with the second base layer through a contact opening; a third base layer of second conductivity type formed independently from the first and second base layers, arranged adjacent to the first base layer, and interposed between the first base layer, the trench insulating layer, and the drift layer; wherein, the peak dopant concentration of the third base layer is lower than 5 x 1On/cm' and preferably lower than lx1017/cm3, and more preferably lower than 5x10m/cm3; at least one trench gate electrode, of a heavily doped polycrystalline layer or a metal-containing layer, arranged in a trench recess at the first surface of the drift layer, and electrically insulated from the first base layer, the source region, the third base layer, and the drift layer by a trench insulating layer; wherein parts of the said trench insulating layer are in direct contact with at least the first and third base layers; a buffer layer of first conductivity type, arranged on the second main surface of the drift layer; a collector layer of second conductivity type, arranged on the second main surface of the drift layer, interposed between the buffer layer and the collector electrode.A semiconductor device according to claim 1, wherein the third base layer is extending into the drift layer at a maximum depth larger than the maximum depth of the trench recess embedding the gate electrode A semiconductor device according to claim 2, wherein the dopant concentration of the third base layer at the bottom of the trench gate electrode is lower than 5 x1015/cm3, and preferably lower than 2x1015/cm3.A semiconductor device according to claim 2, wherein the third base layer is directly adjacent to the first base layer.A semiconductor device according to claim 1, wherein the first and third base layers are formed together, i.e by using one dopant implantation and diffusion manufacturing step.A semiconductor device according to claim 1, wherein the region between two adjacent transistor cells can comprise a contiguous third base layer, or a combination of the two distinct third base layers of the individual transistor cells; characterized in that, the two distinct third base layers can be in direct contact, or in contact via the drift layer.7 A semiconductor according to claim 1, wherein in addition to one or multiple trench gate electrodes, a planar gate electrode of a heavily doped polycrystalline layer or a metal-containing layer is arranged on the first surface of the drift layer; characterized in that: -the planar gate electrode is in contact with the surrounding layers via a planar insulating layer, and -a portion of the said planar insulating layer is in direct contact with at least the first base layer and the source layer. 3 4.8 A semiconductor device according to claim 7, wherein the trench insulating layer is not in direct contact with the first base layer.9 A semiconductor device according to claim 7, where, in a plane view of the first surface of the drift layer, the trench recesses embedding the trench gate electrodes are formed having a longitudinal direction at an angle between V to 900 with respect to the longitudinal direction of the planar gate electrode in the same plane view of the first surface of the drift layer.A semiconductor device according to claim 8, where, in a plane view of the first surface of the drift layer, the trench recesses embedding the trench gate electrodes are formed having a longitudinal direction at a 90° angle with respect to the longitudinal direction of the planar gate electrode in the same plane view of the first surface of the drift layer; characterized in that, the said trench recesses reach into the source regions.11 A semiconductor device according to claim 9, wherein the source regions extend laterally to a position that is the same or closer than the lateral spreading edge of the second base layer with respect to the edge of the contact opening 12. A semiconductor device according to claim 9, wherein the source regions extend laterally to a position that is further away than the lateral spreading edge of the second base layer, with respect to the edge of the contact opening.13 A semiconductor device according to claim 8, where, in a plane view of the first surface of the drift layer, the trench recesses embedding the trench gate electrodes are formed having a longitudinal direction at a 90° angle with respect to the longitudinal direction of the planar gate electrode in the same plane view of the first surface of the drift layer; wherein, the said trench recesses do not reach into the source regions.14. A semiconductor device according to claim 7, wherein the planar and the plurality of trench gate electrodes are electrically connected.15. A semiconductor device according to claim 7, wherein all or some of the plurality of trench gate electrodes are electrically connected to the emitter electrode.16 A semiconductor device according to claim 7, wherein all or some of the plurality of trench gate electrodes are electrically floating 17. A semiconductor device according to claim 1, wherein the device has a stripe layout design or cellular layout design such as a square, a rectangle, a circle, or a hexagon 18. A semiconductor device according to claim 7, wherein the device has a stripe layout design or cellular layout design such as a square, a rectangle, a circle, or a hexagon.19 A semiconductor device according to any of the claims I thru 17, comprising: a reverse conducting type device with a shorted collector layer arranged at the second main surface of the drift layer between the second main electrode and a buffer layer, wherein, the shorted collector layer is formed by a pattern of opposite conductivity type regions; wherein, the buffer layer of first conductivity type is formed closest to the second main surface of the drift layer, and has a dopant concentration higher than that of the drift layer.A semiconductor device according to claims 1 or 7, wherein the drift layer comprises a plurality of pillars of first and second conductivity types arranged in an alternating manner, characterized in that, the physical width of each of the first and second conductivity type pillars and doping concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance of up to 20% between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type.21. A semiconductor device according to claim 20, wherein the third base layer extends into the drift layer and forms the second conductivity type pillar.22. Semiconductor module package comprising single or multiple devices according to claim 1.23. Power converter with a plurality of semiconductor devices or modules according to claim 1.
GB2003442.7A 2020-03-10 2020-03-10 Insulated gate switched transistor Pending GB2592928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2003442.7A GB2592928A (en) 2020-03-10 2020-03-10 Insulated gate switched transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2003442.7A GB2592928A (en) 2020-03-10 2020-03-10 Insulated gate switched transistor

Publications (2)

Publication Number Publication Date
GB202003442D0 GB202003442D0 (en) 2020-04-22
GB2592928A true GB2592928A (en) 2021-09-15

Family

ID=70278426

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2003442.7A Pending GB2592928A (en) 2020-03-10 2020-03-10 Insulated gate switched transistor

Country Status (1)

Country Link
GB (1) GB2592928A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117457709A (en) * 2022-07-18 2024-01-26 无锡华润华晶微电子有限公司 Semiconductor device structure and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0633611A1 (en) * 1993-07-05 1995-01-11 Philips Electronics Uk Limited Insulated gate bipolar transistor
EP0854518A1 (en) * 1997-01-21 1998-07-22 Plessey Semiconductors Limited Trench insulated gate bipolar transistor
US20070235752A1 (en) * 2006-03-24 2007-10-11 Fujifilm Corporation Insulated gate type thyristor
US20120319136A1 (en) * 2011-02-11 2012-12-20 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device and method for manufacturing the same
US20140175459A1 (en) * 2011-02-11 2014-06-26 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0633611A1 (en) * 1993-07-05 1995-01-11 Philips Electronics Uk Limited Insulated gate bipolar transistor
EP0854518A1 (en) * 1997-01-21 1998-07-22 Plessey Semiconductors Limited Trench insulated gate bipolar transistor
US20070235752A1 (en) * 2006-03-24 2007-10-11 Fujifilm Corporation Insulated gate type thyristor
US20120319136A1 (en) * 2011-02-11 2012-12-20 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device and method for manufacturing the same
US20140175459A1 (en) * 2011-02-11 2014-06-26 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
GB202003442D0 (en) 2020-04-22

Similar Documents

Publication Publication Date Title
US8872264B2 (en) Semiconductor device having a floating semiconductor zone
US9768248B2 (en) Semiconductor device having diode characteristic
US11588045B2 (en) Fortified trench planar MOS power transistor
JP7118033B2 (en) semiconductor equipment
US11404542B2 (en) Trench planar MOS cell for transistors
EP3154091A1 (en) Reverse-conducting semiconductor device
US20220216331A1 (en) Semiconductor device and method for designing thereof
US11264475B2 (en) Semiconductor device having a gate electrode formed in a trench structure
US20240063267A1 (en) Semiconductor device and method for producing same
US20220352315A1 (en) Semiconductor device and method for producing same
KR20220016134A (en) Power Transistor Cells and Power Transistors
GB2592928A (en) Insulated gate switched transistor
US11575032B2 (en) Vertical power semiconductor device and manufacturing method
US20220173227A1 (en) Finfet power semiconductor devices
US20240055498A1 (en) Semiconductor device and method for producing same
GB2612636A (en) Semiconductor device
US11411076B2 (en) Semiconductor device with fortifying layer
US20220384577A1 (en) Semiconductor device and method for designing thereof
CN117810265B (en) Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof
GB2602663A (en) Semiconductor device
JP2015039023A (en) Semiconductor device