CN116581150B - Asymmetric double-groove SiC MOSFET cell structure, device and preparation method - Google Patents
Asymmetric double-groove SiC MOSFET cell structure, device and preparation method Download PDFInfo
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Abstract
The application relates to an asymmetric double-groove SiC MOSFET cell structure, a device and a preparation method, which belong to the technical field of semiconductor devices, wherein the cell structure comprises the following components: the semiconductor device comprises an N++ type SiC substrate, an N-type SiC drift layer, a pseudo source groove, a pseudo source groove P+ type shielding layer, a grid groove and a stacking structure, wherein the pseudo source groove P+ type shielding layer surrounds the left side of the grid groove and part of the position below the grid groove. According to the asymmetric double-groove SiC MOSFET cell structure, the device and the preparation method, the protection of the grid groove can be enhanced, so that the reliability of the grid dielectric layer is improved, and the service life of the device is prolonged; by adopting the N-type current conducting layer with higher doping concentration, the on-resistance can be reduced under the same on-current; the system has the advantages of lower instantaneous power, namely better short circuit characteristic under high voltage, and is beneficial to improving the safety of the system.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to an asymmetric double-groove SiC MOSFET cell structure, a device and a preparation method.
Background
One key challenge faced by SiC MOSFETs is the existence of interface states and scattering effects of trapped charges on electrons at the SiC/Si02 interface, resulting in lower channel mobility and greater on-resistance. In this regard, the use of trench SiCMOSFET structures eliminates the JFET region resistance of planar SiCMOSFET structures, improves channel mobility in another crystal orientation, reduces cell size, increases cell density, and co-promotes on-resistance reduction. However, the bottom of the gate trench of the trench type SiCNMOSFET structure has an electric field concentration effect, so that the critical breakdown voltage is reduced, and the gate dielectric layer has a reliability problem.
To solve this problem, a highly doped p+ -type shield layer may be formed at the bottom of the gate trench such that the electric field peak is transferred from the gate dielectric layer to the shield layer. However, this compresses the path width of the current flowing from the channel into the drift layer, resulting in an increase in on-resistance. The prior double-groove type SiCNOSFET structure can better realize the compromise between critical breakdown voltage and on-resistance, but the electric field concentration effect at the middle position in the bottom of the grid groove is still more serious, and the grid-drain capacitance is higher, thereby limiting the improvement of switching frequency and working efficiency.
Disclosure of Invention
The application aims to provide an asymmetric double-groove SiC MOSFET cell structure, a device and a preparation method thereof, which are used for solving the defects in the prior art.
The application provides an asymmetric double-groove SiC MOSFET cell structure, which comprises the following components:
an N++ type SiC substrate and an N-type SiC drift layer which are stacked in sequence;
a pseudo source trench in an inverted-L shape provided at a left side position of the N-type SiC drift layer, and a source trench in an L shape provided at a right side position of the N-type SiC drift layer;
a dummy source trench p+ -type shield layer disposed in the N-type SiC drift layer surrounding the dummy source trench, and a source trench p+ -type shield layer disposed in the N-type SiC drift layer surrounding the source trench;
the grid groove and the stacking structure are sequentially arranged between the pseudo source groove P+ type shielding layer and the source groove P+ type shielding layer;
wherein the pseudo source trench p+ -type shielding layer surrounds a portion of the left side and the lower side of the gate trench;
the stacked structure comprises an N-type current conducting layer, a P-type base region and an N+ type source region, wherein the N-type current conducting layer surrounds part of the position below and left of a P+ type shielding layer of a source electrode groove, the left side of the N-type current conducting layer extends to the part of the position below a grid electrode groove, the P-type base region is positioned above the N-type current conducting layer and between the grid electrode groove and the P+ type shielding layer of the source electrode groove, and the N+ type source region is positioned between the grid electrode groove and the source electrode groove and above the P-type base region and the P+ type shielding layer of the source electrode groove;
and a grid P+ type gradual change shielding ring is arranged in the N type current conducting layer below the grid groove.
In the above-mentioned scheme, the structure further includes:
a gate dielectric layer disposed on the bottom and inner sidewall of the gate trench and a gate electrode disposed on the gate dielectric layer;
a first source ohmic contact electrode disposed at a bottom, a sidewall, and a portion of a top surface of the dummy source trench;
a second source ohmic contact electrode disposed on the bottom, side walls and top surface of the source trench over the n+ type source region;
a drain ohmic contact electrode disposed below the n++ type SiC substrate;
an isolation medium layer arranged above the first source ohmic contact electrode on the top surface of the pseudo source trench, above the exposed p+ type shielding layer of the pseudo source trench, above the exposed gate medium layer, above the gate electrode, above the exposed N+ type source region and above the second source ohmic contact electrode above the N+ type source region;
and a metal layer disposed on the exposed first source ohmic contact electrode, on the exposed second source ohmic contact electrode, and on the exposed isolation dielectric layer.
In the above scheme, the doping concentration of the N-type current conducting layer is higher than the doping concentration of the N-type SiC drift layer.
In the above scheme, the interval between the N-type current conducting layer and the P+ type shielding layer of the pseudo source electrode groove is larger than 0.1 mu m.
In the above scheme, the cross section of the grid P+ type gradual change shielding ring is semicircular, and the edge of the grid P+ type gradual change shielding ring coincides with the edge of the N type current conducting layer.
In the above scheme, the doping concentration of the grid p+ type graded shielding ring is higher than that of the N type current conducting layer.
In the above scheme, the depth of the dummy source trench is the same as that of the source trench and is greater than that of the gate trench.
The asymmetric double-groove SiC MOSFET device provided by the application comprises the asymmetric double-groove SiC MOSFET cell structure.
The preparation method of the asymmetric double-groove SiC MOSFET cell structure provided by the application comprises the following steps:
step S1: providing an N++ type SiC substrate and an N-type SiC drift layer which are sequentially stacked, and forming an N-type current conducting layer at a right side position in the N-type SiC drift layer;
step S2: forming a pseudo source trench p+ type shielding layer at a left side position in the N-type SiC drift layer, forming a source trench p+ type shielding layer at a right side position in the N-type current conducting layer, and forming a P-type base region between the pseudo source trench p+ type shielding layer and the source trench p+ type shielding layer, and forming an n+ type source region in the source trench p+ type shielding layer and the P-type base region;
step S3: partially etching the right side of the P+ type shielding layer of the pseudo source electrode groove, and etching the left side of the N+ type source region and the P type base region below the left side of the N+ type source region to form a grid electrode groove;
step S4: forming a grid P+ type gradual change shielding ring in the N type current conducting layer below the grid groove;
step S5: forming a gate dielectric layer on the bottom and the inner side wall of the gate trench, and forming a gate electrode on the gate dielectric layer;
step S6: partially etching the left side of the P+ type shielding layer of the pseudo source electrode groove to form a pseudo source electrode groove, and partially etching the P+ type shielding layer of the source electrode groove on the right side of the N+ type source region and below the right side of the N+ type source region to form a source electrode groove;
step S7: and respectively forming a first source ohmic contact electrode, a second source ohmic contact electrode, a drain ohmic contact electrode, an isolation medium layer and a metal layer on the structure formed in the steps.
In the above scheme, step S7 includes:
forming a first source ohmic contact electrode at the bottom, the side wall and a part of the top surface of the pseudo source trench, forming a second source ohmic contact electrode above an N+ type source region above the bottom, the side wall and the top surface of the source trench, and forming a drain ohmic contact electrode below the N++ type SiC substrate;
an isolation medium layer above a first source ohmic contact electrode on the top surface of the pseudo source trench, above a p+ type shielding layer of the exposed pseudo source trench, above an exposed gate medium layer, above a gate electrode, above an exposed N+ type source region, and above a second source ohmic contact electrode above the N+ type source region;
and forming metal layers on the exposed first source ohmic contact electrode, the exposed second source ohmic contact electrode and the exposed isolation dielectric layer respectively.
The embodiment of the application has the following advantages:
according to the asymmetric double-groove SiC MOSFET cell structure, the device and the preparation method, the protection of the grid groove can be enhanced through the grid P+ type gradual change shielding ring arranged below the grid groove and the pseudo source groove P+ type shielding layer with smaller distance from the grid groove, so that the reliability of the grid dielectric layer is improved, and the service life of the device is prolonged; by adopting the N-type current conducting layer with higher doping concentration, the on-resistance can be reduced under the same on-current; the grid P+ type gradual change shielding ring is adopted for pinch-off, so that the grid P+ type gradual change shielding ring has lower instantaneous power, namely better short circuit characteristic, under high pressure, and is beneficial to improving the safety of a system; the structure provided by the application can reduce the switching time and switching loss of the device.
Drawings
Fig. 1 is a block diagram of an asymmetric double trench SiC MOSFET cell structure of the present application.
Fig. 2 is a step diagram of a preparation method of an asymmetric double-groove SiC MOSFET cell structure according to the present application.
Fig. 3 is a schematic view of a process of forming an n++ type SiC substrate and an N-type SiC drift layer of the present application.
Fig. 4 is a schematic diagram of a process for forming an N-type current conducting layer according to the present application.
Fig. 5 is a schematic process diagram of forming a dummy source trench p+ type shield layer and a source trench p+ type shield layer according to the present application.
Fig. 6 is a schematic diagram of a process for forming a P-type base region according to the present application.
Fig. 7 is a schematic diagram of a process for forming an n+ type source region according to the present application.
Fig. 8 is a schematic diagram of a process of forming a gate trench according to the present application.
Fig. 9 is a schematic diagram of a process for forming a gate p+ type graded shield ring according to the present application.
Fig. 10 is a schematic diagram of a process for forming a gate dielectric layer according to the present application.
Fig. 11 is a schematic view of a process of forming a gate electrode according to the present application.
Fig. 12 is a schematic view of a process of forming a dummy source trench and a source trench according to the present application.
Fig. 13 is a schematic view of a process of forming a first source ohmic contact electrode, a second source ohmic contact electrode, and a drain ohmic contact electrode according to the present application.
Fig. 14 is a schematic view of a process for forming an isolation dielectric according to the present application.
Fig. 15 is a schematic view of a process for forming a metal layer according to the present application.
Fig. 16 is an electric field distribution diagram in a comparative example of the present application.
Fig. 17 is a graph of a first drain voltage versus drain current density in a comparative example of the present application.
Fig. 18 is a graph of second drain voltage versus drain current density in a comparative example of the present application.
Fig. 19 is a gate charge-gate voltage graph in a comparative example of the present application.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
As shown in fig. 1, the present application provides an asymmetric double-trench SiC MOSFET cell structure, which is characterized in that the structure includes:
an n++ type SiC substrate 1 and an N-type SiC drift layer 2 stacked in this order;
a pseudo source trench in an inverted L shape provided at a left side position of the N-type SiC drift layer 2, and a source trench in an L shape provided at a right side position of the N-type SiC drift layer 2;
a dummy source trench p+ -type shield layer 4 provided in the N-type SiC drift layer 2 surrounding the dummy source trench, and a source trench p+ -type shield layer 5 provided in the N-type SiC drift layer 2 surrounding the source trench;
a gate trench and a stacked structure sequentially disposed between the dummy source trench p+ -type shield layer 4 and the source trench p+ -type shield layer 5;
the dummy source trench p+ type shielding layer 4 surrounds the left side and the lower part of the gate trench, the dummy source trench p+ type shielding layer 4 covers the corner at the bottom of the gate trench and even the lower part, so that the protection of the gate dielectric layer 9 can be enhanced, meanwhile, the area of the front p+ region of the device is increased, the conduction voltage drop of the body diode can be reduced, the SiC MOSFET device does not need to be used in anti-parallel with an additional diode in some applications, and the area cost of the chip is reduced;
wherein the stacked structure comprises an N-type current conducting layer 3, a P-type base region 6 and an n+ type source region 7, wherein the N-type current conducting layer 3 surrounds a part of positions below and to the left of the source trench p+ type shielding layer 5, the left of the N-type current conducting layer 3 extends to a part of positions below the gate trench, the distance between the N-type current conducting layer 3 and the pseudo source trench p+ type shielding layer 4 is greater than 0.1 [ mu ] m, the P-type base region 6 is located above the N-type current conducting layer 3 and between the gate trench and the source trench p+ type shielding layer 5, the n+ type source region 7 is located between the gate trench and the source trench, and above the P-type base region 6 and the source trench p+ type shielding layer 5, and below the P-type base region 6 and at the bottom of the gate trench are located on the same level (note: since the n+ type source region 7 is formed in the P-type base region 6, the depth of the rest of the base region and the gate trench is not expressed from top to bottom here);
a grid P+ type gradual change shielding ring 8 is arranged in the N type current conducting layer 3 below the grid groove, specifically, the edge of the grid P+ type gradual change shielding ring 8 coincides with the edge of the N type current conducting layer 3, the influence on the blocking capacity and parasitic capacitance of a device can be reduced, the cross section of the grid P+ type gradual change shielding ring 8 is semicircular, the interval between the grid P+ type gradual change shielding rings 8 is not smaller than 0.1 mu m and not larger than 0.5 mu m, the compression of a current channel in a conducting state is reduced while the sufficient protection area is provided for the bottom of the grid groove in a blocking state is ensured, and the comprehensive performance of the device is improved; under high drain voltage, the grid P+ type gradual change shielding ring 8 can pinch off a current channel, so that a peak value of current is reduced, the device is prevented from being damaged by high instantaneous power, and the short circuit capacity of the device is improved;
a gate dielectric layer 9 disposed on the bottom and inner sidewalls of the gate trench and a gate electrode 10 disposed on the gate dielectric layer 9;
a first source ohmic contact electrode 11 provided at a bottom, a sidewall, and a portion of the top surface of the dummy source trench;
a second source ohmic contact electrode 12 disposed over the n+ -type source region 7 at the bottom, side walls, and top surface of the source trench;
a drain ohmic contact electrode 13 provided under the n++ type SiC substrate 1;
an isolation medium layer 14 arranged above the first source ohmic contact electrode 11 on the top surface of the pseudo source trench, above the exposed p+ type shielding layer 4 of the pseudo source trench, above the exposed gate medium layer 9, above the gate electrode 10, above the exposed n+ type source region 7 and above the second source ohmic contact electrode 12 above the n+ type source region 7;
a metal layer 15 disposed on the exposed first source ohmic contact electrode 11, on the exposed second source ohmic contact electrode 12, and on the exposed isolation dielectric layer 14.
Specifically, the asymmetric double-groove SiC MOSFET cell structure provided by the application uses an asymmetric structure, a current channel only exists on one side of the grid groove close to the source groove, the space between the pseudo source groove and the grid groove on the other side can be compressed, and the cell width is reduced, so that the cell density is improved.
Specifically, the doping concentration of the N-type current conducting layer 3 is higher than that of the N-type SiC drift layer 2, and the doping concentration of the N-type current conducting layer 3 is at least 5 times that of the N-type SiC drift layer 2, so that the conduction capability of electrons can be improved, the resistance of the device can be reduced, and the static loss can be reduced.
Specifically, the doping concentration of the gate p+ -type graded shield ring 8 is higher than the doping concentration of the N-type current conducting layer 3 and is at least two orders of magnitude larger than the doping concentration of the N-type current conducting layer 3.
Specifically, the depth of the pseudo source groove is the same as that of the source groove, is 1-1.5 mu m, and is larger than that of the gate groove.
Specifically, the doping concentrations of the dummy source trench p+ -type shield layer 4 and the source trench p+ -type shield layer 5 are the same and at least two orders of magnitude larger than the doping concentration of the N-type current conducting layer 3.
Specifically, a spacing between the gate trench and the dummy source trench is not less than 0.2 [ mu ] m.
In one embodiment of the present application, the parameters related to the asymmetric double-trench SiC MOSFET cell structure provided by the present application are shown in the following table:
TABLE 1 relevant parameter Table of cellular Structure
The application also provides an asymmetric double-groove SiC MOSFET device, which comprises the asymmetric double-groove SiC MOSFET cell structure, wherein in the asymmetric double-groove SiC MOSFET device, a pseudo source groove of one double-groove SiC MOSFET cell structure is continuous with a source groove of an adjacent double-groove SiCNMOSFET cell structure, and a pseudo source groove P+ type shielding layer of one double-groove SiC MOSFET cell structure is continuous with a source groove P+ type shielding layer of an adjacent cell.
As shown in fig. 2, the application provides a method for preparing an asymmetric double-groove SiC MOSFET cell structure, which comprises the following steps:
step S1: an n++ type SiC substrate 1 and an N-type SiC drift layer 2 stacked in this order are provided, and an N-type current conducting layer 3 is formed at a right position in the N-type SiC drift layer 2.
As shown in fig. 3, an n++ type SiC substrate 1 is provided, and an N-type SiC drift layer 2 is grown on the n++ type SiC substrate 1 by an epitaxial process.
As shown in fig. 4, an N-type current conducting layer 3 is formed at a right position in the N-type SiC drift layer 2 by a local ion implantation method.
Step S2: a dummy source trench p+ -type shield layer 4 is formed at a left position in the N-type SiC drift layer 2, and a source trench p+ -type shield layer 5 is formed at a right position in the N-type current conducting layer 3, and a P-type base region 6 is formed between the dummy source trench p+ -type shield layer 4 and the source trench p+ -type shield layer 5, and an n+ -type source region 7 is formed in the source trench p+ -type shield layer 5 and the P-type base region 6.
As shown in fig. 5, a dummy source trench p+ -type shield layer 4 is formed at a left side position in the N-type SiC drift layer 2 by a local ion implantation method, and a source trench p+ -type shield layer 5 is simultaneously formed at a right side position in the N-type current conductive layer 3, wherein doping concentrations of the dummy source trench p+ -type shield layer 4 and the source trench p+ -type shield layer 5 are the same.
As shown in fig. 6, a P-type base region 6 is formed between the pseudo source trench p+ -type shielding layer 4 and the source trench p+ -type shielding layer 5 by a local ion implantation method.
As shown in fig. 7, an n+ type source region 7 is formed in the source trench p+ type shielding layer 5 and the P type base region 6 by a local ion implantation method.
Step S3: and partially etching the right side of the pseudo source groove P+ type shielding layer 4, and etching the left side of the N+ type source region 7 and the P type base region 6 below the left side of the N+ type source region 7 to form a gate groove.
As shown in fig. 8, a partial etching method is adopted to partially etch the right side of the p+ type shielding layer 4 of the pseudo source trench, and etch the left side of the n+ type source region 7 and the P type base region 6 below the left side of the n+ type source region 7, so as to form a gate trench.
Step S4: a gate P + type graded shield ring 8 is formed in the N-type current conducting layer 3 below the gate trench.
As shown in fig. 9, by performing multiple ion implantation processes using masks with different thicknesses, a gate p+ type graded shielding ring 8 is formed in the N type current conducting layer 3 below the gate trench, so that the width of a single gate p+ type graded shielding ring is gradually reduced from top to bottom, the cross-sectional shape of the single gate p+ type graded shielding ring is semicircular, and the compression of the current channel in the on state is reduced while providing sufficient protection area for the bottom of the gate trench in the blocking state is ensured, so that the comprehensive performance of the device is improved.
Step S5: a gate dielectric layer 9 is formed on the bottom and inner sidewalls of the gate trench, and a gate electrode 10 is formed on the gate dielectric layer 9.
As shown in fig. 10, a gate dielectric layer 9 is formed on the bottom and inner sidewalls of the gate trench by a thermal oxidation process.
As shown in fig. 11, a gate electrode 10 is formed on the gate dielectric layer 9 by a polysilicon deposition process.
Step S6: and partially etching the left side of the pseudo source groove P+ type shielding layer 4 to form a pseudo source groove, and partially etching the right side of the N+ type source region 7 and the source groove P+ type shielding layer 5 below the right side of the N+ type source region 7 to form a source groove.
As shown in fig. 12, a partial etching process is adopted to partially etch the left side of the p+ type shielding layer 4 of the pseudo source trench to form a pseudo source trench, and simultaneously partially etch the p+ type shielding layer 5 of the source trench on the right side of the n+ type source region 7 and below the right side of the n+ type source region 7 to form a source trench.
Step S7: the first source ohmic contact electrode 11, the second source ohmic contact electrode 12, the drain ohmic contact electrode 13, the isolation dielectric layer 14, and the metal layer 15 are formed on the structure formed in the above steps, respectively.
As shown in fig. 13, a first source ohmic contact electrode 11 is formed at the bottom, side walls, and part of the top surface position of the dummy source trench, and a second source ohmic contact electrode 12 is formed above the n+ -type source region 7 above the bottom, side walls, and top surface of the source trench, and a drain ohmic contact electrode 13 is formed below the n++ -type SiC substrate 1.
As shown in fig. 14, an isolation medium is deposited over the first source ohmic contact electrode 11 on the top surface of the dummy source trench, over the exposed p+ -type shield layer 4 of the dummy source trench, over the exposed gate dielectric layer 9, over the gate electrode 10, over the exposed n+ -type source region 7, and over the second source ohmic contact electrode 12 over the n+ -type source region 7 by a deposition process, and planarized to form an isolation medium layer 14.
As shown in fig. 15, a deposition process is used to deposit metal on the exposed first source ohmic contact electrode 11, the exposed second source ohmic contact electrode 12, and the exposed isolation dielectric layer 14, and planarize the same to form a metal layer 15.
In a comparative example of the present application, a cell width of 5 μm and a doping concentration of 5e18cm of the source P+ -type shield layer were employed -3 The width of the source P+ type shielding layer is 0.4 mu m, and the asymmetric double-groove SiC MOSFET cell structure provided by the application is adopted to compare the conventional double-groove SiC MOSFET with the asymmetric double-groove SiC MOSFET cell structure provided by the application.
As shown in FIG. 16, when the drain voltage is 1200V, because the asymmetric double-trench SiC MOSFET cell structure provided by the application uses the grid P+ type gradual change shielding ring below the grid trench and the pseudo source trench P+ type shielding layer with smaller spacing with the grid trench to strengthen the protection of the grid trench, the peak value of the electric field in the grid dielectric layer of the asymmetric double-trench SiC MOSFET cell structure provided by the application is less than half of the peak value of the electric field in the grid dielectric layer of the traditional double-trench SiC MOSFET cell structure, which means that the reliability of the grid dielectric layer is improved, and the service life of a device is prolonged.
As shown in fig. 17, comparing the conventional double-trench SiC MOSFET cell structure with the drain voltage-drain current density curves respectively corresponding to the asymmetric double-trench SiC MOSFET cell structure provided by the present application when the gate voltage is 20V, when the drain voltage is lower, because the N-type current conducting layer with higher doping concentration is used, the asymmetric double-trench SiC MOSFET cell structure provided by the present application has higher drain current under the same drain voltage, meaning lower on-resistance, which is beneficial to reducing the static loss of the system.
As shown in fig. 18, comparing the conventional double-trench SiC MOSFET cell structure with the drain voltage-drain current density curves respectively corresponding to the asymmetric double-trench SiC MOSFET cell structure provided by the present application when the gate voltage is 20V, when the drain voltage is higher, the asymmetric double-trench SiC MOSFET cell structure provided by the present application has a lower saturated drain current due to the pinch-off effect of the p+ type graded shield ring of the gate, meaning a lower instantaneous power, i.e. a better short circuit characteristic, which is beneficial to improving the safety of the system.
As shown in fig. 19, comparing the gate charge-gate voltage curves corresponding to the conventional double-trench SiC MOSFET cell structure with the asymmetric double-trench SiC MOSFET cell structure provided by the present application, the asymmetric double-trench SiC MOSFET cell structure provided by the present application can significantly reduce the gate drain charge, which means a smaller miller capacitance, can reduce the switching time and switching loss of the device, and is beneficial to improving the operating frequency of the system.
It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.
In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An asymmetric double-trench SiC MOSFET cell structure, the structure comprising:
an N++ type SiC substrate (1) and an N-type SiC drift layer (2) which are stacked in sequence;
a pseudo source trench in an inverted-L shape provided at a left side position of the N-type SiC drift layer (2), and a source trench in an L shape provided at a right side position of the N-type SiC drift layer (2);
a pseudo source trench p+ -type shield layer (4) provided in the N-type SiC drift layer (2) surrounding the pseudo source trench, and a source trench p+ -type shield layer (5) provided in the N-type SiC drift layer (2) surrounding the source trench;
a gate trench and a stacked structure sequentially arranged between the pseudo source trench p+ -type shielding layer (4) and the source trench p+ -type shielding layer (5);
wherein the pseudo source trench p+ -type shielding layer (4) surrounds a part of the left side and the lower side of the gate trench;
the stacked structure comprises an N-type current conducting layer (3), a P-type base region (6) and an N+ type source region (7), wherein the N-type current conducting layer (3) surrounds the position below and at the left side of the source groove P+ type shielding layer (5), the left side of the N-type current conducting layer (3) extends to the position below the grid groove, the P-type base region (6) is located above the N-type current conducting layer (3) and between the grid groove and the source groove P+ type shielding layer (5), the N+ type source region (7) is located between the grid groove and the source groove and above the P-type base region (6) and the source groove P+ type shielding layer (5);
and a grid P+ type gradual change shielding ring (8) is arranged in the N type current conducting layer (3) below the grid groove.
2. The asymmetric double trench SiC MOSFET cell structure of claim 1, further comprising:
a gate dielectric layer (9) disposed on the bottom and inner sidewall of the gate trench, and a gate electrode (10) disposed on the gate dielectric layer (9);
a first source ohmic contact electrode (11) provided at a bottom, a sidewall, and a portion of a top surface of the dummy source trench;
a second source ohmic contact electrode (12) disposed over the n+ type source region (7) at the bottom, side walls, and top surface of the source trench;
a drain ohmic contact electrode (13) provided below the N++ type SiC substrate (1);
an isolation medium layer (14) arranged above the first source ohmic contact electrode (11) on the top surface of the pseudo source trench, above the exposed p+ type shielding layer (4) of the pseudo source trench, above the exposed gate medium layer (9), above the gate electrode (10), above the exposed n+ type source region (7) and above the second source ohmic contact electrode (12) above the n+ type source region (7);
and the metal layer (15) is arranged on the exposed first source electrode ohmic contact electrode (11), the exposed second source electrode ohmic contact electrode (12) and the exposed isolation medium layer (14).
3. The asymmetric double trench SiC MOSFET cell structure according to claim 1, characterized in that the doping concentration of the N-type current conducting layer (3) is higher than the doping concentration of the N-type SiC drift layer (2).
4. The asymmetric double-trench SiC MOSFET cell structure according to claim 1, characterized in that the spacing between the N-type current conducting layer (3) and the pseudo source trench p+ -type shielding layer (4) is greater than 0.1 μm.
5. The asymmetric double-trench SiC MOSFET cell structure according to claim 1, characterized in that the cross-sectional shape of the gate p+ -type graded shield ring (8) is a semicircle, and the edge of the gate p+ -type graded shield ring (8) coincides with the edge of the N-type current conducting layer (3).
6. The asymmetric double trench SiC MOSFET cell structure of claim 1, characterized in that the doping concentration of the gate p+ -type graded shield ring (8) is higher than the doping concentration of the N-type current conducting layer (3).
7. The asymmetric double trench SiC MOSFET cell structure of claim 1 wherein the dummy source trench is the same depth as the source trench and greater than the depth of the gate trench.
8. An asymmetric double trench SiC MOSFET device comprising an asymmetric double trench SiC MOSFET cell structure according to any one of claims 1 to 7.
9. A method of fabricating an asymmetric double trench SiC MOSFET cell structure according to any one of claims 1 to 7, comprising:
step S1: providing an N++ type SiC substrate (1) and an N-type SiC drift layer (2) which are stacked in sequence, and forming an N-type current conducting layer (3) at a right position in the N-type SiC drift layer (2);
step S2: forming a pseudo source trench p+ -type shield layer (4) at a left position in the N-type SiC drift layer (2), and forming a source trench p+ -type shield layer (5) at a right position in the N-type current conducting layer (3), and forming a P-type base region (6) between the pseudo source trench p+ -type shield layer (4) and the source trench p+ -type shield layer (5), and forming an n+ -type source region (7) in the source trench p+ -type shield layer (5) and the P-type base region (6);
step S3: partially etching the right side of the pseudo source electrode groove P+ type shielding layer (4), and etching the left side of the N+ type source region (7) and the P type base region (6) below the left side of the N+ type source region (7) to form a gate electrode groove;
step S4: forming a grid P+ type gradual change shielding ring (8) in the N type current conducting layer (3) below the grid groove;
step S5: forming a gate dielectric layer (9) on the bottom and the inner side wall of the gate trench, and forming a gate electrode (10) on the gate dielectric layer (9);
step S6: partially etching the left side of the pseudo source groove P+ type shielding layer (4) to form a pseudo source groove, and partially etching the right side of the N+ type source region (7) and the source groove P+ type shielding layer (5) below the right side of the N+ type source region (7) to form a source groove;
step S7: and forming a first source ohmic contact electrode (11), a second source ohmic contact electrode (12), a drain ohmic contact electrode (13), an isolation dielectric layer (14) and a metal layer (15) on the structure formed in the steps.
10. The method of fabricating an asymmetric double trench SiC MOSFET cell structure according to claim 9, wherein step S7 includes:
forming a first source ohmic contact electrode (11) at the bottom, side walls and part of the top surface of the pseudo source trench, forming a second source ohmic contact electrode (12) above an n+ type source region (7) above the bottom, side walls and top surface of the source trench, and forming a drain ohmic contact electrode (13) below the n++ type SiC substrate (1);
an isolation medium layer (14) above the first source ohmic contact electrode (11) on the top surface of the pseudo source trench, above the exposed pseudo source trench P+ type shielding layer (4), above the exposed gate medium layer (9), above the gate electrode (10), above the exposed N+ type source region (7) and above the second source ohmic contact electrode (12) above the N+ type source region (7);
a metal layer (15) is formed on the exposed first source ohmic contact electrode (11), the exposed second source ohmic contact electrode (12) and the exposed isolation dielectric layer (14), respectively.
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