CN115714142B

CN115714142B - Trench gate transistor and preparation method thereof

Info

Publication number: CN115714142B
Application number: CN202310023965.1A
Authority: CN
Inventors: 韩玉亮; 徐承福; 罗顶; 何云; 马跃
Original assignee: Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
Current assignee: Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-05-02
Anticipated expiration: 2043-01-09
Also published as: CN115714142A

Abstract

The embodiment of the invention relates to a trench gate transistor and a preparation method thereof, wherein the trench gate transistor comprises: the semiconductor device comprises a semiconductor material layer, a grid groove, a grid electrode, a grid dielectric layer, a first electric field shielding structure and a second electric field shielding structure; the projection of the first electric field shielding structure and the gate dielectric layer on the plane of the side wall of the gate trench is at least partially overlapped; the projection of the second electric field shielding structure and the gate dielectric layer on the plane where the lower surface of the semiconductor material layer is located at least partially coincides; the bottom corner of the gate dielectric layer comprises a first area, the part of the outer side wall located in the first area is not contacted with the first electric field shielding structure, and the projection of the part of the outer side wall located in the first area on the plane of the lower surface of the semiconductor material layer falls into the projection range of the second electric field shielding structure on the plane of the lower surface of the semiconductor material layer. Therefore, the bottom of the gate dielectric layer is protected, and the influence on the on-resistance of the device is reduced as much as possible.

Description

Trench gate transistor and preparation method thereof

Technical Field

The invention relates to the field of semiconductors, in particular to a trench gate transistor and a preparation method thereof.

Background

Compared with a planar gate transistor, the trench gate transistor can greatly reduce the cell size, thereby greatly improving the current density. For example, compared with a planar gate MOSFET, the performance of the trench gate Metal-Oxide-Semiconductor Field-Effect Transistor field effect transistor (MOSFET) is greatly improved, so that not only can the higher channel mobility be obtained, but also the on-resistance is reduced, and the on-current density and the on-performance of the device are improved.

However, the trench gate transistor faces a reliability problem of the gate dielectric layer, because the bottom of the gate trench is exposed to a high electric field region in the drift region when the device is in a blocking state, so that a portion of the gate dielectric layer at the bottom of the gate trench, particularly at a corner of the bottom, is subjected to a high-intensity electric field, and thus degradation of insulation performance and even early breakdown easily occurs, reducing the stability and lifetime of long-term operation of the device. Particularly, for a silicon carbide (SiC) -based trench gate transistor, since the critical breakdown field strength of silicon carbide is much greater than that of silicon, the portion of the gate dielectric layer at the bottom corner of the gate trench is relatively weaker, and degradation of insulation performance and even early breakdown are more likely to occur.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a trench gate transistor and a method for manufacturing the same to solve at least one of the problems in the background art.

In order to achieve the above purpose, the technical scheme of the application is realized as follows:

in a first aspect, in this embodiment, there is provided a trench gate transistor including:

a layer of semiconductor material;

a gate trench extending from an upper surface of the semiconductor material layer to an inside of the semiconductor material layer;

the grid dielectric layer covers the side wall and the bottom wall of the grid groove, and the grid is positioned in the grid dielectric layer;

the first electric field shielding structure and the second electric field shielding structure are positioned outside the grid groove, wherein the projections of the first electric field shielding structure and the grid dielectric layer on the plane where the side wall of the grid groove is positioned are at least partially overlapped, and the projections of the second electric field shielding structure and the grid dielectric layer on the plane where the lower surface of the semiconductor material layer is positioned are at least partially overlapped; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench;

The bottom corner of the gate dielectric layer comprises a first area, the bottom corner is the intersection of the outer side wall and the outer bottom wall of the gate dielectric layer, the part of the outer side wall in the first area is not contacted with the first electric field shielding structure, and the projection of the part of the outer bottom wall in the first area on the plane of the lower surface of the semiconductor material layer falls into the projection range of the second electric field shielding structure on the plane of the lower surface of the semiconductor material layer; .

Optionally, the second electric field shielding structure is electrically connected to the first electric field shielding structure.

Optionally, the second electric field shielding structure and the first electric field shielding structure are both connected to a ground potential.

Optionally, a portion of the outer bottom wall located within the first region is completely covered by the second electric field shielding structure.

Optionally, the trench gate transistor further includes: a body region and a source contact region; the body region and the source contact region are adjacent to the gate trench, the source contact region extending from an upper surface of the layer of semiconductor material to an interior of the layer of semiconductor material, the body region being located below the source contact region;

The outer side wall of the gate dielectric layer comprises a first part and a second part; wherein the projections of the first portion and the first electric field shielding structure on the plane where the side wall of the gate trench is located coincide, and the second portion is adjacent to the body region and the source contact region.

Optionally, the second electric field shielding structure includes a first second electric field shielding unit and a second electric field shielding unit, and a first gap exists between the first second electric field shielding unit and the second electric field shielding unit.

Optionally, the first electric field shielding structure includes a first electric field shielding unit and a second first electric field shielding unit, a second gap exists between the first electric field shielding unit and the second first electric field shielding unit, and a distance of the first gap is smaller than a distance of the second gap.

Optionally, an overlapping region exists between the second electric field shielding structure and the first electric field shielding structure, and the ion doping concentration of the overlapping region is greater than the ion doping concentration of any one of the second electric field shielding structure and the first electric field shielding structure.

Optionally, a third gap exists between the second electric field shielding structure and the outer bottom wall of the gate dielectric layer.

Optionally, a fourth gap exists between the first electric field shielding structure and the outer side wall of the gate dielectric layer;

the second electric field shielding structure comprises a main shielding region and an auxiliary shielding region, the main shielding region is located under the gate dielectric layer, and the auxiliary shielding region penetrates through the fourth gap to connect the main shielding region and the first electric field shielding structure.

In a second aspect, an embodiment of the present application provides a method for preparing a trench gate transistor, where the method includes:

providing a substrate, and forming a first epitaxial semiconductor material layer on the substrate;

ion implantation is carried out on the upper surface of the first epitaxial semiconductor material layer, so that a second electric field shielding structure is formed;

forming a second epitaxial semiconductor material layer on the first epitaxial semiconductor material layer;

ion implantation is carried out on the upper surface of the second epitaxial semiconductor material layer, so that a first electric field shielding structure is formed;

forming a gate trench extending from the upper surface of the second epitaxial semiconductor material layer to the interior of the second epitaxial semiconductor material layer, and sequentially forming a gate dielectric layer and a gate in the gate trench; the projections of the first electric field shielding structure and the gate dielectric layer on the plane where the side wall of the gate trench is located are at least partially overlapped, and the projections of the second electric field shielding structure and the gate dielectric layer on the plane where the lower surface of the semiconductor material layer is located are at least partially overlapped; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench.

In a third aspect, an embodiment of the present application provides a method for preparing a trench gate transistor, where the method includes:

providing a substrate, and forming a semiconductor material layer on the substrate;

ion implantation is carried out on the upper surface of the semiconductor material layer, so that a first electric field shielding structure is formed;

forming a gate trench extending from an upper surface of the semiconductor material layer to an interior of the semiconductor material layer;

ion implantation is carried out at the bottom of the grid electrode groove to form a second electric field shielding structure;

forming a gate dielectric layer and a gate electrode in the gate trench in sequence; the projection of the first electric field shielding structure and the gate dielectric layer on the plane where the side wall of the gate trench is located at least partially coincides. The first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench.

The trench gate transistor and the preparation method thereof provided by the embodiment of the application, wherein the trench gate transistor comprises: a layer of semiconductor material; a gate trench extending from an upper surface of the semiconductor material layer to an inside of the semiconductor material layer; the grid dielectric layer covers the side wall and the bottom wall of the grid groove, and the grid is positioned in the grid dielectric layer; the first electric field shielding structure and the second electric field shielding structure are positioned outside the grid electrode groove, and projections of the first electric field shielding structure and the grid dielectric layer on a plane where the side wall of the grid electrode groove is positioned are at least partially overlapped; the projection of the second electric field shielding structure and the gate dielectric layer on the plane where the lower surface of the semiconductor material layer is located at least partially coincides; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench; the bottom corner of the gate dielectric layer comprises a first area, the bottom corner is the intersection of the outer side wall and the outer bottom wall of the gate dielectric layer, the part of the outer side wall in the first area is not contacted with the first electric field shielding structure, and the projection of the part of the outer bottom wall in the first area on the plane of the lower surface of the semiconductor material layer falls into the projection range of the second electric field shielding structure on the plane of the lower surface of the semiconductor material layer; therefore, the first electric field shielding structure and the second electric field shielding structure are matched with each other, so that the bottom of the gate dielectric layer is protected, and meanwhile, the influence on the on-resistance of the device is reduced as much as possible; specifically, on one hand, the electric field distribution of the side surface of the grid electrode groove is changed through the first electric field shielding structure, so that the electric field concentration effect of the grid dielectric layer at the bottom corner is relieved to a certain extent; on the other hand, for the bottom corner, the gate dielectric layer at least comprises a first area, the lateral surface of the first area is not contacted with the first electric field shielding structure, so that the formation of a channel is not influenced, the current circulation is facilitated, the second electric field shielding structure is arranged below the first area, the bottom of the gate dielectric layer is protected through the second electric field shielding structure, and the effect of the bottom electric field shielding effect of the gate dielectric layer and the influence on the on-resistance of the trench gate transistor are considered. Therefore, the trench gate transistor and the preparation method thereof provided by the embodiment of the application can improve the stability of long-term operation of the device, prolong the service life of the device, enable the structure to be arranged more flexibly, and facilitate the simplification of the corresponding preparation process.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a schematic perspective view of a trench gate transistor according to an embodiment of the present disclosure;

FIG. 2 is a schematic view of the structure of section A-A of FIG. 1;

FIG. 3 is a schematic view of the structure of section B-B of FIG. 1;

FIG. 4 is a schematic view of the first projection of FIG. 1 along a first direction;

FIG. 5 is a schematic view of the projection of FIG. 1 along a second direction;

FIG. 6 is another schematic view of the projection of FIG. 1 along a second direction;

FIG. 7 is a schematic perspective view in section taken along section C-C of FIG. 1;

FIG. 8 is a schematic perspective view in section taken along section B-B and section C-C of FIG. 1;

fig. 9 is a schematic view of a trench gate transistor according to a second embodiment of the present disclosure along a second direction in fig. 1;

fig. 10 is a schematic perspective view of a cross-section of a trench gate transistor according to a second embodiment of the present disclosure along section C-C in fig. 1;

Fig. 11 is a schematic view of a trench gate transistor according to a third embodiment of the present disclosure along the second direction in fig. 1;

fig. 12 is a schematic perspective view of a trench-gate transistor according to a third embodiment of the present application, which is cross-sectional along the C-C section in fig. 1;

fig. 13 is a schematic structural diagram of a trench-gate transistor according to a fourth embodiment of the present disclosure in a section A-A in fig. 1;

fig. 14 is a schematic structural diagram of a trench-gate transistor according to a fourth embodiment of the present disclosure in a section B-B of fig. 1;

fig. 15 is a schematic view of a trench gate transistor according to a fourth embodiment of the present disclosure along the second direction in fig. 1;

fig. 16 is a schematic perspective view of a trench-gate transistor according to a fourth embodiment of the present application, which is cross-sectional along the C-C section in fig. 1;

fig. 17 is a schematic structural diagram of a trench-gate transistor according to a fifth embodiment of the present application in a section A-A in fig. 1;

fig. 18 is a schematic structural diagram of a trench-gate transistor according to a fifth embodiment of the present disclosure in a section B-B of fig. 1;

fig. 19 is a schematic view of a trench gate transistor according to a fifth embodiment of the present disclosure along the second direction in fig. 1;

fig. 20 is a schematic perspective view of a cross-section of a trench-gate transistor according to a fifth embodiment of the present application along section C-C in fig. 1;

Fig. 21 is a schematic view of a trench gate transistor according to a sixth embodiment of the present disclosure along the second direction in fig. 1;

fig. 22 is a schematic view of a trench gate transistor according to a seventh embodiment of the present disclosure along the second direction in fig. 1;

fig. 23 is a schematic flow chart of a method for manufacturing a trench gate transistor according to an eighth embodiment of the present application;

fig. 24 to 28 are schematic views of a trench-gate transistor according to an eighth embodiment of the present application during various processes in one method for manufacturing the same;

fig. 29 is a schematic flow chart of a method for manufacturing a trench gate transistor according to a ninth embodiment of the present application;

fig. 30 to 34 are schematic views of a trench gate transistor according to a ninth embodiment of the present application during each process in one manufacturing method.

Reference numerals illustrate:

100. a substrate; 110. a layer of semiconductor material; 120. a gate trench; 130. a gate dielectric layer; 131. a bottom corner; 132. a first region; 133. an outer sidewall; 1331. a first portion; 1332. a second portion; 134. an outer bottom wall; 140. a gate; 150. a first electric field shielding structure; 151. a first electric field shielding unit; 152. a second first electric field shielding unit; 160. a second electric field shielding structure; 161. a first and second electric field shielding unit; 1613. a first main shielding region; 1614. a first auxiliary shielding region; 162. a second electric field shielding unit; 1623. a second main shielding region; 1624. a second auxiliary shielding region; 163. a main shielding region; 164. an auxiliary shielding region; 170. a body region; 180. a source contact region; 190. a first electric field shielding structure contact region; 200. and a metal wiring layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical aspects of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.

Example 1

In view of the technical problems in the prior art, an embodiment of the present application provides a trench gate transistor, as shown in fig. 1 to 3, where the trench gate transistor includes a semiconductor material layer 110, a gate trench 120, a gate dielectric layer 130, a gate 140, a first electric field shielding structure 150 and a second electric field shielding structure 160, where:

the gate trench 120 extends from an upper surface of the semiconductor material layer 110 to an interior of the semiconductor material layer 110;

the gate dielectric layer 130 is located in the gate trench 120 and covers the sidewall and the bottom wall of the gate trench 120;

the gate 140 is located in the gate dielectric layer 130;

the first electric field shielding structure 150 and the second electric field shielding structure 160 are located outside the gate trench 120;

the projections of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the side wall of the gate trench 120 is located at least partially coincide;

The projections of the second electric field shielding structure 160 and the gate dielectric layer 130 on the plane where the lower surface of the semiconductor material layer 110 is located at least partially coincide; the first electric field shielding structure 150 and the second electric field shielding structure 160 are both electric field shielding structures corresponding to the gate trench.

The bottom corner 131 of the gate dielectric layer 130 includes a first region 132, where the bottom corner 131 is a junction between an outer sidewall of the gate dielectric layer 130 and an outer sidewall, where the outer sidewall is located in the first region 132 and is not in contact with the first electric field shielding structure 150, and a projection of the portion of the outer sidewall located in the first region 132 on a plane where a lower surface of the semiconductor material layer 110 is located falls within a range of a projection of the second electric field shielding structure 160 on a plane where a lower surface of the semiconductor material layer 110 is located.

Illustratively, the semiconductor material layer 110 may be an epitaxial layer grown on the substrate 100. The substrate 100 may be a base of a transistor device, be a carrier to which a subsequent material layer is added, and the substrate 100 may include a top surface for forming the transistor device and a bottom surface opposite to the top surface, and a direction perpendicular to the top surface and the bottom surface of the substrate 100 is defined as a thickness direction of the substrate 100, ignoring flatness of the top surface and the bottom surface. The thickness direction of the substrate 100 is also the stacking direction of the subsequent layers of materials deposited on the substrate 100, or the height direction of the device, shown in the figure as the "second direction". While the top and bottom surfaces of the substrate 100 are located on, or strictly speaking, the center plane in the thickness direction of the substrate, i.e., defined as the substrate plane. Defining two first and third directions intersecting each other in a substrate plane direction; the first direction and the third direction are, for example, two directions perpendicular to each other. In some embodiments, the layer of semiconductor material 110 comprises an epitaxial layer of silicon carbide. Further, the trench gate transistor is a silicon carbide based trench gate transistor.

In the present embodiment, the plane in which the side walls of the gate trench 120 are located is parallel to the plane determined by the second direction and the third direction; in other words, the plane where the sidewall of the gate trench 120 is located is perpendicular to the first direction, and the projection of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the sidewall of the gate trench 120 is located is the projection of the first electric field shielding structure 150 and the gate dielectric layer 130 along the first direction. In addition, in the present embodiment, the gate trench 120 includes two sidewalls opposite to each other, the two sidewalls are parallel to each other, the projection of the gate trench 120 along the second direction is rectangular (the top plane shape of the gate trench 120 is rectangular), and the two sidewalls correspond to two long sides of the rectangle.

It should be understood that the present application is not limited thereto, and the projection of the gate trench 120 along the second direction may also take other shapes, such as triangle, square, pentagon, hexagon, circle, etc. As such, the gate trench 120 may include a plurality of sidewalls extending along different planar directions, and the projection of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane of the sidewalls of the gate trench 120 at least partially coincides, which means that the projection of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane of any sidewall of the gate trench 120 at least partially coincides. In the case where the projection of the gate trench 120 in the second direction is circular, the plane in which the sidewall of the gate trench 120 is located refers to an external tangential plane.

The first electric field shielding structure 150 is at least partially disposed on the side surface of the gate dielectric layer 130, so as to change the electric field distribution on the side surface of the gate trench 120, and alleviate the electric field concentration effect of the gate dielectric layer 130 at the bottom corner to some extent.

The plane of the lower surface of the semiconductor material layer 110 is the plane of the top surface of the substrate 100, or is understood as the substrate plane. The projection onto the plane of the lower surface of the semiconductor material layer 110 may also be understood as a projection in the second direction.

The second electric field shielding structure 160 is at least partially disposed below the gate dielectric layer 130, so as to directly protect the bottom of the gate dielectric layer 130.

Illustratively, the substrate 100 is an n+ type semiconductor substrate; the semiconductor material layer 110 is an N-type semiconductor layer.

The gate trench 120 may be formed by a photolithography process, for example. Specifically, a mask material is deposited on the semiconductor material layer 110, and then a preset formation position of the gate trench 120 is defined in the mask material through photolithography and etching processes, so as to form a patterned mask layer. This process is well known to those skilled in the art and will not be described in detail here. Next, the semiconductor material layer 110 is etched using the patterned mask layer as a mask until the gate trench 120 is formed. In this embodiment, the gate trench 120 may extend along the third direction.

The portion of the semiconductor material layer 110 under the gate trench 120 is used to form a drift region of the device.

The gate dielectric layer 130 may be a gate oxide layer, specifically, the gate oxide layer may be formed by an oxidation process, a deposition process, or a process of oxidizing and then depositing. The gate dielectric layer 130 in this embodiment may also extend along the third direction corresponding to the gate trench 120.

Illustratively, the material of the gate electrode 140 may be the same as or different from the material of the semiconductor material layer 110. In actual preparation, the material of the gate 140 may be polysilicon.

Illustratively, as shown in fig. 1 and 2, the first electric field shielding structure 150 may be at least partially located at two sides of the gate dielectric layer 130 in the third direction, which may serve to attract an electric field and alleviate the problem of electric field concentration at the corners 131 at the bottom of the gate dielectric layer 130. The at least partial overlap of the projections of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the sidewalls of the gate trench are located may include: the first electric field shielding structure 150 is abutted to the gate dielectric layer 130 in the first direction, the projection portions of the first electric field shielding structure and the gate dielectric layer on the plane where the side wall of the gate trench is located are overlapped, and the non-overlapped portions can be used for flowing on-current when the transistor works. Illustratively, the first electric field shielding structure 150 is of a different conductivity type than the semiconductor material layer 110, and thus may function to attract or deplete a portion of the electric field. The projection of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the sidewalls of the gate trench are located can be seen in fig. 4.

As can be easily understood, since the bottom corner 131 of the gate dielectric layer 130 is weaker, decreasing the electric field strength at the bottom of the gate dielectric layer 130 mainly refers to decreasing the electric field strength at the bottom corner 131 of the gate dielectric layer 130, and the purpose of the two is the same.

Specifically, as shown in fig. 3, the gate dielectric layer 130 includes a first region 132, where the first region 132 is at least a portion of a bottom corner 131 of the gate dielectric layer 130; and specifically a portion satisfying the following condition: the outside of the region has no first electric field shielding structure 150 in contact therewith, and the region has a second electric field shielding structure 160 disposed thereunder; in this way, the first electric field shielding structure 150 is not disposed outside the first region 132, so that the formation of a channel is not affected, current circulation is facilitated, the influence of the first electric field shielding structure 150 on the on-resistance of the trench gate transistor is reduced, and the portion of the gate dielectric layer 130 located in the first region 132 is protected mainly by the second electric field shielding structure 160 disposed below. It will be appreciated that in some embodiments, the bottom corner 131 may include a first region 132, may also include a second region, even a third region, etc.; in other embodiments, the bottom corner 131 may also include only the first region 132, in other words, the entire bottom corner 131 is the first region 132.

Illustratively, as shown in fig. 2 and 3, the second electric field shielding structure 160 is located below the gate dielectric layer 130, that is, located at an end of the gate dielectric layer 130 near the substrate 100 in the second direction.

Illustratively, the second electric field shielding structure 160 is of a different conductivity type than the semiconductor material layer 110, and thus may function to shield or deplete a portion of the electric field. The projections of the second electric field shielding structure 160 and the gate dielectric layer 130 on the plane where the sidewalls of the gate trench are located can be seen in fig. 5 and 6, wherein fig. 5 only shows the projections of the gate electrode 140, the gate dielectric layer 130, the first electric field shielding structure 150 and the second electric field shielding structure 160, and fig. 6 only shows the projections of the first electric field shielding structure 150 and the second electric field shielding structure 160.

The arrangement of the first electric field shielding structure 150 has the effect of reducing the electric field intensity at the corner 131 at the bottom of the gate dielectric layer 130, and also has the adverse effect of reducing the channel area of the on-current flow when the trench gate transistor is operated, thereby increasing the on-resistance of the device. Therefore, the shape and volume of the first electric field shielding structure 150 are limited, so that the effect of reducing the electric field intensity at the bottom corner 131 of the gate dielectric layer 130 is limited. Therefore, the embodiment of the application further provides a second electric field shielding structure 160, and the first electric field shielding structure 150 and the second electric field shielding structure 160 are mutually matched to realize the protection of the bottom of the gate dielectric layer 130, and simultaneously reduce the influence on the on-resistance of the device as much as possible; specifically, on one hand, the electric field distribution of the side surface of the gate trench is changed through the first electric field shielding structure 150, so that the electric field concentration effect of the gate dielectric layer at the bottom corner is relieved to a certain extent; on the other hand, for the bottom corner, the gate dielectric layer at least comprises a first area 132, and the lateral surface of the first area is not contacted with the first electric field shielding structure, so that the formation of a channel is not influenced, the current circulation is facilitated, and a second electric field shielding structure 160 is arranged below the first area, the bottom of the gate dielectric layer is protected through the second electric field shielding structure 160, the effect of shielding the bottom electric field of the gate dielectric layer and the influence on the on-resistance of the trench gate transistor are considered, and the structural arrangement of the trench gate transistor in the aspects of working stability and service life is improved more flexibly.

It should be noted that, the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench. No other gate trenches are included between the first electric field shielding structure and the gate trench and between the second electric field shielding structure and the gate trench.

Illustratively, the conductivity type of the first electric field shielding structure 150 and the second electric field shielding structure 160 are P-type. The ion doping concentrations of the first electric field shielding structure 150 and the second electric field shielding structure 160 are approximately equal; in a practical process, the ion doping concentrations of both may be in the same order of magnitude. The first electric field shielding structure 150 may also be referred to as a P pilar structure; the second electric field shielding structure 160 may also be referred to as a P shield structure.

Illustratively, the gate dielectric layer 130 may further include a second region, and a portion of the outer sidewall 133 located in the second region is adjacent to the first electric field shielding structure 150. And the second electric field shielding structure 160 may or may not be provided under the second region, so that the electric field concentration problem is solved in the second region mainly by means of the first electric field shielding structure 150. Specifically, in an alternative embodiment, the projection of the portion of the outer bottom wall 134 located in the second region on the plane of the lower surface of the semiconductor material layer falls within the range of the projection of the second electric field shielding structure 160 on the plane of the lower surface of the semiconductor material layer; in another alternative embodiment, the projection of the portion of the outer bottom wall 134 located in the second region onto the plane of the lower surface of the semiconductor material layer does not fall within the range of the projection of the second electric field shielding structure 160 onto the plane of the lower surface of the semiconductor material layer. Furthermore, in consideration of the comprehensive factors such as the electric field shielding effect and the complexity of the process flow, in a specific example, the first electric field shielding structure 150 may be partially disposed under the second region; in other words, the projection of the portion of the outer bottom wall 134 located in the second region on the plane in which the lower surface of the semiconductor material layer is located falls within the range of the projection of the first electric field shielding structure 150 on the plane in which the lower surface of the semiconductor material layer is located.

In some embodiments, the second electric field shielding structure 160 is electrically connected to the first electric field shielding structure 150. Illustratively, after the conductive connection, the second electric field shielding structure 160 is integrally connected with the first electric field shielding structure 150, so as to more effectively attract the electric field, so as to reduce or shield the electric field concentrated at the bottom corner 131 of the gate dielectric layer 130.

In some embodiments, the second electric field shielding structure 160 and the first electric field shielding structure 150 are both connected to ground potential. Thus, the shielding effect can be better exerted, so that the effect of reducing the electric field intensity at the corner 131 at the bottom of the gate dielectric layer 130 can be better realized. Illustratively, the connection to the ground potential may be to the source contact region 180, and since the source contact region 180 is typically grounded, the second electric field shielding structure 160 and the first electric field shielding structure 150 may be connected to the ground potential through the source contact region 180. It should be noted that connection to ground potential is broadly referred to herein as being connected to a low potential in the device.

In some embodiments, as shown in fig. 7 and 8, the portion of the outer bottom wall 134 that is located within the first region 132 is completely surrounded by the second electric field shielding structure 160. The second electric field shielding structure 160 is in direct contact with and completely covers the portion of the outer bottom wall 134 located in the first region 132, so that the problem of electric field concentration at the bottom corner 131 of the gate dielectric layer 130 is better alleviated. While on-current during operation of the trench gate transistor may flow through the layer of semiconductor material 110 adjacent to the first region 132 without affecting operation of the trench gate transistor.

In some embodiments, as shown in fig. 1 and 3, the trench gate transistor further includes: a body region 170 and a source contact region 180; the body region 170 and the source contact region 180 are adjacent to the gate trench 120, the source contact region 180 extending from the upper surface of the semiconductor material layer 110 to the interior of the semiconductor material layer 110, the body region 170 being located below the source contact region 180; illustratively, the body region 170, also referred to as a base region, is a body layer that forms a channel, the body region 170 being of opposite conductivity type to the semiconductor material layer 110. Illustratively, the body region 170 is a P-type doped region (shown as P body). The source contact region 180 is of the same conductivity type as the semiconductor material layer 110. Illustratively, the source contact region 180 is an n+ doped region (shown as n+.

As shown in fig. 4, the outer sidewall of the gate dielectric layer 130 includes a first portion 1331 and a second portion 1332; wherein the projections of the first portion 1331 and the first electric field shielding structure 150 on the plane of the side wall of the gate trench coincide, and the second portion 1332 adjoins the body region 170 and the source contact region 180. Illustratively, the bottom corner 131 of the second portion 1332 is located within the first region 132 and the bottom corner 131 of the first portion 1331 is located within the second region.

In some embodiments, as shown in fig. 1 and 2, the trench gate transistor further includes:

a first electric field shielding structure contact region 190, the first electric field shielding structure contact region 190 being located above the first electric field shielding structure 150 in the second direction. The first electric field shielding structure contact region 190 is electrically connected to both the first electric field shielding structure 150 and the source contact region 180, and both the first electric field shielding structure 150 and the second electric field shielding structure 160 are electrically connected to the source contact region 180 through the first electric field shielding structure contact region 190, thereby being connected to a ground potential. The first electric field shielding structure contact region 190 is opposite to the conductivity type of the semiconductor material layer 110, is the same as the conductivity type of the first electric field shielding structure 150 and the second electric field shielding structure 160, but has a higher doping concentration than the first electric field shielding structure 150. Illustratively, the first electric field shield structure contact region 190 is a p+ doped region; and is formed by heavily doping the top of the first electric field shielding structure 150.

In some embodiments, as shown in fig. 1 and 2, the trench gate transistor further includes: a metal wiring layer 200. The metal wiring layer 200 is used to realize conductive connection of the gate 140 and the source contact region 180 with an external circuit.

Example two

The first embodiment is based on the first embodiment, and further improvements are made on the structures such as the first electric field shielding structure and the second electric field shielding structure, so that implementation is more flexible, and only differences from the first embodiment are described below:

in this embodiment, as shown in fig. 9 and 10, the second electric field shielding structure 160 includes a first second electric field shielding unit 161 and a second electric field shielding unit 162, and a first gap exists between the first second electric field shielding unit 161 and the second electric field shielding unit 162. Illustratively, the second electric field shielding structure 160 does not completely cover the bottom of the gate dielectric layer 130 in the third direction, but is divided into two parts, one part is a first second electric field shielding unit 161, the other part is a second electric field shielding unit 162, and a first gap exists between the two units, so that not only can the electric field be shielded, but also the influence on the on-resistance of the trench gate transistor can be reduced. Alternatively, the first gap may be located in the middle of the second electric field shielding structure 160 in the third direction, so that the electric field at the bottom of the gate dielectric layer 130 is more uniform.

In some embodiments, as shown in fig. 9 and 10, the first electric field shielding structure 150 may include a first electric field shielding unit 151 and a second first electric field shielding unit 152, and a second gap exists between the first electric field shielding unit 151 and the second first electric field shielding unit 152, so that an electric field can be shielded and an effect on an on-resistance of the trench gate transistor can be reduced.

The distance of the first gap is smaller than the distance of the second gap. The distance of the first gap is denoted as L1 in the figure and the distance of the second gap is denoted as L2 in the figure, i.e. L1 < L2. Since the first electric field shielding structure 150 is generally distributed on two sides (not necessarily contacting) of the gate dielectric layer 130, the electric field distribution on the side surface of the gate trench 120 is mainly changed; the second electric field shielding structure 160 is generally distributed below (not necessarily contacting) the gate dielectric layer 130, and mainly directly protects the bottom of the gate dielectric layer 130. Therefore, the provision of L1 < L2 is more advantageous for the second electric field shielding structure 160 to function.

In some embodiments, as shown in fig. 9 and 10, the second electric field shielding structure 160 may have an overlapping region with the first electric field shielding structure 150, and the ion doping concentration of the overlapping region is greater than that of either of the second electric field shielding structure 160 and the first electric field shielding structure 150. In this way, the second electric field shielding structure 160 may be brought into good conductive contact with the first electric field shielding structure 150, so that both may be connected to the source contact region 180, i.e. to the ground potential, with good electrical conduction.

Example III

In this embodiment, on the basis of the second embodiment, the first electric field shielding structure, the second electric field shielding structure and other structures are further improved, so that the implementation is more flexible, and only the differences from the second embodiment are described below:

in this embodiment, as shown in fig. 11 and 12, the second electric field shielding structure 160 and the first electric field shielding structure 150 may not necessarily have an overlapping area, but may be connected by abutting the two boundaries. In this manner, the ion doping concentrations at the respective positions of the first and second electric

field shielding structures

150 and 160 are more uniform; however, the requirement of the manufacturing process is more stringent in this embodiment, and if the boundaries of the first electric field shielding structure 150 and the second electric field shielding structure 160 are not connected, there is a possibility that the second electric field shielding structure 160 cannot be connected to the ground potential.

It should be understood that although the present embodiment is illustrated based on the second embodiment, the absence of an overlap region between the second electric field shielding structure 160 and the first electric field shielding structure 150 is obviously applicable to other embodiments including the first embodiment.

Example IV

In this embodiment, as shown in fig. 13-16, a third gap exists between the second electric field shielding structure 160 and the outer bottom wall of the gate dielectric layer 130. Thus, it is an alternative embodiment to shield the electric field and reduce the effect on the on-resistance of the trench gate transistor. The distance of the third gap is denoted L3 in the figures.

It should be understood that, although the present embodiment is illustrated based on the first embodiment, the arrangement in which the third gap exists between the second electric field shielding structure 160 and the outer bottom wall of the gate dielectric layer 130 is obviously applicable to other embodiments.

Example five

The fourth embodiment is based on the fourth embodiment, and further improvements are made on the structures such as the first electric field shielding structure and the second electric field shielding structure, so that implementation is more flexible, and only differences from the fourth embodiment are described below:

in this embodiment, as shown in fig. 17 to 20, a fourth gap exists between the first electric field shielding structure 150 and the outer sidewall of the gate dielectric layer 130; thus, it is an alternative embodiment to shield the electric field and reduce the effect on the on-resistance of the trench gate transistor. The distance of the fourth gap is denoted L4 in the figures.

As shown in fig. 19 and 20, the second electric field shielding structure 160 includes a main shielding region 163 and an auxiliary shielding region 164, the main shielding region 163 is located directly under the gate dielectric layer 130, and the auxiliary shielding region 164 passes through the fourth gap to connect the main shielding region 163 and the first electric field shielding structure 150. Here, the auxiliary shielding region 164 is mainly used to electrically connect the main shielding region 163 to the first electric field shielding structure 150, so that the second electric field shielding structure 160 as a whole can be connected to the ground potential.

Further, the length of the auxiliary shielding region 164 in the third direction is smaller than the length of the main shielding region 163 in the third direction. The auxiliary shielding region 164 mainly plays a role of connecting the main shielding region 163 and the first electric field shielding structure 150, and reducing the length of the auxiliary shielding region 164 in the third direction is advantageous in reducing occupation of the current conducting channel, thereby being advantageous in reducing influence on the on-resistance of the trench gate transistor.

It should be understood that, although the present embodiment is illustrated based on the fourth embodiment, the arrangement in which the fourth gap exists between the first electric field shielding structure 150 and the outer sidewall of the gate dielectric layer 130 is obviously applicable to other embodiments. For example, a fourth gap exists between the first electric field shielding structure 150 and the outer sidewall of the gate dielectric layer 130, but a third gap does not exist between the second electric field shielding structure 160 and the outer sidewall of the gate dielectric layer 130, and as in the first embodiment, the second electric field shielding structure 160 is in direct contact with the outer sidewall of the gate dielectric layer 130.

Example six

The present embodiment is based on the second embodiment and the fifth embodiment, and the first electric field shielding structure, the second electric field shielding structure, and other structures are further improved, so that the implementation is more flexible, and only the differences from the fifth embodiment are described below:

in this embodiment, as shown in fig. 21, a fourth gap exists between the first electric field shielding structure 150 and the outer sidewall of the gate dielectric layer 130, and the second electric field shielding structure 160 includes a first second electric field shielding unit 161 and a second electric field shielding unit 162 that are separated from each other, and each second electric field shielding unit includes a respective main shielding region and auxiliary shielding region. For example, the first and second electric field shielding units 161 include a first main shielding region 1613 and a first auxiliary shielding region 1614; the second electric field shielding unit 162 includes a second main shielding region 1623 and a second auxiliary shielding region 1624. In this way, the on-resistance can be further reduced. Regarding the fourth gap, the main and auxiliary shielding regions, the first and second electric

field shielding units

161 and 162, reference may be made to the above-described embodiments, and no further description is given here.

Example seven

In this embodiment, on the basis of the sixth embodiment, the structures of the first electric field shielding structure, the second electric field shielding structure, and the like are further improved, so that the implementation is more flexible, and only the differences from the sixth embodiment are described below:

In this embodiment, as shown in fig. 22, for each main shielding region, it is possible to connect with the first electric field shielding structure 150 through only one auxiliary shielding region. For example, the first main shielding region 1613 is connected to a portion of the upper left corner of the first electric field shielding structure 150 through a first auxiliary shielding region 1614 located at the left side thereof; the second main shielding region 1623 is connected to a lower right corner portion of the first electric field shielding structure 150 through a second auxiliary shielding region 1624 located on the right side thereof; here, left, right, up, and down are all described in the orientation in the drawings. Thus, the occupation of the current conduction channel can be further reduced, and the influence on the on-resistance of the trench gate transistor is reduced.

Further, for two adjacent electric field shielding units (for example, the first and second electric

field shielding units

161 and 162 in the drawing), the auxiliary shielding regions are disposed on different sides of the main shielding region, respectively, and if the first auxiliary shielding region 1614 is disposed on one side (specifically, the left side in the drawing) of the first main shielding region 1613, the second auxiliary shielding region 1624 is disposed on the other side (specifically, the right side in the drawing) of the second main shielding region 1623.

Example eight

The embodiment of the present application also provides a method for preparing a trench gate transistor, which may be used to prepare the trench gate transistor provided in the foregoing embodiment, and in combination with fig. 23 to fig. 28, the method includes:

Step 201: a substrate 100 is provided, and a first epitaxial semiconductor material layer is formed on the substrate 100, see fig. 24. The first epitaxial semiconductor material layer will subsequently be formed as part of the semiconductor material layer 110, and reference numeral 110 in fig. 24 may be referred to;

step 202: performing ion implantation on the upper surface of the first epitaxial semiconductor material layer to form a second electric field shielding structure 160, see fig. 25;

step 203: forming a second epitaxial semiconductor material layer on the first epitaxial semiconductor material layer;

step 204: performing ion implantation on the upper surface of the second epitaxial semiconductor material layer to form a first electric field shielding structure 150, see fig. 26;

step 205: forming a gate trench 120 extending from an upper surface of the second epitaxial semiconductor material layer to an inside of the second epitaxial semiconductor material layer, and sequentially forming a gate dielectric layer 130 and a gate 140 in the gate trench 120, see fig. 27; the projections of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the sidewalls of the gate trench are located at least partially coincide, and the projections of the second electric field shielding structure 160 and the gate dielectric layer 130 on the plane where the lower surface of the semiconductor material layer is located at least partially coincide. The first electric field shielding structure 150 and the second electric field shielding structure 160 are both electric field shielding structures corresponding to the gate trench.

Illustratively, referring to fig. 25, in step 202, the first epitaxial semiconductor material layer is part of the semiconductor material layer 110 in the trench-gate transistor embodiment described above, i.e., the semiconductor material layer 110 is grown in two steps. In this way, the second electric field shielding structure 160 is formed by ion implantation from the upper surface of the first epitaxial semiconductor material layer, and the implantation depth is relatively shallow. Therefore, the ion implantation requires less energy and less time, the operation time of the ion implantation machine can be greatly reduced, and the production efficiency is high; and, it is more convenient to control the formation position of the second electric field shielding structure 160. In some embodiments, the layer of semiconductor material 110 comprises an epitaxial layer of silicon carbide. Further, the trench gate transistor is a silicon carbide based trench gate transistor. Illustratively, the second electric field shielding structure 160 is formed below the gate dielectric layer 130. This serves to shield the electric field and reduce the electric field strength at the corners 131 at the bottom of the gate dielectric layer 130. Illustratively, in the present embodiment, the conductivity type of the semiconductor material layer 110 may be N-type, the conductivity type of the second electric field shielding structure 160 may be P-type, and the implanted ions may be at least one P-type ion of boron, indium, gallium, etc.

Illustratively, in step 203, the second epitaxial semiconductor material layer is continuously grown on the basis of the second electric field shielding structure 160, and the semiconductor material layer 110 in the above embodiment is formed by adding the second epitaxial semiconductor material layer to the first epitaxial semiconductor material layer.

Illustratively, referring to fig. 26, in step 204, the first electric field shielding structure 150 is formed at a position corresponding to a position where the gate dielectric layer 130 is formed, for example, projections of the first electric field shielding structure 150 and the gate dielectric layer 130 on a plane where sidewalls of the gate trench are located at least partially overlap. In the eighth embodiment shown in fig. 26, specifically, the first electric field shielding structure 150 may be disposed in a partial area of the gate dielectric layer 130 at two sides in the third direction. The extending direction of the first electric field shielding structure 150 may be perpendicular to the extending direction of the gate dielectric layer 130. This may act to attract the electric field and reduce the strength of the electric field at the corners of the bottom of the gate dielectric layer 130.

Illustratively, referring to fig. 27, in step 205, the gate trench 120 may be formed by a photolithography process. Specifically, a mask material is deposited on the semiconductor material layer 110, and then a preset formation position of the gate trench 120 is defined in the mask material through photolithography and etching processes, so as to form a patterned mask layer. This process is well known to those skilled in the art and will not be described in detail here. Next, the semiconductor material layer 110 is etched using the patterned mask layer as a mask until the gate trench 120 is formed. In this embodiment, the gate trench 120 may extend along the third direction.

In some embodiments, after ion implantation is performed on the upper surface of the second epitaxial semiconductor material layer to form the first electric field shielding structure 150, the method further includes: a body region 170 and a source contact region 180 are formed by ion implantation, the body region 170 and the source contact region 180 being contiguous with the gate trench 120, the source contact region 180 extending from an upper surface of the layer of semiconductor material 110 to an interior of the layer of semiconductor material 110, the body region 170 being located below the source contact region 180. The body region 170 is of the opposite conductivity type to the layer of semiconductor material 110, and the source contact region 180 is of the same conductivity type as the layer of semiconductor material 110. The doping concentration of the source contact region 180 is greater than the semiconductor material layer 110.

Illustratively, the formation of the body region 170 and the source contact region 180 may be preceded by the formation of the gate trench 120, such that a mask pattern of a photolithography process is simpler. It will be appreciated that the formation of the body region 170 and the source contact region 180 may also be after the formation of the gate trench 120.

Illustratively, the forming of the body region 170 and the source contact region 180 may include: the body region 170 is formed by a first ion implantation and the source contact region 180 is formed by a second ion implantation on the body region 170, the conductivity type of the second ion implantation being opposite to the conductivity type of the first ion implantation.

In some embodiments, after ion implantation is performed on the upper surface of the second epitaxial semiconductor material layer to form the first electric field shielding structure 150, the method further includes: a first electric field shielding structure contact region 190 is formed by ion implantation, the first electric field shielding structure contact region 190 being located above the first electric field shielding structure 150 in the second direction. The first electric field shielding structure contact region 190 is electrically connected to both the first electric field shielding structure 150 and the source contact region 180, and both the first electric field shielding structure 150 and the second electric field shielding structure 160 are electrically connected to the source via the first electric field shielding structure contact region 190. The first electric field shielding structure contact region 190 is opposite to the conductivity type of the semiconductor material, is the same conductivity type as the first electric field shielding structure 150 and the second electric field shielding structure 160, but has a doping concentration greater than the first electric field shielding structure 150.

In some embodiments, after forming gate dielectric layer 130 and gate 140, referring to fig. 28, the method further comprises: the metal wiring layer 200 is formed.

Example nine

The embodiment of the present application further provides a method for preparing a trench gate transistor, which may be used to prepare the trench gate transistor described in the foregoing embodiment, and in conjunction with fig. 29 to fig. 34, the method includes:

step 301: providing a substrate 100, forming a semiconductor material layer 110 on the substrate 100, see fig. 30;

step 302: ion implantation is performed on the upper surface of the semiconductor material layer 110 to form a first electric field shielding structure 150, see fig. 31;

step 303: forming a gate trench 120 extending from an upper surface of the semiconductor material layer 110 to an inside of the semiconductor material layer 110;

step 304: ion implantation is performed at the bottom of the gate trench 120 to form a second electric field shielding structure 160;

step 305: sequentially forming a gate dielectric layer 130 and a gate 140 in the gate trench 120, see fig. 33; wherein, the projections of the first electric field shielding structure 150 and the gate dielectric layer 130 on the plane where the side wall of the gate trench is located are at least partially overlapped.

As can be seen from the above steps, the main difference between the present embodiment and the eighth embodiment is that the semiconductor material layer 110 is formed by one epitaxial growth, and the eighth embodiment is formed by two epitaxial growth, so that the forming order of the first electric field shielding structure 150 and the second electric field shielding structure 160 is different, only the differences will be described below, and the same parts will not be repeated.

Illustratively, in step 302 described above, the first electric field shielding structure 150 is formed, at which time the second electric field shielding structure 160 is not yet formed.

Illustratively, in the step 303, the gate trench 120 is formed, and at this time, the second electric field shielding structure 160 is not formed yet, without considering the alignment problem between the slotting position of the gate trench 120 and the forming position of the second electric field shielding structure 160. Then, since the gate trench 120 exposes not only the semiconductor material layer 110 through the bottom wall but also the semiconductor material layer 110 on the sidewalls when the second electric field shielding structure 160 is formed; in this way, the sidewall of the gate trench 120 may be doped during ion implantation, which may affect the performance of the channel, and this problem may be well avoided in embodiment eight.

It should be noted that, the trench gate transistor embodiment and the trench gate transistor preparation method embodiment provided in the present application belong to the same concept; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict. However, it should be further described that the trench gate transistor provided in the embodiments of the present application may have various technical feature combinations that solve the technical problems to be solved in the present application; therefore, the trench gate transistor provided in the embodiments of the present application may not be limited by the method for manufacturing a trench gate transistor provided in the embodiments of the present application, and any trench gate transistor manufactured by the method for manufacturing a trench gate transistor capable of forming the trench gate transistor structure provided in the embodiments of the present application is within the scope of protection of the present application.

It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the individual features of the above embodiments can also be combined arbitrarily to form further embodiments of the invention which may not be explicitly described. Therefore, the above examples merely represent several embodiments of the present invention and do not limit the scope of protection of the patent of the present invention.

Claims

1. A trench-gate transistor, comprising:

a layer of semiconductor material;

a first electric field shielding structure and a second electric field shielding structure located outside the gate trench; the first electric field shielding structure is partially arranged below the grid groove and partially distributed on two sides of the grid groove; the second electric field shielding structure is at least partially arranged below the gate dielectric layer; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench; the second electric field shielding structure and the first electric field shielding structure have an overlapping area, and the second electric field shielding structure and the first electric field shielding structure are in conductive connection through the overlapping area;

The bottom corner of the gate dielectric layer comprises a first region, the bottom corner is the intersection of the outer side wall and the outer bottom wall of the gate dielectric layer, the part of the outer side wall in the first region is not contacted with the first electric field shielding structure, and the second electric field shielding structure is arranged below the part of the outer bottom wall in the first region;

the trench gate transistor further includes: the first electric field shielding structure comprises a body region, a source electrode contact region and a first electric field shielding structure contact region; the source contact region and the first electric field shielding structure contact region respectively extend from the upper surface of the semiconductor material layer to the inside of the semiconductor material layer; the source contact region is located above the body region; the first electric field shielding structure contact area is positioned above the part of the first electric field shielding structure distributed on two sides of the grid electrode groove; the outer side wall of the gate dielectric layer comprises a first part and a second part; wherein the first portion adjoins the first electric field shielding structure and the first electric field shielding structure contact region, and the second portion adjoins the body region and the source contact region.

2. The trench-gate transistor of claim 1, wherein the second electric field shielding structure and the first electric field shielding structure are both connected to ground potential.

3. The trench-gate transistor of claim 1, wherein a portion of the outer bottom wall that is located within the first region is completely covered by the second electric field shielding structure.

4. The trench-gate transistor of claim 1, wherein the second electric field shielding structure comprises a first second electric field shielding element and a second electric field shielding element, the first second electric field shielding element and the second electric field shielding element having a first gap therebetween.

5. The trench-gate transistor of claim 4, wherein the first electric field shielding structure comprises a first electric field shielding element and a second first electric field shielding element, a second gap exists between the first electric field shielding element and the second first electric field shielding element, and a distance of the first gap is smaller than a distance of the second gap.

6. The trench-gate transistor of claim 1, wherein the overlap region has an ion doping concentration that is greater than an ion doping concentration of either of the second electric field shielding structure and the first electric field shielding structure.

7. The trench-gate transistor of claim 1, wherein a third gap exists between the second electric field shielding structure and an outer bottom wall of the gate dielectric layer.

8. A method of fabricating a trench-gate transistor, the method comprising:

ion implantation is carried out on the upper surface of the second epitaxial semiconductor material layer, so that a first electric field shielding structure is formed; the second electric field shielding structure and the first electric field shielding structure have an overlapping area, and the second electric field shielding structure and the first electric field shielding structure are in conductive connection through the overlapping area;

forming a gate trench extending from the upper surface of the second epitaxial semiconductor material layer to the interior of the second epitaxial semiconductor material layer, and sequentially forming a gate dielectric layer and a gate in the gate trench; the first electric field shielding structure is partially arranged below the grid groove and partially distributed on two sides of the grid groove; the second electric field shielding structure is at least partially arranged below the gate dielectric layer; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench;

Forming a body region and a source contact region; the source contact region extends from the upper surface of the second epitaxial semiconductor material layer to the inside, and the body region is located below the source contact region;

forming a first electric field shielding structure contact region which extends from the upper surface of the second epitaxial semiconductor material layer to the inside and is positioned above the parts of the first electric field shielding structure distributed on two sides of the grid groove;

the outer side wall of the gate dielectric layer comprises a first part and a second part; wherein the first portion adjoins the first electric field shielding structure and the first electric field shielding structure contact region, and the second portion adjoins the body region and the source contact region.

9. A method of fabricating a trench-gate transistor, the method comprising:

forming a body region and a source contact region; the source contact region extends from the upper surface of the semiconductor material layer to the inside, and the body region is positioned below the source contact region;

Forming a first electric field shielding structure contact region formed by heavily doping a top portion of the first electric field shielding structure on an upper surface of the semiconductor material layer;

forming a gate trench extending from an upper surface of the semiconductor material layer to an interior of the semiconductor material layer; the first electric field shielding structure is partially arranged below the grid groove and partially distributed on two sides of the grid groove; the first electric field shielding structure contact area is positioned above the part of the first electric field shielding structure distributed on two sides of the grid electrode groove;

ion implantation is carried out at the bottom of the grid electrode groove to form a second electric field shielding structure positioned below the bottom of the grid electrode groove; the second electric field shielding structure and the first electric field shielding structure have an overlapping area, and the second electric field shielding structure and the first electric field shielding structure are in conductive connection through the overlapping area;

forming a gate dielectric layer and a gate electrode in the gate trench in sequence; the outer side wall of the gate dielectric layer comprises a first part and a second part; the first portion is adjacent to the first electric field shielding structure and the first electric field shielding structure contact region, and the second portion is adjacent to the body region and the source contact region; the first electric field shielding structure and the second electric field shielding structure are both electric field shielding structures corresponding to the gate trench.