CN115513298A - Trench transistor and method of forming the same - Google Patents
Trench transistor and method of forming the same Download PDFInfo
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- CN115513298A CN115513298A CN202211408647.9A CN202211408647A CN115513298A CN 115513298 A CN115513298 A CN 115513298A CN 202211408647 A CN202211408647 A CN 202211408647A CN 115513298 A CN115513298 A CN 115513298A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The application discloses a trench transistor and a method of forming the same, the trench transistor comprising: a substrate; the long strip-shaped grid structure is positioned in the substrate; the grid structure comprises a plurality of grid structures and a plurality of shielding regions, wherein the grid structures are arranged on the side of the grid structures, the shielding regions are arranged on the side of the grid structures, and the shielding regions are distributed along the length direction of the grid. The reliability of the trench transistor is improved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a trench type transistor and a forming method thereof.
Background
A trench MOS (Trench MOS) transistor is taken as a novel vertical structure device, belongs to a high-cell-density device, and has low conduction and switching loss and high switching speed. Meanwhile, as the channel of the groove type MOS is vertical, the channel density can be further improved, and the size of the chip is reduced.
Because the grid structure of the trench transistor is positioned in the trench in the substrate, extremely high electric field intensity is gathered at the bottom and the corner when the trench transistor works reversely, the grid dielectric layer is degraded when the trench transistor works under a high electric field for a long time, and the reliability of a device is reduced.
How to further improve the reliability of the device is a problem to be solved urgently at present.
Disclosure of Invention
In view of the above, the present application provides a trench transistor and a method for forming the same to solve the reliability problem of the conventional trench transistor.
The application provides a trench transistor, including: a substrate; the long strip-shaped grid structure is positioned in the substrate; the grid structure comprises a plurality of strip-shaped grid structures, a plurality of shielding regions and a plurality of shielding parts, wherein the plurality of shielding regions are positioned on at least one side of each strip-shaped grid structure and distributed along the length direction of each grid structure, and the shielding regions wrap corners of the connecting part of the side walls of the grid structures on the side where the shielding regions are positioned and the bottoms of the grid structures.
Optionally, the shielding region further covers a portion of the sidewall of the gate structure.
Optionally, all of the shielding regions are located on the same side of the corresponding gate structures.
Optionally, the shielding regions are distributed in a row in a direction perpendicular to the length direction of the gate structure.
Optionally, the shielding regions corresponding to adjacent gate structures are staggered from each other in the row direction.
Optionally, the shielding regions corresponding to adjacent gate structures are aligned in the row direction.
Optionally, the width of the shielding region between adjacent gate structures occupies 1/3 to 2/3 of the distance between adjacent gate structures.
Optionally, in the length direction of the gate structure, a distance between adjacent shielding regions is greater than or equal to a width of the shielding region.
Optionally, the substrate further includes: a base layer; the drift layer and the base region layer are sequentially stacked from the surface of the base layer to the surface of the substrate; source regions located at two sides of the gate structure in the base region layer; the bottom of the gate structure and the shielding region are positioned in the drift layer, and the shielding region is positioned between a source region on one side of the gate structure and the gate structure; the doping type of the shielding region is the same as that of the base region layer, and the doping type of the shielding region is opposite to that of the drift layer.
Optionally, the doping concentration of the shielding region is greater than the doping concentration of the base region layer.
Optionally, the method further includes: a source connection layer on the substrate, the source connection layer electrically connecting the source regions.
Optionally, the source connection layer is further electrically connected to the shielding region.
Optionally, the thickness of the shielding region at the bottom of the gate structure is 1-5um.
Optionally, the gate structure is formed in a trench in the substrate, and includes a gate dielectric layer covering an inner wall of the trench, and a gate located on a surface of the gate dielectric layer and filling the trench.
The present application also provides a method for forming a trench transistor as described in any of the above, comprising: providing a substrate; forming a plurality of discrete shielding regions in the substrate; and forming a strip-shaped gate structure in the substrate, wherein the shielding region is positioned on at least one side of the gate structure, the shielding region is distributed along the length direction of the gate structure, and the shielding region wraps the corner of the joint of the side wall of the gate structure on the side where the shielding region is positioned and the bottom of the gate structure.
Optionally, the forming method of the trench transistor further includes: forming source regions in the base region layers on two sides of the grid structure, wherein the shielding region is positioned between the source region on one side of the grid structure and the grid structure; and forming a source electrode connecting layer on the surface of the substrate, wherein the source electrode connecting layer is electrically connected with the source electrode region and the shielding region.
According to the trench transistor, the discrete shielding region is arranged on one side of the grid structure of the strip-shaped unit cell, and the long-term reliability of the grid dielectric layer is improved by reducing the electric field intensity near the grid dielectric layer at the bottom of the grid structure. And the shielding regions are distributed discretely, so that the occupied channel region is less, and the reliability of the gate dielectric layer is improved while the higher channel density and the higher conduction capability can be obtained.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a trench transistor according to an embodiment of the present application;
FIG. 2 is a schematic top view of a trench transistor according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a trench transistor according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a trench transistor in an embodiment of the present application;
FIG. 5 is a schematic diagram of a trench transistor according to another embodiment of the present application;
FIG. 6 is a schematic top view of a trench transistor in another embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a trench transistor in another embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a trench transistor in another embodiment of the present application;
FIGS. 9a and 9b are schematic cross-sectional views of a trench transistor in another embodiment of the present application;
fig. 10a and 10b are schematic structural diagrams of a trench transistor according to another embodiment of the present application.
Detailed Description
As described in the background art, the reliability of the existing trench transistor is yet to be further improved.
The gate dielectric layer is degraded due to the high electric field intensity at the bottom and the corners of the gate structure. The reliability of the device can be improved by reducing the electric field at the periphery of the gate dielectric layer of the gate structure.
The inventors propose that a shield layer may be introduced within the body region. However, the shield layer may occupy a portion of the body region location, resulting in a reduced channel density.
In view of the above, the inventors propose a new trench transistor and a method for forming the same, which introduces a discrete shielding structure to maintain a higher channel density on the basis of improving the reliability of the device, so as to ensure the current conducting capability of the device.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 1 to fig. 4 are schematic structural diagrams of a trench transistor according to an embodiment of the invention. Fig. 1 is a partial perspective view, fig. 2 is a top view, fig. 3 is a cross-sectional view along a cut line AA 'in fig. 2, and fig. 4 is a cross-sectional view along a cut line BB' in fig. 2.
In this embodiment, the trench transistor includes a substrate 100; an elongated gate structure 110 located within the substrate 100; the shielding regions 120 are located on at least one side of the strip-shaped gate structure 110 and distributed along the length direction of the gate, and the shielding regions 120 wrap corners of the connection between the sidewalls of the gate structure 110 and the bottom of the gate structure 110.
In this embodiment, the substrate 100 includes a base layer 101 and an epitaxial layer 102 formed on a surface of the base layer 101.
In this embodiment, the base layer 101 is a SiC layer, and the epitaxial layer 102 is a SiC epitaxial layer.
In other embodiments, the material of the base layer 101 may also be a semiconductor material such as single crystal Si, single crystal Ge, single crystal GeSi, gaN, etc., and the material of the epitaxial layer 102 may be an epitaxial semiconductor layer of other materials, such as a Si epitaxial layer, a Ge epitaxial layer, a GeSi epitaxial layer, a GaN epitaxial layer, etc. Preferably, the base layer 101 and the epitaxial layer 102 are made of the same material, which is beneficial to forming the high-quality epitaxial layer 102, reducing defects in the epitaxial layer 102, and improving the performance of the subsequently formed trench transistor. The base layer 101 is typically heavily doped to act as a drain region for the trench transistor.
In the epitaxial layer 102, a doped region, such as an N-type or P-type doped well, may be formed according to the requirements of the device to be formed. The doped region may be formed by ion implantation, or may be formed by an in-situ doping process during an epitaxial deposition process for forming the epitaxial layer 102. In this embodiment, a doped base layer 1022 is formed at a certain depth on the surface of the epitaxial layer 102, and a source region 1023 is formed in the base layer 1022. The epitaxial layer 102 is located between the base layer 1022 and the base layer 101 and serves as a drift layer 1021.
The gate structure 110 is formed in a trench in the substrate 100, and includes a gate dielectric layer 112 covering an inner wall of the trench, and a gate 111 located on a surface of the gate dielectric layer 112 and filling the trench. The gate dielectric layer 112 is made of a commonly used gate oxide material, such as silicon oxide, and may also be a high-K dielectric material, such as at least one of hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide, and may have a single-layer or multi-layer structure. The gate 111 is a conductive material, and may be a semiconductor conductive material, such as polysilicon, doped polysilicon, or the like; but also a metallic material such as tungsten, copper, aluminum, gold, silver, or the like.
The top view of the gate 111 is in a long shape to form a long-strip cellular structure. Several gates 111 are arranged in parallel, and the source regions 1023 are located at two sides of the gate 111 in the length direction.
In this embodiment, the bottom of the gate structure 110 is located in the drift layer 1021. The region of the base layer 1022 close to the gate dielectric layer 112 is a channel region of a transistor. The thickness of the gate dielectric layer 112 between the channel region and the gate 111 is small, so that the on-resistance of the channel can be reduced, and the performance of the device can be improved.
The shielding region 120 extends from the surface of the epitaxial layer 102 to the inside, the bottom of the shielding region is located in the drift layer 1021, the bottom of the shielding region 120 is lower than the bottom of the gate structure 110, and a part of the shielding region is located at the bottom of the gate structure 110 and at least wraps a corner of a connection between the sidewall of the gate structure 110 and the bottom of the gate structure 110. And a drift layer 1021 with a partial thickness is arranged between the shielding region 120 and the base layer 101. The thickness of the shielding region 120 at the bottom of the gate structure 110 is sufficient to ensure sufficient protection of the bottom of the gate structure 110. Preferably, in some embodiments, the shielding region 120 is 1-5um thick at the bottom of the gate structure 110.
In this embodiment, the shielding regions 120 are all located at the sidewalls of the same side of the corresponding gate structures 110; the individual screening regions are distributed in columns perpendicular to the length of the gate structure 110, i.e., aligned along the y-direction of the coordinate axis. In other embodiments, the shielding regions 120 may be distributed at both side wall positions of each gate structure 110.
The shielding region 120 is located between the source region 1023 on one side of the gate structure 110 and the gate structure 110, and covers a portion of the sidewall of the corresponding gate structure 110 and a corner where the sidewall connects with the bottom of the gate structure 110. In other embodiments, the shielding region 120 may further include the entire bottom of the gate structure 110, and the bottom corners of both sides. The shielding region 120 may be formed in the substrate 100 by ion implantation, and then the gate structure 110 is formed, for example, the substrate 100 is etched to form a trench, and then the gate structure 110 is formed in the trench, and a part of the trench region overlaps with the shielding region, so that the remaining shielding region is located at one side of the gate structure 110 and covers a sidewall and a part of the bottom of the gate structure.
The doping type of the shielding region 120 is the same as that of the base region layer 1022, and the doping concentration of the shielding region 120 is greater than that of the base region layer 1022. Preferably, the doping concentration of the shielding region 120 is 10 to 10 of the doping concentration of the base region layer 1022 3 And (4) doubling. The doping type of the shielding region 120 is opposite to that of the drift layer 1021, and a depletion region is formed between the shielding region and the drift layer, so that the electric field intensity near the gate dielectric layer 112 of the gate structure 110 is reduced, and the reliability of the gate dielectric layer 112 can be improved.
Since the shielding region 120 is located at a sidewall of the gate structure 110 and located between the gate structure 110 and the source region 1023, a certain channel region is occupied. However, since the shielding region 120 is a plurality of discrete structures, only a part of the channel region is occupied by the shielding region 120 at the side of the gate structure 110 where the shielding region 120 is formed, and most of the channel region can still be formed, so as to ensure that the trench transistor has sufficient channel density and sufficient current conducting capability.
In this embodiment, the trench transistor is an N-type transistor, the substrate layer 101 is an N-type heavily doped layer, the drift layer 1021 is an N-type doped layer, the base layer 1022 is a P-type doped layer, the source region 1023 is an N-type heavily doped layer, and the shielding region 120 is a P-type heavily doped layer.
In other embodiments, the trench transistor is a P-type transistor, the substrate layer 101 is a P-type heavily doped layer, the drift layer 1021 is a P-type doped layer, the base layer 1022 is an N-type doped layer, the source region 1023 is a P-type heavily doped layer, and the shielding region 120 is an N-type heavily doped layer.
The width D of the shielding region 120 between adjacent gate structures 110 occupies the space D between adjacent gate structures 110, which cannot be too large, so as to avoid affecting the channel region of the adjacent gate structures 110 on the side where the shielding region 120 is not formed. Preferably, the width D of the shielding region 120 between adjacent gate structures 110 occupies 1/3 to 2/3 of the distance D between adjacent gate structures 110.
The distance d 'between the shielding regions 120 in the same column may be adjusted according to the electric field intensity in the gate dielectric layer of the trench transistor to be formed, and the larger the distance d', the larger the electric field intensity in the gate dielectric layer, which affects the long-term reliability. On the premise of ensuring long-term reliability, d 'is as large as possible, and the larger d', the higher the channel region density is. The distance d' and the dimension of the shielding region 120 along the length direction of the gate structure 110 may be set according to the requirements on the reliability of the gate dielectric layer and the density of the channel region.
As shown in fig. 1 and fig. 2, in this embodiment, the shielding regions corresponding to the adjacent gate structures 110 are staggered from each other in the row direction, that is, the shielding regions corresponding to the adjacent gate structures 110 are staggered from each other in the x-axis direction. In the embodiment, the shielding regions corresponding to the gate structures 110 disposed at intervals are aligned in the x-axis direction (see fig. 2). In other embodiments, the shielding regions 120 corresponding to the gate structures 110 disposed at intervals may be staggered from each other in the x-axis direction.
Fig. 5 to 8 are schematic structural diagrams of a trench transistor according to another embodiment of the present invention, wherein fig. 5 is a schematic perspective view of the trench transistor in the embodiment, fig. 6 is a schematic top view of the trench transistor in the embodiment, fig. 7 is a schematic cross-sectional view along a cut line CC 'in fig. 6, and fig. 8 is a schematic cross-sectional view along a cut line DD' in fig. 6.
The difference from the embodiment shown in fig. 1 is that in this embodiment, the shielding regions 120 on one side of the adjacent gate structures 110 are aligned in the x-axis direction, so that the shielding regions 120 are distributed in an array in the y-direction and the x-direction.
Please refer to fig. 9a and 9b, which are schematic cross-sectional views along the cutting line EE' in fig. 6.
A triode structure is formed between two adjacent shielding regions 120 and the drift layer 1021 between the shielding regions. In this embodiment, the shielding region 120 is P-type heavily doped, and the drift layer 1021 is N-type doped to form a (P +) N (P +) structure, thereby generating a JFET effect. The dimension of the shielding regions 120 in the y-direction, and the distance between adjacent shielding regions 120, can be designed as desired. Preferably, in the y direction, the distance between adjacent shielding regions 120 is greater than or equal to the width of the shielding region 120 in the y direction.
Advantageously, referring to fig. 9a, when the transistor is turned on, the drain-source voltage VDS is small, the space charge region 201 generated at the edge of the shielding region 120 is narrow, and a conductive channel is left in the drift layer 1021 between adjacent shielding regions 120, as shown by the arrows in fig. 9b, which can increase the channel and current density.
Referring to fig. 9b, when the transistor is turned off, the drain-source voltage VDS is large, the space charge region 201 is wide, and a portion of the electric field lines E terminate in the space charge region 201, which can reduce the electric field strength in the gate dielectric layer 112, thereby improving the long-term reliability of the gate dielectric layer 112.
Fig. 10a and fig. 10b are schematic structural diagrams of a trench transistor according to another embodiment of the present application.
In the embodiment shown in fig. 10a and 10b, compared to the embodiment shown in fig. 6, the trench transistor further comprises: a source connection layer 200 on the substrate 100, the source connection layer 200 electrically connecting the source regions 1023. Fig. 10a and 10b correspond to the same cross-sectional views as the cross-sectional structure diagrams of fig. 7 and 8, respectively, and the same structural features are not repeated.
The source connecting layer 200 is isolated from the gate 111 by an interlayer dielectric layer 210. A patterned interlayer dielectric layer 210 is formed on the epitaxial layer 102, the interlayer dielectric layer 210 covers the region to be isolated, and the source region 1023 to be connected is exposed; a source connecting layer 200 covers the interlayer dielectric layer 210 and the exposed surface of the epitaxial layer 102, and the source connecting layer 200 may be formed by patterning a conductive material layer.
In other regions, a gate connection layer may be formed to electrically connect the gate electrode 111. The gate connection layer may be located at the same or different metal layer as the source connection layer 200. The gate connection layer is isolated from the source connection layer 200 by an interlayer dielectric layer.
In this embodiment, the source connection layer 200 is also electrically connected to the shielding region 120, so that the shielding region 120 and the source connection layer 200 have the same potential. In the operation process of the N-type or P-type trench transistor, the source connection layer 200 is connected to a low potential, for example, grounded, and the shielding region 120 is also connected to a low potential, so that more electric field lines can be terminated in the shielding region 120, and the electric field shielding effect on the gate dielectric layer 112 is better. In addition, in the high-frequency operating state, the shielding region 120 is not in a dynamic depletion state, which does not cause a decrease in switching speed and an increase in specific on-resistance, which is beneficial to device stability.
In the trench transistor, the discrete shielding region 120 is arranged on one side of the gate structure 110 of the elongated unit cell, and the long-term reliability of the gate dielectric layer 112 is improved by reducing the electric field intensity near the gate dielectric layer 112 at the bottom of the gate structure 110. Moreover, the shielding regions 120 are distributed discretely, and occupy less channel region, so that higher channel density and conduction capability can be obtained while the reliability of the gate dielectric layer 112 is improved.
The embodiment of the present application further provides a method for forming the trench transistor in the above embodiment. The forming method comprises the following steps: providing a substrate 100, forming a plurality of discrete screening regions 120 within the substrate 100; forming a strip-shaped gate structure 110 in the substrate 100, wherein the shielding region 120 is located on at least one side of the strip-shaped gate structure 110, the shielding region 120 is distributed along the gate length direction, and the shielding region 120 wraps the corner of the connection between the sidewall of the gate structure 110 on the side where the shielding region 120 is located and the bottom of the gate structure 110.
The substrate 100 includes a base layer 101 and an epitaxial layer 102 formed on a surface of the base layer 101. In this embodiment, the base layer 101 is a SiC layer, and the epitaxial layer 102 is a SiC epitaxial layer. In other embodiments, the substrate layer 101 and the epitaxial layer 102 may also adopt other semiconductor materials, as described in the foregoing embodiments.
In the epitaxial layer 102, according to the requirements of a device to be formed, a doped region, such as an N-type or P-type doped well, may also be formed by ion implantation, or may also be formed by an in-situ doping process in an epitaxial deposition process for forming the epitaxial layer 102. In this embodiment, a doped base layer 1022 with a certain depth is formed on the surface of the epitaxial layer 102, and a source region 1023 is formed in the base layer 1022. In other embodiments, after a gate structure is formed subsequently, ion implantation may be performed on the epitaxial layer 102 to form the base layer 1022 and the source region 1023.
Performing ion implantation on the epitaxial layer 102 to form shielding regions 120 in discrete distribution; then, etching the epitaxial layer 102 to form a long-strip-shaped groove in the epitaxial layer 102, then forming a gate dielectric layer 112 covering the inner wall of the groove, and forming a gate 111 filled in the groove. By properly positioning the shielding region 120 and the gate structure 110, the shielding region 120 is located on one side of the gate structure 110, covering the sidewall and the bottom corner region of the gate structure 110.
For the structural features of each part, reference may be made to the detailed description in the foregoing embodiments, which are not repeated herein.
In some embodiments, after forming the structures in the epitaxial layer 102, such as the gate structure 110 and the source region 1023, a source connection layer 200 (see fig. 10a and 10 b) may be further formed on the epitaxial layer 102, and the source connection layer 200 is electrically connected to the source region 1023. The source connecting layer 200 is isolated from the gate 111 by an interlayer dielectric layer 210, and specifically, after an insulating dielectric material layer is formed on the surface of the epitaxial layer 102, the insulating dielectric material layer is patterned according to the region to be isolated to form the interlayer dielectric layer 210; and forming a conductive material layer covering the interlayer dielectric layer 210 and the surface of the epitaxial layer 102, and patterning the conductive material layer to form the source connection layer 200. The conductive material layer may be made of metal.
In this embodiment, the interlayer dielectric layer 210 further exposes the shielding region 120, so that the source connection layer 200 simultaneously electrically connects the source region 1023 and the shielding region 120, thereby improving the electric field shielding effect of the shielding region 120.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (16)
1. A trench transistor, comprising:
a substrate;
the long strip-shaped grid structure is positioned in the substrate;
the grid structure comprises a plurality of strip-shaped grid structures, a plurality of shielding regions and a plurality of shielding parts, wherein the plurality of shielding regions are positioned on at least one side of each strip-shaped grid structure and distributed along the length direction of each grid structure, and the shielding regions wrap corners of the connecting part of the side walls of the grid structures on the side where the shielding regions are positioned and the bottoms of the grid structures.
2. The trench transistor of claim 1 wherein the shield region further covers a portion of the sidewalls of the gate structure.
3. A trench transistor according to claim 1 wherein all of the shield regions are located on the same side of the corresponding gate structure.
4. A trench transistor according to claim 1 wherein the shield regions are arranged in rows perpendicular to the length of the gate structure.
5. A trench transistor according to claim 1 wherein the shield regions corresponding to adjacent gate structures are offset from each other in the row direction.
6. The trench transistor of claim 1 wherein the corresponding shield regions of adjacent gate structures are aligned in the row direction.
7. The trench transistor of claim 1, wherein the width of the shielding region between adjacent gate structures occupies 1/3 to 2/3 of the space between adjacent gate structures.
8. The trench transistor of claim 1 wherein a distance between adjacent shield regions along a length of the gate structure is greater than or equal to a width of the shield regions.
9. The trench transistor of claim 1 wherein the substrate further comprises:
a base layer;
the drift layer and the base region layer are sequentially stacked from the surface of the base layer to the surface of the substrate;
source regions positioned at two sides of the gate structure in the base region layer;
the bottom of the gate structure and the shielding region are positioned in the drift layer, and the shielding region is positioned between a source region on one side of the gate structure and the gate structure;
the doping type of the shielding region is the same as that of the base region layer, and the doping type of the shielding region is opposite to that of the drift layer.
10. A trench transistor according to claim 9 wherein the shield region has a doping concentration greater than the doping concentration of the base layer.
11. The trench transistor of claim 9 further comprising: a source connection layer on the substrate, the source connection layer electrically connecting the source regions.
12. The trench transistor of claim 11 wherein the source connection layer is further electrically connected to the shield region.
13. The trench transistor of claim 1 wherein the shield region is 1-5um thick at the bottom of the gate structure.
14. The trench transistor of claim 1 wherein the gate structure is formed in a trench in the substrate and comprises a gate dielectric layer covering an inner wall of the trench and a gate on a surface of the gate dielectric layer and filling the trench.
15. A method of forming a trench transistor according to any one of claims 1 to 14, comprising:
providing a substrate;
forming a plurality of discrete shielding regions in the substrate;
and forming a strip-shaped gate structure in the substrate, wherein the shielding region is positioned on at least one side of the gate structure and is distributed along the length direction of the gate structure, and the shielding region wraps the corner of the joint of the side wall of the gate structure on the side where the shielding region is positioned and the bottom of the gate structure.
16. A method of forming a trench transistor according to claim 15, further comprising: forming source regions in the base region layers on two sides of the grid structure, wherein the shielding region is positioned between the source region on one side of the grid structure and the grid structure; and forming a source electrode connecting layer on the surface of the substrate, wherein the source electrode connecting layer is electrically connected with the source electrode region and the shielding region.
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