CN111564493B - Trench power transistor and method for fabricating the same - Google Patents
Trench power transistor and method for fabricating the same Download PDFInfo
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- CN111564493B CN111564493B CN201910114813.6A CN201910114813A CN111564493B CN 111564493 B CN111564493 B CN 111564493B CN 201910114813 A CN201910114813 A CN 201910114813A CN 111564493 B CN111564493 B CN 111564493B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
A trench power transistor includes a semiconductor substrate. The semiconductor substrate comprises at least one active part, wherein the at least one active part is provided with a gate trench structure, the gate trench structure is provided with a surrounding wall extending downwards from the top surface and defining a gate trench, a first isolation layer which is made of an insulating material and extends to cover the surface of the surrounding wall, an isolation unit which is filled in the gate trench and covers the first isolation layer, a shielding electrode which is positioned at the bottom of the gate trench, and a gate electrode which is positioned above the shielding electrode. The fourth isolation layer is made to cover the peripheral surface of the gate electrode adjacent to the shielding electrode by the structural design of the isolation unit, so that the gate electrode is isolated from the nitride material, and the defect that the element characteristics are affected due to interaction caused by contact or too close contact of the gate electrode with the nitride is avoided. In addition, the invention also provides a method for manufacturing the trench type power transistor.
Description
Technical Field
The present invention relates to a power transistor and a method for fabricating the same, and more particularly, to a trench power transistor and a method for fabricating the same.
Background
Power transistors (Power MOSFETs) are used in digital circuits or analog circuits, and thus are currently the main current source of Power devices and are widely used in various electronic devices.
The power transistors may be divided into horizontal and vertical power transistors according to current flow paths, wherein the vertical power transistors are commonly known as trench gate metal oxide semiconductor field effect transistors (Trench Gate Power MOSFET, or UMOSFETs), V-trench metal oxide semiconductor field effect transistors (VMOSFETs), or vertical double-diffused metal oxide semiconductor field effect transistors (VDMOSFETs). Furthermore, the U-shaped trench can effectively reduce the on-state resistance and improve the terminal edge characteristics (edge termination characteristics) of the transistor, which also makes the trench gate MOSFET become the main stream of high frequency low voltage power devices.
However, although the on-resistance of the trench power transistor can be reduced, in the blocking mode (blocking mode), since all the forward blocking voltages (forward blocking voltage) flowing through the drift region (e.g., N-type drift layer) need to be received, the doping concentration of the drift region must be reduced in order to receive the higher forward blocking voltages, but the on-resistance of the device is improved by reducing the doping concentration of the drift region, which is detrimental to the device characteristics. In addition, because the volume of the gate electrode in the trench is large, the gate-drain capacitance (gate-to-drain capacitance C) GD ) And also larger, and also reduces the sensitivity of the trench power transistor at high frequencies.
Referring to fig. 1, US5998833 discloses a power transistor capable of improving high frequency characteristics and breakdown voltage. Each transistor cell (unit cell) of the power transistor includes a first type doped drain layer (drain layer) 114 having a high doping concentration (e.g., n+ doped), a first type doped drift region (drift layer) 112, a well region (base layer) 116 formed in the drift region 112 and being a second type doped, a high doping concentration source layer (source layer) 118, source electrode 128b and drain electrode 130 in ohmic contact with the source layer 118 and drain layer 114, respectively, and a trench structure. The trench structure has opposite sidewalls 120a, a bottom 120b, an oxide insulating layer 125, the oxide insulating layer 125 having a gate electrode 127, a trench source electrode (trench-based source electrode) 128a, and an insulating region 125a between the gate electrode 127 and the trench source electrode 128 a. It is mainly to replace part of the gate electrode with the trench source electrode 128a to reduce the gate-drain capacitance (gate-to-drain capacitance C) GD ) So as to reduce the interference current and gate charge generated during the high frequency operation of the device, and to increase the breakdown voltage and the switching speed of the device at high frequency without sacrificing the on-resistance.
In order to provide better device characteristics in the conventional trench power transistor with the shielding electrode (such as the trench source electrode 128a shown in fig. 1), a lower interface trap charge (interface trap charge) and dielectric trap charge (dielectric trap charge) are required between the insulating region 125a or the insulating region 125a and the trench source electrode 128a, and the insulating region 125a between the gate electrode 127 and the trench source electrode 128a needs to have a higher quality and a thickness that is sufficiently thick to withstand the potential difference between the gate electrode 127 and the trench source electrode 128a during operation.
Generally, in order to obtain a thicker isolation layer, the gate electrode 127 and the trench source electrode 128a are effectively isolated, so that a thicker silicon oxide isolation layer is usually obtained by multiple thermal oxidation. However, since the thermal oxidation process is performed at a relatively high temperature (typically 950 ℃ to 1150 ℃), the top region of the gate trench is easily oxidized to become larger, resulting in a smaller distance (mesa) between the adjacent gate trenches, which in turn affects the threshold voltage (threshold voltage, vth) of the device due to the close distance between the adjacent gate trenches and the conductive plugs, and thus is also prone to process variability, which is detrimental to the fabrication of high density devices.
Disclosure of Invention
The present invention is to provide a trench power transistor capable of improving the voltage resistance of a device and having a low on-resistance.
Accordingly, the trench power transistor of the present invention includes a semiconductor substrate. The semiconductor substrate comprises a top surface and at least one active part.
The at least one active portion has a gate trench structure, a well region, and a source.
The gate trench structure has a surrounding wall extending downward from the top surface and defining a gate trench, a first isolation layer made of an insulating material and extending to cover the surface of the surrounding wall, an isolation unit made of an insulating material and filled in the gate trench and covering the first isolation layer, a shielding electrode at the bottom of the gate trench, and a gate electrode above the shielding electrode. The isolation unit is provided with an upper isolation region between the top surface and the bottom of the gate trench, and a lower isolation region between the upper isolation region and the bottom of the gate trench, wherein the lower isolation region is provided with a second isolation layer and a third isolation layer which are sequentially formed from the surface of the first isolation layer, the second isolation layer is nitride, the second isolation layer and the third isolation layer are made of different insulating materials, the shielding electrode is positioned in the lower isolation region and is covered by the third isolation layer, the upper isolation region is provided with a fourth isolation layer which is made of insulating materials, covers the surface of the first isolation layer and the surface of the lower isolation region, and is made of different materials from the second isolation layer, the gate electrode is positioned in the upper isolation region, the peripheral surface of the gate electrode is covered by the fourth isolation layer, and the top surface of the gate electrode is exposed from the gate trench.
The well region extends downward from the top surface and to the gate trench structure.
The source is formed in the well region and extends to the gate trench structure.
Preferably, the trench power transistor of the present invention, wherein the third isolation layer and the fourth isolation layer are oxide.
Preferably, the trench power transistor of the present invention, wherein the first isolation layer is an oxide.
Preferably, the trench power transistor of the present invention, wherein the semiconductor substrate further comprises an edge termination structure surrounding the at least one active portion, having a surrounding surface extending downward from the top surface and defining a termination trench, an insulating unit made of an insulating material and filled in the termination trench, and a conductive portion covered by the insulating unit, the conductive portion extending upward from a bottom surface adjacent to the termination trench and having a height not less than 1/2 of a depth of the termination trench.
Preferably, in the trench power transistor of the present invention, the insulating unit is made of an insulating material, and has a first insulating layer, a second insulating layer, and a third insulating layer sequentially formed from a surface of the surrounding surface, the second insulating layer and the third insulating layer are made of different insulating materials, and the conductive portion is covered by the third insulating layer.
Preferably, in the trench power transistor of the present invention, the first blocking layer and the third blocking layer are oxide, and the second blocking layer is nitride.
Preferably, the trench power transistor of the present invention further comprises an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit penetrating through the insulating layer for external electrical connection, wherein the conductive unit has a source conductive plug in ohmic contact with the source, a gate conductive plug in ohmic contact with the gate electrode, and a terminal conductive plug in ohmic contact with the conductive portion.
Preferably, in the trench power transistor of the present invention, the semiconductor substrate has a plurality of active portions, and the semiconductor substrate further comprises at least one rectifying structure interposed between two adjacent active portions, the at least one rectifying structure having a schottky conductive plug in contact with the semiconductor substrate Cheng Xiaote.
In addition, the present invention is to provide a method for manufacturing a trench power transistor capable of improving the voltage resistance of a device and having a low on-resistance.
Thus, the method for fabricating the trench power transistor of the present invention comprises the following steps.
Step A, providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product is provided with a semiconductor substrate and a plurality of surrounding walls which are formed downwards from the top surface of the semiconductor substrate and define a grid trench.
And step B, sequentially depositing a first insulating layer, a nitride layer and a second insulating layer from the top surface of the semiconductor substrate and the surface of the surrounding wall of the gate trench, wherein the first insulating layer and the second insulating layer are made of insulating materials different from the nitride layer.
And C, filling polysilicon in the gate trench, and then etching to remove the second insulating layer exposed on the surfaces of the top surface and the surrounding walls of the gate trench.
And D, etching to remove the polysilicon at the inner part of the grid electrode ditch, and forming a third insulating layer covering the top surface and filling the grid electrode ditch in a thermal oxidation mode and covering the polysilicon.
And E, etching to remove the third insulating layer correspondingly positioned on the top surface to expose the nitride layer, and removing part of the third insulating layer filled in the grid ditch to a preset thickness between the third insulating layer and the polysilicon.
And F, etching to remove the exposed nitride layer, so that the first insulating layer covered by the nitride layer is exposed.
And G, depositing a fourth insulating layer on the exposed surfaces of the first insulating layer, the nitride layer, the second insulating layer, the third insulating layer and the polysilicon by utilizing low-pressure chemical vapor deposition at the temperature of 650-750 ℃.
And step H, depositing polysilicon on the fourth insulating layer of the grid electrode ditch, and etching and removing the fourth insulating layer correspondingly positioned on the top surface.
And I, forming a well region and a source electrode around the grid ditch by utilizing ion implantation, forming a plurality of active parts, forming an insulating layer covering the top surface of the semiconductor substrate and the active parts, and forming ohmic contact with the active parts to electrically connect the active parts to the outside.
Preferably, in the method for manufacturing a trench power transistor of the present invention, the semiconductor semi-product of the step a further includes a termination trench surrounding the gate trench, the step B sequentially deposits the first insulating layer, the nitride layer and the second insulating layer on the top surface of the semiconductor substrate, the surrounding wall of the gate trench and the surrounding surface of the termination trench, the step C simultaneously fills the polysilicon in the gate trench and the termination trench, and etches the second insulating layer corresponding to the top surface, the surrounding wall and the surrounding surface, the third insulating layer of the step D fills and covers the termination trench, the gate trench and the exposed area of the top surface, the step E removes the third insulating layer corresponding to the top surface and the termination trench, and exposes the polysilicon corresponding to the top surface and the termination trench, the step I further obtains an edge termination structure surrounding the active portion, and the conductive unit further enables the edge termination structure to be electrically connected to the outside.
Preferably, in the method for fabricating a trench power transistor of the present invention, the step I further forms at least one rectifying structure located between the gate trenches and in contact with the semiconductor substrate Cheng Xiaote.
The beneficial effects of the invention are that: the fourth isolation layer is formed by deposition at 650-750 ℃ by utilizing the process and structural design, and the peripheral surfaces adjacent to the gate electrode and the shielding electrode are covered by the fourth isolation layer, so that the gate electrode and the nitride material are isolated, and the influence on the characteristics of the element caused by the interaction between the gate electrode and the nitride or the interaction caused by the contact or the too close approach of the gate electrode and the nitride is avoided.
Drawings
FIG. 1 is a schematic side cross-sectional view illustrating a conventional trench power transistor;
FIG. 2 is a schematic side cross-sectional view illustrating an embodiment of a trench power transistor of the present invention;
FIG. 3 is a text flow chart illustrating the manufacturing process of the embodiment of the present invention;
fig. 4 is a schematic diagram for aiding in the description of the structure formed by step 93;
FIG. 5 is a schematic diagram that assists in illustrating the structure formed via step 94;
FIG. 6 is a schematic diagram that assists in illustrating the structure formed via step 95;
FIG. 7 is a schematic diagram to assist in illustrating the structure formed by step 96;
FIG. 8 is a schematic diagram to assist in illustrating the structure formed by step 98; a kind of electronic device with high-pressure air-conditioning system
FIG. 9 is a schematic diagram illustrating a trench power transistor according to the present invention further having a rectifying structure.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples. In the drawings, like reference numbers indicate identical or functionally similar elements. Before the present invention is described in detail, it should be noted that in the following description, like elements are denoted by the same reference numerals.
Referring to FIG. 2, an embodiment of the trench power transistor of the present invention comprises a substrate 2, a semiconductor body 3, an edge termination structure 4, an insulating layer 5, and a conductive unit 6.
The substrate 2 has a drain electrode 21 and a drain region 22 of semiconductor material with a high concentration of a first type doping in ohmic contact with the drain electrode 21.
The semiconductor body 3 covers the drain region 22, has a top surface 31 opposite the substrate 2, a drift region 32 extending upwardly from the drain region 22 and having a doping of the first type with a doping concentration less than that of the drain region 22, and at least one active portion 3A formed in the drift region 32. The top surface 31 is the surface of the drift region 32 opposite to the drain electrode 21, and is illustrated by 2 active portions 3A in fig. 2. It is noted that the first type doping is a first conductivity type doping, and the second type doping is a second conductivity type doping having an opposite electrical property to the first conductivity type doping. For example, the first type doping is N type doping, and the second type doping is P type doping; when the first type doping is P type doping, the second type doping is N type doping. The trench power transistor of the present invention can be used for NMOS and PMOS, and is not particularly limited.
Each active portion 3A comprises a gate trench structure 33, a well region 34 having a second type doping, and a source 35 having a first type doping. The gate trench structure 33 extends downward from the top surface 31 to form the drift region 32, and the well region 34 extends downward from the top surface 31 to the gate trench structure 33. The source 35 is formed in the well 34 and extends to the gate trench structure 33.
In detail, the gate trench structure 33 has a wall 331 extending downward from the top surface 31 and defining a gate trench, a first isolation layer 36 extending over the surface of the wall 331, an isolation unit 37 filled in the gate trench and covering the first isolation layer 36, a shielding electrode 38 at the bottom of the gate trench, and a gate electrode 39 above the shielding electrode 38.
The isolation unit 37 is made of an insulating material and has a lower isolation region 37A at the bottom of the gate trench and an upper isolation region 37B between the lower isolation region 37A and the top surface 31.
The lower isolation region 37A has a second isolation layer 371 and a third isolation layer 372 sequentially formed from the surface of the first isolation layer 36, the second isolation layer 371 being composed of nitride which protects the first isolation layer 36 and prevents the first isolation layer 36 from oxidation growth.
The upper isolation region 37B has a fourth isolation layer 373 made of an oxide insulating material covering the surface of the first isolation layer 36 and the surfaces of the second isolation layer 371 and the third isolation layer 372 of the lower isolation region 37A. In the present embodiment, the first isolation layer 36 and the third isolation layer 372 are silicon oxide, the second isolation layer is silicon nitride, and the fourth isolation layer 373 is oxide (silicon dioxide) deposited by low pressure chemical vapor deposition at a temperature of 650 ℃ to 750 ℃ and has a thickness of about 100 to about
The material composition of (2) is exemplified.
It is noted that the silicon oxide of the first isolation layer 36 and the third isolation layer 372 may be formed by different processes. For example, the first isolation layer 36 may be formed by chemical vapor deposition or thermal oxidation, and the third isolation layer 372 may be formed by thermal oxidation. The method for manufacturing the film layer is well known in the art, and therefore, no further description is given.
The shielding electrode 38 is located in the lower isolation region 37A and is covered by the third isolation layer 372. The gate electrode 39 is located in the upper isolation region 37B, wherein the peripheral surface of the gate electrode 39 is covered by the fourth isolation layer 373 and the top surface is exposed from the gate trench, the third isolation layer 372 has a thickness T between the shielding electrode 38 and the gate electrode 39, and the thickness T is between 2000 and 2000
The edge termination structure 4 surrounds the active portion 3A and is located at the outermost periphery of the active portion 3A. Has a surrounding surface 41 extending downward from the top surface 31 and defining a termination trench, an insulating unit 42 filled in the termination trench and made of an insulating material, and a conductive portion 43 covered by the insulating unit 42.
The insulating unit 42 has a first insulating layer 421, a second insulating layer 422, and a third insulating layer 423 sequentially formed from the surface of the surrounding surface 41. The second blocking layer 422 is made of a material capable of protecting the first blocking layer 421 and preventing the first blocking layer 421 from being oxidized, the first blocking layer 421 and the third blocking layer 423 can be made of the same or different materials, and made of different materials from the second blocking layer 422, and the conductive portion 43 is covered by the third blocking layer 423.
In some embodiments, the first blocking layer 421, the second blocking layer 422, and the third blocking layer 423 are respectively made of oxide, nitride, and oxide, and in this embodiment, the first blocking layer 421, the second blocking layer 422, and the third blocking layer 423 are respectively made of silicon oxide, silicon nitride, and silicon oxide. The silicon oxide of the first blocking layer 421 and the third blocking layer 423 may be formed by different processes. For example, the first blocking layer 421 can be formed by chemical vapor deposition or thermal oxidation, and the third blocking layer 423 can be formed by thermal oxidation. The method for manufacturing the film layer is well known in the art, and therefore, no further description is given.
In some embodiments, the conductive portion 43 extends upward from the bottom surface adjacent to the termination trench and has a height not less than 1/2 of the depth of the termination trench.
The insulating layer 5 covers the top surface 31 of the semiconductor substrate 3 and is made of an insulating material having a low dielectric constant, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like.
The conductive unit 6 is disposed on the insulating layer 5, and is configured to electrically connect the active portion 3A and the edge termination structure 4 to the outside via a three-dimensional wiring structure. Has a plurality of source conductive plugs 61 passing through the insulating layer 5 in ohmic contact with the source 35, a plurality of gate conductive plugs (not shown) in ohmic contact with the gate electrode 39, a terminal conductive plug 62 in ohmic contact with the conductive portion 44, and a conductive layer 63 formed on the surface of the insulating layer 5 for electrically connecting the source conductive plugs 61, gate conductive plugs, and terminal conductive plugs 62, respectively.
It should be noted that the nitride in the gate trench structure 33 may protect the silicon oxide from damage and influence of subsequent processes during etching and thermal processes, thereby affecting the interface characteristics between the gate trench structure 33 and the drift region 32. However, nitride interacts with the gate electrode 39 to affect device characteristics, so that the trench power transistor of the present invention utilizes the structural design of the isolation unit 37 to make the fourth isolation layer 373 cover the gate electrode 39 and make the fourth isolation layer 373 further between the gate electrode 39 and the shielding electrode 38, so that the gate electrode 39 is effectively isolated from the nitride material, and the problems of reduced operation performance and reliability of the trench power transistor due to induced charges generated by the interaction between nitride and the gate electrode 39 caused by the contact or too close of the gate electrode 39 and the second isolation layer 371 are avoided.
In addition, the trench power transistor of the present invention has a higher voltage resistance, so that the doping concentration of the drift region 32 can be increased, and the on-resistance can be reduced, thereby further reducing the power consumption of the device operation.
The method of fabricating the foregoing embodiment is described below with reference to fig. 3 to 8.
Referring to fig. 3 and 4, step 91 is first performed to provide a semiconductor semi-finished product.
The step 91 is to form the drain region 22 and the drift region 32 with the first type doping by using a general semiconductor epitaxy and ion implantation process. Then, a plurality of gate trenches and terminal trenches located at the outermost periphery of the gate trenches are etched downward from the top surface 31 of the drift region 32.
Then, step 92 is performed to deposit an insulating layer on the top surface 31, the surrounding walls 331 of the gate trench and the surrounding surface 41 of the termination trench.
In detail, the step 92 is to sequentially deposit a first insulating layer 201, a nitride layer 202, and a second insulating layer 203 from the top surface 31, the surrounding wall 331 of the gate trench, and the surface of the surrounding surface 41 of the termination trench.
It should be noted that the depth of the trench and the thickness of the insulating material are different depending on the voltage resistance of the power device to be fabricated, because the insulating material (e.g., a high dielectric insulating material such as silicon nitride (Si) 3 N 4 ) Alumina (Al) 2 O 3 ) Yttria (Y) 2 O 3 ) Titanium oxide (TiO) 2 ) Hafnium oxide (HfO) 2 ) Zirconium oxide (ZrO) 2 ) Or silicon oxide (SiO) 2 ) The selection of the trench depth and the relationship between the thickness of the insulating material and the voltage resistance of the power device is well known to those skilled in the art, and therefore will not be described. In the present embodiment, the first insulating layer 201 and the second insulating layer 203 are both illustrated by silicon oxide, the depth of the gate trench and the termination trench is about 2 to 6um, and the thickness of the first insulating layer 201 is about
The thickness of the nitride layer 202 is about 250 to +.>
And the thickness of the second insulating layer 203 is about 1000 to +.>
Then, step 93 is performed to fill the trench with polysilicon 204 and etch away a portion of the second insulating layer 203.
In detail, the step 93 is to fill the polysilicon 204 in the gate trench and the termination trench, and then etch and remove the second insulation layer 203 exposed on the surfaces of the surrounding walls 331 of the top surface 31 and the gate trench and the surrounding surface 41 of the termination trench. The structure shown in fig. 4 can be obtained.
Next, in step 94, a portion of the polysilicon 204 is etched away, and a third insulating layer 205 is formed.
The step 94 is to protect the polysilicon 204 of the termination trench with photoresist and etch away the polysilicon 204 in the portion of the gate trench. The height of the polysilicon 204 within the gate trench is no greater than 1/2 of the gate trench depth. Then, the photoresist is removed, and a third insulating layer 205 is formed by thermal oxidation or low pressure chemical vapor deposition to fill and cover the terminal trench, the gate trench and the exposed area of the top surface 31, so as to obtain the structure shown in fig. 5. In step 94, the third insulating layer 205 is formed of silicon oxide, for example, and the polysilicon 204 is removed by about 0.7 to 1.5 um.
Then, step 95 is performed to etch away a portion of the third insulating layer 205 to a predetermined thickness T from the polysilicon 204.
In detail, the third insulating layer 205 corresponding to the top surface 31 and the termination trench is etched and removed in the step 95, so that the nitride layer 202 and the polysilicon 204 of the termination trench are exposed, and a portion of the third insulating layer 205 filled in the gate trench is removed to have a predetermined thickness T with the polysilicon 204, thereby obtaining the structure shown in fig. 6. It should be noted that the thickness T may be adjusted according to device requirements, and in this embodiment the thickness T is about 2000 to about
Next, in step 96, a portion of the nitride layer 202 is etched away.
In the step 96, the exposed nitride layer 202 is etched and removed, so that the first insulating layer 201 covered by the nitride layer 202 is exposed, resulting in the structure shown in fig. 7. Referring to fig. 2, the first insulating layer 201, the nitride layer 202, the second insulating layer 203, and the third insulating layer 205 remaining at the bottom of the gate trench are the first insulating layer 36, the second insulating layer 371, and the third insulating layer 372, which are shown in fig. 2. The polysilicon 204 covered by the second insulating layer 203 and the third insulating layer 205 becomes the shielding electrode 38 as shown in fig. 2.
Then, referring to fig. 8, in step 97, a fourth insulating layer 206 is formed by low-pressure chemical vapor deposition.
In detail, in the step 97, tetraethyl orthosilicate (TEOS) is used as a reaction gas at a temperature between 650 ℃ and 750 ℃, and a fourth insulating layer 206 is formed by low-pressure chemical vapor deposition to cover the exposed surfaces of the first insulating layer 201, the nitride layer 202, the second insulating layer 203, the third insulating layer 205 and the polysilicon 204. The thickness of the fourth insulating layer 206 in this embodiment is about 100 a to about
Continuing with fig. 8, next, step 98 is performed to deposit polysilicon 207 in the gate trench.
In detail, the step 98 is to deposit polysilicon 207 prior to the gate trench, and then etch and remove the fourth insulating layer 206 corresponding to the top surface 31, resulting in the structure shown in fig. 8. Referring to fig. 2 again, the fourth insulating layer 206 remaining in the upper half of the gate trench after the etching in the step 98 forms the fourth isolation layer 373 as shown in fig. 2, and the polysilicon 207 surrounded by the fourth insulating layer 206 forms the gate electrode 39. In addition, the first insulating layer 201, the nitride layer 202, the second insulating layer 203, and the fourth insulating layer 206 remaining in the termination trench together constitute the insulating unit 42, and the polysilicon 204 remaining in the termination trench becomes the conductive portion 43. The gate trench structure 33 and the edge termination structure 4 are completed.
The insulating oxide between the shielding electrode 38 and the gate electrode 39 is formed by low-pressure chemical vapor deposition at a temperature not higher than 750deg.C, which not only solves the problem of contact between the gate electrode 39 and nitride (nitride layer 202), but also avoids the disadvantage of reduced distance between adjacent gate trenches due to multiple thermal oxidation processes.
Then, in step 99, ion implantation is performed to complete the fabrication of the active portion 3A.
In the step 99, a second type doped well region 34 and a first type doped source 35 with high doping concentration are formed around the gate trench structure 33, thereby completing the fabrication of the active portion 3A.
Next, an insulating layer 5 is formed on the top surface 31 of the semiconductor substrate 3, and through holes are formed on the insulating layer 5 corresponding to the source electrode 35, the gate electrode 39 and the conductive portion 44, and metal is deposited on the semiconductor substrate 3 through the through holes after ion implantation to form a source conductive plug 61, a gate conductive plug (not shown) and a terminal conductive plug 62 which are in ohmic contact with the semiconductor substrate 3, and then the drain electrode 21 and a conductive layer 63 electrically connected to the source conductive plug 61, the gate conductive plug and the terminal conductive plug 62, respectively, are formed. The power transistor shown in FIG. 2 is obtained.
It is noted that the height of the polysilicon 204 of the termination trench may be equal to or less than the depth of the termination trench, and when the height of the polysilicon is less than the depth of the termination trench, the step 94 is performed without using photoresist to protect the polysilicon 204 of the termination trench, and etching to remove the polysilicon 204 of the termination trench, so as to reduce the height of the polysilicon 204.
In addition, referring to FIG. 9, it is noted that in some embodiments, the semiconductor substrate further comprises at least one rectifying structure 7 interposed between two adjacent active portions 3A, the rectifying structure 7 may be integrated with a power MOSFET, or may be a trench-type rectifying Schottky diode (Trench MOS Barrier Schottky Rectifiers-TMBS) alone, and FIG. 9 illustrates the rectifying structure 7 integrated with a power MOSFET having a Schottky contact 71 with the drift region 32 Cheng Xiaote. The rectifying structure 7 can reduce the power consumption of the recovery time (recovery) of the trench power transistor during forward turn-on and turn-off.
When the semiconductor substrate further includes the rectifying structure 7 as shown in FIG. 9, the step 99 further forms a Schottky conductive plug 71 penetrating the insulating layer 5 and making Schottky contact with the semiconductor substrate 3, and then the Schottky conductive plug 71 is electrically connected to the outside by the conductive layer 63.
In summary, the trench power transistor of the present invention utilizes the process design of the isolation unit 37 to form the fourth isolation layer 373 by low-pressure chemical vapor deposition, so as to avoid the disadvantage of decreasing the adjacent gate trench distance caused by the formation of the post-oxide layer by multiple thermal oxidation processes. In addition, in combination with the structural design of the isolation unit 37, the fourth isolation layer 373 is used to encapsulate the gate electrode 39 between the gate electrode 39 and the shielding electrode 38, so that the gate electrode 39 is effectively isolated from the nitride material. Therefore, the problem of decreasing the operation performance and reliability of the trench power transistor due to the induced charges generated by the interaction between the nitride and the gate electrode 39 caused by the contact or the too close contact between the gate electrode 39 and the second isolation layer 371 can be avoided. The power transistor of the invention has higher voltage resistance, thus, the doping concentration of the drift region can be increased, the on-resistance can be further reduced, and the power consumption of the element operation can be further reduced, so that the aim of the invention can be truly achieved.
Claims (10)
1. A trench power transistor, comprising: the semiconductor substrate has a top surface and at least one active portion, and is characterized in that: the at least one active portion includes:
a gate trench structure having an enclosure wall extending downward from the top surface and defining a gate trench, a first isolation layer made of an insulating material and extending over the enclosure wall surface, an isolation unit filled in the gate trench and covering the first isolation layer, a shielding electrode located at the bottom of the gate trench, and a gate electrode located above the shielding electrode, wherein the isolation unit has an upper isolation region between the top surface and the bottom of the gate trench, and a lower isolation region between the upper isolation region and the bottom of the gate trench, the lower isolation region has a second isolation layer and a third isolation layer sequentially formed from the first isolation layer surface, the second isolation layer is nitride, the second isolation layer and the third isolation layer are made of different insulating materials, the shielding electrode is located in the lower isolation region and covered by the third isolation layer, the upper isolation region has a fourth isolation layer made of an insulating material covering the first isolation layer surface and the lower isolation region surface, and forming a material different from the second isolation layer, the gate electrode is located in the upper isolation region, the fourth isolation layer is covered by the fourth isolation layer and is exposed from the peripheral surface of the gate trench;
a well region extending downward from the top surface to the gate trench structure; a kind of electronic device with high-pressure air-conditioning system
A source formed in the well region and extending to the gate trench structure;
the semiconductor substrate further comprises an edge terminal structure surrounding the at least one active part, an insulating unit and a conductive part, wherein the edge terminal structure is provided with a surrounding surface which extends downwards from the top surface and defines a terminal trench, the insulating unit is made of insulating materials and is filled in the terminal trench, the conductive part is covered by the insulating unit, and the conductive part extends upwards from the bottom surface adjacent to the terminal trench and has a height not less than 1/2 of the depth of the terminal trench.
2. The trench power transistor of claim 1, wherein: the third isolation layer and the fourth isolation layer are oxides.
3. The trench power transistor of claim 1, wherein: the first isolation layer is an oxide.
4. The trench power transistor of claim 1, wherein: the insulating unit is made of insulating materials and is provided with a first insulating layer, a second insulating layer and a third insulating layer which are sequentially formed on the surface of the surrounding surface, the second insulating layer and the third insulating layer are made of different insulating materials, and the conductive part is covered by the third insulating layer.
5. The trench power transistor of claim 4, wherein: the first and third barrier layers are oxide and the second barrier layer is nitride.
6. The trench power transistor of claim 1, wherein: the semiconductor device further comprises an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit penetrating through the insulating layer for external electrical connection, wherein the conductive unit is provided with a source electrode conductive plug in ohmic contact with the source electrode, a gate electrode conductive plug in ohmic contact with the gate electrode, and a terminal conductive plug in ohmic contact with the conductive part.
7. The trench power transistor of claim 1, wherein: the semiconductor substrate has a plurality of active portions, and the semiconductor substrate further comprises at least one rectifying structure interposed between two adjacent active portions, the at least one rectifying structure having a Schottky conductive plug in contact with the semiconductor substrate Cheng Xiaote.
8. A method for fabricating a trench power transistor is disclosed, which is characterized in that: comprising:
step A, providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product is provided with a semiconductor substrate and a plurality of surrounding walls which are formed downwards from the top surface of the semiconductor substrate and define a grid trench;
step B, sequentially depositing a first insulating layer, a nitride layer and a second insulating layer from the top surface of the semiconductor substrate and the surface of the surrounding wall of the gate trench, wherein the first insulating layer and the second insulating layer are made of insulating materials different from the nitride layer;
step C, filling polysilicon in the gate trench, and then etching to remove the second insulating layer exposed on the surfaces of the top surface and the surrounding walls of the gate trench;
step D, etching to remove the polysilicon at the inner part of the grid electrode ditch, and forming a third insulating layer covering the top surface and filling the grid electrode ditch and covering the polysilicon in a thermal oxidation mode;
step E, etching to remove the third insulating layer correspondingly positioned on the top surface to expose the nitride layer, and removing part of the third insulating layer filled in the grid ditch to a preset thickness between the third insulating layer and the polysilicon;
step F, etching to remove the exposed nitride layer, so that the first insulating layer covered by the nitride layer is exposed;
step G, depositing a fourth insulating layer on the exposed surfaces of the first insulating layer, the nitride layer, the second insulating layer, the third insulating layer and the polysilicon by utilizing low-pressure chemical vapor deposition at the temperature of 650-750 ℃;
step H, depositing polysilicon on the fourth insulating layer of the grid electrode ditch, and etching and removing the fourth insulating layer correspondingly positioned on the top surface; a kind of electronic device with high-pressure air-conditioning system
And I, forming a well region and a source electrode around the grid ditch by utilizing ion implantation, forming a plurality of active parts, forming an insulating layer covering the top surface of the semiconductor substrate and the active parts, and forming ohmic contact with the active parts to electrically connect the active parts to the outside.
9. The method of fabricating a trench power transistor as defined in claim 8, wherein: the semiconductor semi-finished product of the step A further comprises a terminal trench surrounding the gate trench, the step B sequentially deposits the first insulating layer, the nitride layer and the second insulating layer on the top surface of the semiconductor substrate, the surrounding wall of the gate trench and the surrounding surface of the terminal trench, the step C simultaneously fills polysilicon in the gate trench and the terminal trench, the surrounding wall and the surrounding surface are etched to remove the second insulating layer correspondingly positioned on the top surface, the surrounding wall and the surrounding surface, the third insulating layer of the step D fills and covers the terminal trench, the gate trench and the exposed area of the top surface, the step E removes the third insulating layer correspondingly positioned on the top surface and the terminal trench, the polysilicon of the nitride layer and the terminal trench is exposed, the step I also obtains an edge terminal structure surrounding the active part, and the conductive unit can be electrically connected with the edge terminal structure.
10. The method of fabricating a trench power transistor as defined in claim 9, wherein: the step I also forms at least one rectifying structure between the gate trenches in contact with the semiconductor substrate Cheng Xiaote.
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| TW200304681A (en) * | 2002-03-19 | 2003-10-01 | Infineon Technologies Ag | Method for fabricating a transistor arrangement having trench transistor cells having a field electrode |
| DE102007003812A1 (en) * | 2007-01-25 | 2008-08-07 | Infineon Technologies Ag | Semiconductor device with trench gate and method of manufacture |
| TW200915437A (en) * | 2007-08-21 | 2009-04-01 | Fairchild Semiconductor | Method and structure for shielded gate trench FET |
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| TW200304681A (en) * | 2002-03-19 | 2003-10-01 | Infineon Technologies Ag | Method for fabricating a transistor arrangement having trench transistor cells having a field electrode |
| DE102007003812A1 (en) * | 2007-01-25 | 2008-08-07 | Infineon Technologies Ag | Semiconductor device with trench gate and method of manufacture |
| TW200915437A (en) * | 2007-08-21 | 2009-04-01 | Fairchild Semiconductor | Method and structure for shielded gate trench FET |
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