CN111564493A - Trench power transistor and method for fabricating the same - Google Patents
Trench power transistor and method for fabricating the same Download PDFInfo
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- CN111564493A CN111564493A CN201910114813.6A CN201910114813A CN111564493A CN 111564493 A CN111564493 A CN 111564493A CN 201910114813 A CN201910114813 A CN 201910114813A CN 111564493 A CN111564493 A CN 111564493A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
A trench power transistor includes a semiconductor substrate. The semiconductor substrate comprises at least one active part, wherein the at least one active part is provided with a grid ditch structure, the grid ditch structure is provided with a surrounding wall which extends downwards from the top surface and defines a grid ditch, a first isolating layer which is made of insulating materials and extends to cover the surface of the surrounding wall, an isolating unit which is made of insulating materials, filled in the grid ditch and covers the first isolating layer, a shielding electrode which is positioned at the bottom of the grid ditch, and a grid electrode which is positioned above the shielding electrode. By using the structural design of the isolation unit, the fourth isolation layer covers the peripheral surface of the gate electrode adjacent to the shielding electrode, and the gate electrode can be isolated from the nitride material, so that the defect that the device characteristics are influenced due to the interaction generated by the contact or close proximity of the gate electrode and the nitride can be avoided. In addition, the invention also provides a method for manufacturing the trench type power transistor.
Description
Technical Field
The present invention relates to a power transistor and a method for fabricating the same, and more particularly, to a trench power transistor and a method for fabricating the same.
Background
Power transistors (Power MOSFETs) are used in digital circuits or analog circuits, and are therefore the mainstream of Power devices and widely used in various electronic devices.
The Power transistor can be divided into a horizontal type and a vertical type according to the current flowing path, wherein, for the vertical type Power transistor, it is commonly known to be a Trench Gate metal oxide semiconductor field effect transistor (MOSFET, or UMOSFET), a V-type Trench metal oxide semiconductor field effect transistor (VMOSFET), or a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET). In the trench power transistor, the U-shaped trench can effectively reduce the on-state resistance and improve the edge characteristics of the transistor, so that the trench gate MOSFET is the main current of the high frequency low voltage power device.
However, although the on-resistance of the trench power transistor can be reduced, in the blocking mode, the on-resistance of the device is not good because the device is required to withstand the forward blocking voltage (forward blocking voltage) flowing through the drift region (e.g., N-type drift layer), and therefore, in order to withstand a higher forward blocking voltage, the doping concentration of the drift region must be reduced, but the reduction of the doping concentration of the drift region increases the on-resistance of the device, which is not good for the device characteristics. In addition, because the gate electrode in the trench has a larger volume, the gate-to-drain capacitance (gate-to-drain capacitance)GD) Also larger, and also reduces the sensitivity of the trench power transistor at high frequencies.
Referring to fig. 1, U.S. patent No. US5998833 discloses a power transistor capable of improving high frequency characteristics and breakdown voltage. Each unit cell (unit cell) of the power transistor includes a drain layer (drain layer)114 doped with a first type and having a high doping concentration (e.g., N < + >), a drift region (drift layer)112 doped with a first type, a well region (bas) formed in the drift region 112 and doped with a second type (P < + >)e layer)116, a source layer 118 of high doping concentration, source electrodes 128b and drain electrodes 130 in ohmic contact with the source layer 118 and drain layer 114, respectively, and a trench structure. The trench structure has two opposite sidewalls 120a, a bottom 120b, an oxide insulating layer 125, the oxide insulating layer 125 having a gate electrode 127, a trench-based source electrode 128a, and an insulating region 125a between the gate electrode 127 and the trench source electrode 128 a. The trench source electrode 128a is used to replace part of the gate electrode to reduce the gate-to-drain capacitance (gate-to-drain capacitance C)GD) The method can reduce the interference current and gate charge generated during high frequency operation of the device, thereby improving breakdown voltage and switching speed of the device at high frequency without sacrificing on-resistance.
In order to have better device characteristics, the conventional trench power transistor having a shielding electrode (such as the trench source electrode 128a shown in fig. 1) needs to have a lower interface trap charge (interface trap charge) and dielectric trap charge (dielectric trap charge) in the insulating region 125a or between the insulating region 125a and the trench source electrode 128a, and the insulating region 125a between the gate electrode 127 and the trench source electrode 128a needs to have a higher quality and a thickness enough to withstand the potential difference between the gate electrode 127 and the trench source electrode 128a during operation.
To effectively isolate the gate electrode 127 from the trench source electrode 128a, a thicker isolation layer is typically formed by thermal oxidation multiple times. However, since the thermal oxidation process is performed at a high temperature (usually between 950 ℃ to 1150 ℃), when the thermal oxidation times are high, the top region of the gate trench is easily oxidized to be large, which results in a small distance (mesa) between adjacent gate trenches, and the distance between the top region and the adjacent gate trench is too close when the conductive plug is subsequently formed, which affects the threshold voltage (Vth) of the device, and is also easy to cause process variability, which is not favorable for the fabrication of high density devices.
Disclosure of Invention
The present invention provides a trench power transistor with a low on-resistance and a high voltage resistance.
Thus, the trench power transistor of the present invention includes a semiconductor substrate. The semiconductor substrate includes a top surface and at least one active portion.
The at least one active portion has a gate trench structure, a well region, and a source.
The grid ditch structure is provided with a wall extending downwards from the top surface and defining a grid ditch, a first isolation layer which is made of insulating materials and extends to cover the surface of the wall, an isolation unit which is made of insulating materials, filled in the grid ditch and covers the first isolation layer, a shielding electrode positioned at the bottom of the grid ditch, and a grid electrode positioned above the shielding electrode. The isolation unit is provided with an upper isolation region between the top surface and the bottom of the grid ditch and a lower isolation region between the upper isolation region and the bottom of the grid ditch, the lower isolation region is provided with a second isolation layer and a third isolation layer which are sequentially formed from the surface of the first isolation layer, the second isolation layer is nitride, the second isolation layer and the third isolation layer are made of different insulating materials, the shielding electrode is positioned in the lower isolation region and is coated by the third isolation layer, the upper isolation region is provided with a fourth isolation layer which is made of an insulating material, covers the surface of the first isolation layer and the surface of the lower isolation region and is made of a material different from that of the second isolation layer, the grid electrode is positioned in the upper isolation region, the peripheral surface of the grid electrode is coated by the fourth isolation layer, and the top surface of the grid electrode is exposed from the grid ditch.
The well region extends from the top surface down to the gate trench structure.
The source is formed in the well region and extends to the gate trench structure.
Preferably, in the trench power transistor of the present invention, the third isolation layer and the fourth isolation layer are oxide.
Preferably, in the trench power transistor of the present invention, the first isolation layer is an oxide.
Preferably, the trench power transistor of the present invention further includes an edge termination structure surrounding the at least one active portion, an insulating unit formed of an insulating material and filled in the terminal trench, and a conductive portion covered by the insulating unit, the conductive portion extending upward from a bottom surface adjacent to the terminal trench and having a height not less than 1/2 of a depth of the terminal trench.
Preferably, in the trench power transistor of the present invention, the insulating unit is made of an insulating material, and has a first blocking layer, a second blocking layer, and a third blocking layer sequentially formed from the surface of the surrounding surface, the second blocking layer and the third blocking layer are made of different insulating materials, and the conductive portion is covered by the third blocking layer.
Preferably, in the trench power transistor of the present invention, the first blocking layer and the third blocking layer are oxides, and the second blocking layer is a nitride.
Preferably, the trench power transistor of the present invention further includes an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit penetrating the insulating layer for external electrical connection, the conductive unit having a source conductive plug in ohmic contact with the source, a gate conductive plug in ohmic contact with the gate electrode, and a terminal conductive plug in ohmic contact with the conductive portion.
Preferably, the trench power transistor of the present invention has a plurality of active portions on the semiconductor substrate, and the semiconductor substrate further includes at least one rectifying structure between two adjacent active portions, wherein the at least one rectifying structure has a schottky conductive plug in schottky contact with the semiconductor substrate.
In addition, the present invention provides a method for fabricating a trench power transistor with a low on-resistance while improving the voltage endurance of the device.
Thus, the manufacturing method of the trench power transistor of the present invention includes the following steps.
Step A, providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product is provided with a semiconductor substrate and a plurality of surrounding walls which are formed downwards from the top surface of the semiconductor substrate and define a grid ditch.
And step B, sequentially depositing a first insulating layer, a nitride layer and a second insulating layer from the top surface of the semiconductor substrate and the surface of the surrounding wall of the grid trench, wherein the first insulating layer and the second insulating layer are made of different insulating materials from the nitride layer.
And step C, filling polysilicon in the gate trench, and etching to remove the second insulating layer exposed from the top surface and the surface of the wall of the gate trench.
And D, etching and removing part of the polycrystalline silicon in the grid ditch, and forming a third insulating layer which covers the top surface, is filled in the grid ditch and covers the polycrystalline silicon in a thermal oxidation mode.
And E, etching and removing the third insulating layer corresponding to the top surface to expose the nitride layer, and removing part of the third insulating layer filled in the gate trench to a preset thickness between the third insulating layer and the polysilicon.
And F, etching and removing the exposed nitride layer to expose the first insulating layer covered by the nitride layer.
And G, depositing a fourth insulating layer on the exposed surfaces of the first insulating layer, the nitride layer, the second insulating layer, the third insulating layer and the polysilicon by using low-pressure chemical vapor deposition at the temperature of 650-750 ℃.
And H, depositing polysilicon on the fourth insulating layer of the gate trench, and etching and removing the fourth insulating layer correspondingly positioned on the top surface.
And step I, forming a well region and a source electrode around the grid trench by utilizing ion implantation to form a plurality of active parts, then forming an insulating layer covering the top surface of the semiconductor substrate and the active parts, and forming a conductive unit which is in ohmic contact with the active parts and is used for electrically connecting the active parts to the outside.
Preferably, the method for fabricating a trench power transistor according to the present invention, wherein the semiconductor semi-finished product of step a further comprises a terminal trench surrounding the gate trench, step B is to deposit the first insulating layer, the nitride layer and the second insulating layer sequentially from the top surface of the semiconductor substrate, the wall of the gate trench and the surrounding surface of the terminal trench, step C is to fill polysilicon in the gate trench and the terminal trench at the same time, and etch and remove the second insulating layer on the top surface, the wall and the surrounding surface, the third insulating layer of step D fills and covers the exposed areas of the terminal trench, the gate trench and the top surface, and step E is to remove the third insulating layer on the top surface and the terminal trench to expose the nitride layer and the polysilicon of the terminal trench, step I also results in an edge termination structure surrounding the active portion, and the conductive element is also electrically connectable to the edge termination structure.
Preferably, in the method for fabricating a trench power transistor according to the present invention, the step I further forms at least one rectifying structure located between the gate trenches and in schottky contact with the semiconductor substrate.
The invention has the beneficial effects that: by utilizing the process and structure design, the fourth isolation layer is formed by deposition at the temperature of 650-750 ℃, and the four isolation layers cover the peripheral surfaces of the gate electrode and the shielding electrode, so that the gate electrode can be isolated from the nitride material, and the influence of induced charges of the gate trench structure on the characteristics of the element caused by the interaction generated by the contact or close proximity of the gate electrode and the nitride can be avoided.
Drawings
FIG. 1 is a schematic side cross-sectional view illustrating a conventional trench power transistor;
FIG. 2 is a schematic side cross-sectional view illustrating an embodiment of a trench power transistor of the present invention;
FIG. 3 is a text flow diagram illustrating the fabrication process of this embodiment of the present invention;
fig. 4 is a schematic view for assisting in explaining the structure formed in step 93;
fig. 5 is a schematic view for assisting in explaining the structure formed in step 94;
fig. 6 is a schematic view for assisting in explaining the structure formed in step 95;
fig. 7 is a schematic view for assisting in explaining the structure formed in step 96;
fig. 8 is a schematic view for assisting in explaining the structure formed in step 98; and
FIG. 9 is a schematic diagram illustrating a trench power transistor having a rectifying structure.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples. In the drawings, like reference numbers can indicate functionally identical or similar elements. Before the present invention is described in detail, it should be noted that in the following description, like elements are represented by like reference numerals.
Referring to fig. 2, an embodiment of a trench power transistor of the present invention includes a substrate 2, a semiconductor substrate 3, an edge termination structure 4, an insulating layer 5, and a conductive unit 6.
The substrate 2 has a drain electrode 21 and a drain region 22 in ohmic contact with the drain electrode 21, made of a semiconductor material and having a high concentration of a first type dopant.
The semiconductor body 3 covers the drain region 22, has a top surface 31 opposite to the substrate 2, a drift region 32 extending upward from the drain region 22, having a first type doping and having a doping concentration less than that of the drain region 22, and at least one active portion 3A formed in the drift region 32. Wherein the top surface 31 is the surface of the drift region 32 opposite to the drain electrode 21 and is illustrated by 2 active portions 3A in fig. 2. It is noted that the first type dopant is a first conductivity type dopant, and the second type dopant is a second conductivity type dopant of opposite conductivity type to the first conductivity type dopant. For example, the first type doping is N type doping, and the second type doping is P type doping; when the first type doping is P type doping, the second type doping is N type doping. The trench power transistor of the present invention can be used for NMOS or PMOS without any limitation.
Each active portion 3A includes a gate trench structure 33, a well region 34 having the second type doping, and a source 35 having the first type doping. Wherein the gate trench structure 33 extends from the top surface 31 to the drift region 32, and the well region 34 extends from the top surface 31 to the gate trench structure 33. The source 35 is formed in the well region 34 and extends to the gate trench structure 33.
In detail, the gate trench structure 33 has a wall 331 extending downward from the top surface 31 and defining a gate trench, a first isolation layer 36 extending to cover the surface of the wall 331, an isolation unit 37 filling the gate trench and covering the first isolation layer 36, a shield electrode 38 at the bottom of the gate trench, and a gate electrode 39 above the shield electrode 38.
The isolation unit 37 is made of an insulating material, and has a lower isolation region 37A located at the bottom of the gate trench and an upper isolation region 37B between the lower isolation region 37A and the top surface 31.
The lower isolation region 37A has a second isolation layer 371 and a third isolation layer 372 formed sequentially from the surface of the first isolation layer 36, the second isolation layer 371 is made of nitride which can protect the first isolation layer 36 and can prevent the first isolation layer 36 from oxidation growth.
The upper isolation region 37B has a fourth isolation layer 373 formed of an oxide insulating material covering the surface of the first isolation layer 36 and the surfaces of the second isolation layer 371 and the third isolation layer 372 of the lower isolation region 37A. In the present embodiment, the first isolation layer 36 and the third isolation layer 372 are silicon oxide, the second isolation layer is silicon nitride, and the fourth isolation layer 373 is oxide (silicon dioxide) deposited by low pressure chemical vapor deposition at 650-750 deg.C, with a thickness of about 100-750 deg.C
The material composition of (2) will be described.
It is noted that the silicon oxide of the first isolation layer 36 and the third isolation layer 372 may be formed by different processes. For example, the first isolation layer 36 may be formed by chemical vapor deposition or thermal oxidation, and the third isolation layer 372 may be silicon oxide formed by thermal oxidation. Since the manufacturing method of the film is well known in the art, further description is omitted.
The shielding electrode 38 is located in the lower isolation region 37A and is covered by the third isolation layer 372. The gate electrode 39 is located in the upper isolation region 37B, wherein the gate electrode 39 is surrounded by the fourth isolation layer 373 and exposed from the gate trench at its top surface, and the third isolation layer 372 has a thickness T between the shield electrode 38 and the gate electrode 39, wherein the thickness T is between 2000 and 39
The edge termination structure 4 surrounds the active portion 3A and is located at the outermost periphery of the active portion 3A. Has a surrounding surface 41 extending downward from the top surface 31 and defining a terminal trench, an insulating unit 42 filled in the terminal trench and made of insulating material, and a conductive portion 43 covered by the insulating unit 42.
The insulating unit 42 has a first blocking layer 421, a second blocking layer 422, and a third blocking layer 423 sequentially formed from the surface of the surrounding surface 41. The second blocking layer 422 is made of a material that can protect the first blocking layer 421 and can prevent the first blocking layer 421 from being oxidized and grown, the first blocking layer 421 and the third blocking layer 423 can be selected from the same or different materials and are made of different materials from the second blocking layer 422, and the conductive portion 43 is covered by the third blocking layer 423.
In some embodiments, the first blocking layer 421, the second blocking layer 422, and the third blocking layer 423 are respectively made of oxide, nitride, and oxide, and in this embodiment, the first blocking layer 421, the second blocking layer 422, and the third blocking layer 423 are respectively made of silicon oxide, silicon nitride, and silicon oxide. The silicon oxide of the first blocking layer 421 and the third blocking layer 423 can be formed by different processes. For example, the first blocking layer 421 may be formed by chemical vapor deposition or thermal oxidation, and the third blocking layer 423 may be silicon oxide with a denser structure. Since the manufacturing method of the film is well known in the art, further description is omitted.
In some embodiments, the conductive portion 43 extends upwardly from adjacent the bottom surface of the termination trench and has a height no less than 1/2 of the depth of the termination trench.
The insulating layer 5 covers the top surface 31 of the semiconductor substrate 3 and is made of an insulating material having a low dielectric constant, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like.
The conductive unit 6 is disposed on the insulating layer 5, and can be used to electrically connect the active portion 3A and the edge terminal structure 4 to the outside through a three-dimensional wiring structure. There are a plurality of source conductive plugs 61 in ohmic contact with the source electrode 35 through the insulating layer 5, a plurality of gate conductive plugs (not shown) in ohmic contact with the gate electrode 39, a terminal conductive plug 62 in ohmic contact with the conductive portion 44, and a conductive layer 63 formed on the surface of the insulating layer 5 for electrically connecting the source conductive plugs 61, the gate conductive plugs, and the terminal conductive plugs 62, respectively.
It should be noted that the nitride in the gate trench structure 33 can protect the silicon oxide from being damaged and affected by the subsequent processes during the etching and thermal processes, and thus the interfacial characteristics between the gate trench structure 33 and the drift region 32 are not affected. However, the nitride also interacts with the gate electrode 39 to affect the device characteristics, so that the trench power transistor of the present invention utilizes the structural design of the isolation unit 37 to make the fourth isolation layer 373 cover the gate electrode 39 and further make the fourth isolation layer 373 be between the gate electrode 39 and the shielding electrode 38, so as to effectively isolate the gate electrode 39 from the nitride material, thereby avoiding the problem that the interaction between the nitride and the gate electrode 39 generates induced charges due to the contact or too close proximity of the gate electrode 39 and the second isolation layer 371, which reduces the operation performance and reliability of the trench power transistor.
In addition, the trench power transistor of the present invention has a higher voltage resistance, so that the doping concentration of the drift region 32 can be increased, and the on-resistance can be reduced, thereby further reducing the power consumption of the device operation.
The manufacturing method of the embodiment is described below with reference to fig. 3 to 8.
Referring to fig. 3 and 4, a step 91 of providing a semiconductor semi-finished product is performed.
The drain region 22 and the drift region 32 are formed with a first type of doping in step 91 using conventional semiconductor epitaxy and ion implantation processes. Next, a plurality of gate trenches and a terminal trench located at the outermost periphery of the gate trenches are etched from the top surface 31 of the drift region 32.
Then, step 92 is performed to deposit an insulating layer on the top surface 31, the wall 331 of the gate trench and the surface 41 of the terminal trench.
In detail, the step 92 is to sequentially deposit a first insulating layer 201, a nitride layer 202, and a second insulating layer 203 from the top surface 31, the wall 331 of the gate trench, and the surface of the surrounding surface 41 of the terminal trench.
It should be noted that the depth of the trench and the thickness of the insulating material are different according to the voltage resistance of the power device to be fabricated, because of the insulating material (e.g. high dielectric insulating material commonly used in semiconductors, such as silicon nitride (Si)3N4) Alumina (Al)2O3) Yttrium oxide (Y)2O3) Titanium oxide (TiO)2) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Etc. or is silicon oxide (SiO)2) The choice of trench and the relationship between the depth of the trench and the thickness of the insulating material and the voltage resistance of the power device are well known in the art, and therefore, will not be further described. In the present embodiment, the first insulating layer 201 and the second insulating layer 203 are silicon oxide, and the gate trench and the terminal trench are illustrated as the exampleIs about 2 to 6um, and the thickness of the first insulating layer 201 is about
The nitride layer 202 has a thickness of about 250 a to about 250 a
And the thickness of the second insulating layer 203 is about 1000 a to
Then, step 93 is performed to fill the trenches with polysilicon 204 and etch away a portion of the second insulating layer 203.
In detail, the step 93 is to fill the gate trench and the terminal trench with polysilicon 204, and then etch and remove the exposed second insulating layer 203 corresponding to the walls 331 of the top surface 31 and the gate trench and the surrounding surface 41 of the terminal trench. The structure shown in fig. 4 is obtained.
Next, in step 94, a portion of the polysilicon layer 204 is etched away to form a third insulating layer 205.
The polysilicon 204 in the termination trench is protected by photoresist at step 94 and the portion of the polysilicon 204 in the gate trench is etched away. The height of the polysilicon 204 in the gate trench is no greater than 1/2 the depth of the gate trench. Then, the photoresist is removed, and a third insulating layer 205 is formed by thermal oxidation or low pressure chemical vapor deposition to fill and cover the terminal trench, the gate trench and the exposed region of the top surface 31, so as to obtain the structure shown in fig. 5. In step 94, the third insulating layer 205 is formed of silicon oxide, for example, and about 0.7 to 1.5um of the polysilicon 204 is removed.
Then, in step 95, a portion of the third insulating layer 205 is etched and removed to have a predetermined thickness T with the polysilicon 204.
In detail, the step 95 is to etch away the third insulating layer 205 corresponding to the top surface 31 and the terminal trench, so that the nitride layer 202 and the poly of the terminal trench are formedThe silicon 204 is exposed and a portion of the third insulating layer 205 filling the gate trenches is removed to a predetermined thickness T with the polysilicon 204, resulting in the structure shown in fig. 6. It should be noted that the thickness T may be adjusted according to device requirements, and in the present embodiment, the thickness T is about 2000 to about 2000
Next, in step 96, a portion of the nitride layer 202 is etched away.
The exposed nitride layer 202 is etched away in step 96, exposing the first insulating layer 201 covered by the nitride layer 202, resulting in the structure shown in fig. 7. Referring to fig. 2, the first insulating layer 201, the nitride layer 202, the second insulating layer 203 and the third insulating layer 205 remaining at the bottom of the gate trench together form the first isolation layer 36, the second isolation layer 371 and the third isolation layer 372 shown in fig. 2. The polysilicon 204 covered by the second insulating layer 203 and the third insulating layer 205 becomes the shield electrode 38 shown in fig. 2.
Then, referring to fig. 8, in step 97, a fourth insulating layer 206 is formed by low pressure chemical vapor deposition.
In detail, in the step 97, a fourth insulating layer 206 covering the exposed surfaces of the first insulating layer 201, the nitride layer 202, the second insulating layer 203, the third insulating layer 205, and the polysilicon layer 204 is formed by low pressure chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a reaction gas at a temperature between 650 ℃ and 750 ℃. The thickness of the fourth insulating layer 206 in this embodiment is about 100 a to about 100 a
Referring still to fig. 8, next, at step 98, polysilicon 207 is deposited in the gate trenches.
In detail, the step 98 is to deposit polysilicon 207 before the gate trenches, and then etch away the fourth insulating layer 206 corresponding to the top surface 31, thereby obtaining the structure shown in fig. 8. Referring to fig. 2, the fourth insulating layer 206 remaining on the upper half of the gate trench after etching in step 98 forms the fourth isolation layer 373 shown in fig. 2, and the polysilicon 207 surrounded by the fourth insulating layer 206 forms the gate electrode 39. In addition, the first insulating layer 201, the nitride layer 202, the second insulating layer 203, and the fourth insulating layer 206 remaining in the terminal trench together constitute the insulating unit 42, and the polysilicon 204 remaining in the terminal trench serves as the conductive portion 43. Thereby completing the fabrication of the gate trench structure 33 and the edge termination structure 4.
The present invention utilizes low pressure chemical vapor deposition at a temperature of not greater than 750 ℃ to form the insulating oxide between the shield electrode 38 and the gate electrode 39, which not only solves the problem of contact between the gate electrode 39 and the nitride (nitride layer 202), but also avoids the disadvantage of reduced distance between adjacent gate trenches caused by multiple thermal oxidation processes.
Then, in step 99, ion implantation is performed to complete the fabrication of the active portion 3A.
In step 99, a well region 34 of the second type dopant and a source 35 of the first type dopant and having a high dopant concentration are formed around the gate trench structure 33, thereby completing the fabrication of the active portion 3A.
Then, an insulating layer 5 is formed on the top surface 31 of the semiconductor substrate 3, and through holes are formed at positions of the insulating layer 5 corresponding to the source electrode 35, the gate electrode 39, and the conductive portion 44, and metal is deposited after ion implantation is performed on the semiconductor substrate 3 through the through holes to form a source conductive plug 61, a gate conductive plug (not shown), and a terminal conductive plug 62 which are in ohmic contact with the semiconductor substrate 3, and then the drain electrode 21 and a conductive layer 63 electrically connected to the source conductive plug 61, the gate conductive plug, and the terminal conductive plug 62, respectively, are formed. The power transistor shown in FIG. 2 can be obtained.
It is noted that the height of the polysilicon 204 of the terminal trench may be equal to or less than the depth of the terminal trench, and when the height of the polysilicon is less than the depth of the terminal trench, the step 94 is performed without using photoresist to protect the polysilicon 204 of the terminal trench, and the polysilicon 204 of the terminal trench is etched away to reduce the height of the polysilicon 204.
In addition, referring to fig. 9, it is noted that in some embodiments, the semiconductor substrate further includes at least one rectifying structure 7 between two adjacent active portions 3A, the rectifying structure 7 may be integrated in a power mosfet or a Trench rectifying Schottky diodes (TMBS) alone, and fig. 9 illustrates the rectifying structure 7 integrated in a power mosfet and having a Schottky conductive plug 71 in Schottky contact with the drift region 32. The power consumption of the recovery time (recovery) of the trench power transistor during the forward conduction and the turn-off can be reduced by using the rectifying structure 7.
When the semiconductor substrate further includes the rectifying structure 7 as shown in FIG. 9, the step 99 further forms a Schottky conductive plug 71 penetrating through the insulating layer 5 and being in Schottky contact with the semiconductor substrate 3, and then electrically connects the Schottky conductive plug 71 to the outside by using the conductive layer 63.
In summary, the trench power transistor of the present invention utilizes the process design of the isolation unit 37 and utilizes the low pressure chemical vapor deposition to form the fourth isolation layer 373, so as to avoid the disadvantage of the reduced distance between adjacent gate trenches caused by the formation of the back oxide layer by multiple thermal oxidation processes. In addition, in combination with the structural design of the isolation unit 37, the fourth isolation layer 373 covers the gate electrode 39 and is disposed between the gate electrode 39 and the shielding electrode 38, so that the gate electrode 39 is effectively isolated from the nitride material. Therefore, the problem of reducing the operation performance and reliability of the trench power transistor due to the induced charge generated by the interaction between the nitride and the gate electrode 39 caused by the contact or close proximity between the gate electrode 39 and the second isolation layer 371 can be avoided. The power transistor of the present invention has higher voltage resistance, so the doping concentration of the drift region can be increased, the on-resistance can be reduced, and the power consumption of the device operation can be further reduced, thereby the purpose of the present invention can be achieved.
Claims (11)
1. A trench power transistor, comprising: the semiconductor substrate is provided with a top surface and at least one active part, and is characterized in that: the at least one active portion includes:
a gate trench structure having a wall extending downward from the top surface and defining a gate trench, a first isolation layer made of an insulating material and extending to cover the surface of the wall, an isolation unit filled in the gate trench and covering the first isolation layer, a shield electrode at the bottom of the gate trench, and a gate electrode above the shield electrode, wherein the isolation unit has an upper isolation region between the top surface and the bottom of the gate trench, and a lower isolation region between the upper isolation region and the bottom of the gate trench, the lower isolation region has a second isolation layer and a third isolation layer formed sequentially from the surface of the first isolation layer, the second isolation layer is a nitride, the second isolation layer and the third isolation layer are made of different insulating materials, and the shield electrode is located in the lower isolation region and covered by the third isolation layer, the upper isolation region is provided with a fourth isolation layer which is made of an insulating material, covers the surface of the first isolation region and the surface of the lower isolation region and is made of a material different from that of the second isolation layer, the grid electrode is positioned in the upper isolation region, the peripheral surface of the grid electrode is coated by the fourth isolation layer, and the top surface of the grid electrode is exposed from the grid ditch;
a well region extending from the top surface down to the gate trench structure; and
and a source electrode formed in the well region and extending to the gate trench structure.
2. The trench power transistor of claim 1, wherein: the third isolation layer and the fourth isolation layer are oxide.
3. The trench power transistor of claim 1, wherein: the first isolation layer is an oxide.
4. The trench power transistor of claim 1, wherein: the semiconductor body further includes an edge termination structure surrounding the at least one active portion, having a surrounding surface extending downward from the top surface and defining a termination trench, an insulating element formed of an insulating material and filling the termination trench, and a conductive portion covered by the insulating element, the conductive portion extending upward from adjacent a bottom surface of the termination trench and having a height not less than 1/2 a depth of the termination trench.
5. The trench power transistor of claim 4, wherein: the insulation unit is made of insulation materials and is provided with a first barrier layer, a second barrier layer and a third barrier layer which are sequentially formed from the surface of the surrounding surface, the second barrier layer and the third barrier layer are made of different insulation materials, and the conductive part is coated by the third barrier layer.
6. The trench power transistor of claim 5, wherein: the first and third barrier layers are oxide, and the second barrier layer is nitride.
7. The trench power transistor of claim 1, wherein: the semiconductor device further comprises an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit penetrating through the insulating layer and electrically connected to the outside, wherein the conductive unit is provided with a source electrode conductive plug in ohmic contact with the source electrode, a grid electrode conductive plug in ohmic contact with the grid electrode, and a terminal conductive plug in ohmic contact with the conductive part.
8. The trench power transistor of claim 1, wherein: the semiconductor substrate has a plurality of active portions, and the semiconductor substrate further includes at least one rectifying structure interposed between two adjacent active portions, the at least one rectifying structure having a Schottky conductive plug in Schottky contact with the semiconductor substrate.
9. A method for fabricating a trench power transistor is characterized in that: comprises the following steps:
step A, providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product is provided with a semiconductor substrate and a plurality of surrounding walls which are formed downwards from the top surface of the semiconductor substrate and define a grid ditch;
step B, depositing a first insulating layer, a nitride layer and a second insulating layer in sequence from the top surface of the semiconductor substrate and the surface of the surrounding wall of the grid ditch, wherein the first insulating layer and the second insulating layer are made of different insulating materials from the nitride layer;
step C, filling polycrystalline silicon in the grid ditch, and then etching and removing the second insulating layer exposed from the top surface and the surface of the wall of the grid ditch;
step D, etching and removing part of the polycrystalline silicon in the grid ditch, and forming a third insulating layer which covers the top surface, is filled in the grid ditch and covers the polycrystalline silicon in a thermal oxidation mode;
step E, etching and removing the third insulating layer corresponding to the top surface to expose the nitride layer, and removing part of the third insulating layer filled in the gate trench to a predetermined thickness between the third insulating layer and the polysilicon;
step F, etching and removing the exposed nitride layer to expose the first insulating layer covered by the nitride layer;
step G, depositing a fourth insulating layer on the exposed surfaces of the first insulating layer, the nitride layer, the second insulating layer, the third insulating layer and the polysilicon by using low-pressure chemical vapor deposition at the temperature of 650-750 ℃;
step H, depositing polysilicon on the fourth insulating layer of the gate trench, and etching and removing the fourth insulating layer correspondingly positioned on the top surface; and
and step I, forming a well region and a source electrode around the grid trench by utilizing ion implantation to form a plurality of active parts, then forming an insulating layer covering the top surface of the semiconductor substrate and the active parts, and forming a conductive unit which is in ohmic contact with the active parts and is used for electrically connecting the active parts to the outside.
10. The method of claim 9, wherein: the semi-finished product of the step A also comprises a terminal trench surrounding the grid trench, the step B is to deposit the first insulating layer, the nitride layer and the second insulating layer sequentially from the top surface of the semiconductor substrate, the surrounding wall of the grid trench and the surrounding surface of the terminal trench at the same time, step C, filling polysilicon in the gate trench and the terminal trench, and etching to remove the second insulating layer on the top surface, the wall and the surrounding surface, the third insulating layer of step D fills and covers the terminal trench, the gate trench and the exposed region of the top surface, step E is to remove the third insulation layer corresponding to the top surface and the terminal trench to expose the nitride layer and the polysilicon of the terminal trench, step I also results in an edge termination structure surrounding the active portion, and the conductive element is also electrically connectable to the edge termination structure.
11. The method of claim 10, wherein: step I also forms at least one rectifying structure between the gate trenches in Schottky contact with the semiconductor substrate.
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