TWI842116B - Transistor device and manufacturing method thereof - Google Patents

Transistor device and manufacturing method thereof Download PDF

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TWI842116B
TWI842116B TW111137684A TW111137684A TWI842116B TW I842116 B TWI842116 B TW I842116B TW 111137684 A TW111137684 A TW 111137684A TW 111137684 A TW111137684 A TW 111137684A TW I842116 B TWI842116 B TW I842116B
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dielectric layer
gate
layer
disposed
shielding electrode
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TW111137684A
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TW202416534A (en
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楊梅玉
何昌瑾
蔣永康
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力晶積成電子製造股份有限公司
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Priority to CN202211293091.3A priority patent/CN117894824A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor device including a substrate structure, a shield electrode, a first dielectric layer, a gate, and a gate dielectric layer is provided. There is a trench in the substrate structure. The shield electrode is disposed in the trench. The first dielectric layer is disposed between the shield electrode and the substrate structure. The gate is disposed in the trench and on the shield electrode. The gate dielectric layer is disposed between the gate and the substrate structure and between the gate and the shield electrode. The gate dielectric layer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the corner of the bottom of the gate and the substrate structure. The third dielectric layer is disposed between the gate and the substrate structure, between the gate and the second dielectric layer, and between the gate and the shield electrode.

Description

電晶體元件及其製造方法Transistor element and manufacturing method thereof

本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種電晶體元件及其製造方法。The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a transistor device and a manufacturing method thereof.

目前，發展出一種屏蔽閘極溝渠式電晶體(shielded gate trench transistor)，其可降低閘極與汲極之間的寄生電容且可改善電晶體元件的效能。一般而言，屏蔽閘極溝渠式電晶體包含閘極與位在閘極下方的屏蔽電極(shield electrode)。然而，由於位在閘極與基底之間的閘極介電層在閘極的底部的轉角處會有偏薄的現象，因此位在閘極的底部的轉角處的閘極介電層容易被擊穿，而導致電晶體元件失效。At present, a shielded gate trench transistor has been developed, which can reduce the parasitic capacitance between the gate and the drain and improve the performance of the transistor element. Generally speaking, the shielded gate trench transistor includes a gate and a shield electrode located below the gate. However, since the gate dielectric layer located between the gate and the substrate is thinner at the corner of the bottom of the gate, the gate dielectric layer located at the corner of the bottom of the gate is easily broken down, resulting in failure of the transistor element.

本發明提供一種電晶體元件及其製造方法，其可有效地防止閘極介電層被擊穿，進而防止電晶體元件失效。The present invention provides a transistor element and a manufacturing method thereof, which can effectively prevent the gate dielectric layer from being broken down, thereby preventing the transistor element from failing.

本發明提出一種電晶體元件，包括基底結構、屏蔽電極、第一介電層、閘極與閘極介電層。在基底結構中具有溝渠。屏蔽電極設置在溝渠中。第一介電層設置在屏蔽電極與基底結構之間。閘極設置在溝渠中與屏蔽電極上。閘極介電層設置在閘極與基底結構之間以及閘極與屏蔽電極之間。閘極介電層包括第二介電層與第三介電層。第二介電層設置在閘極的底部的轉角與基底結構之間。第三介電層設置在閘極與基底結構之間、閘極與第二介電層之間以及閘極與屏蔽電極之間。The present invention provides a transistor element, including a substrate structure, a shielding electrode, a first dielectric layer, a gate and a gate dielectric layer. A trench is provided in the substrate structure. The shielding electrode is arranged in the trench. The first dielectric layer is arranged between the shielding electrode and the substrate structure. The gate is arranged in the trench and on the shielding electrode. The gate dielectric layer is arranged between the gate and the substrate structure and between the gate and the shielding electrode. The gate dielectric layer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is arranged between the corner of the bottom of the gate and the substrate structure. The third dielectric layer is disposed between the gate and the base structure, between the gate and the second dielectric layer, and between the gate and the shielding electrode.

依照本發明的一實施例所述，在上述電晶體元件中，閘極介電層更可包括墊層。墊層設置在第二介電層與基底結構之間以及第三介電層與基底結構之間。According to an embodiment of the present invention, in the transistor device, the gate dielectric layer may further include a pad layer disposed between the second dielectric layer and the base structure and between the third dielectric layer and the base structure.

依照本發明的一實施例所述，在上述電晶體元件中，更可包括第四介電層。第四介電層設置在第三介電層與屏蔽電極之間。第二介電層與第四介電層可彼此分離。According to an embodiment of the present invention, the transistor device may further include a fourth dielectric layer. The fourth dielectric layer is disposed between the third dielectric layer and the shielding electrode. The second dielectric layer and the fourth dielectric layer may be separated from each other.

依照本發明的一實施例所述，在上述電晶體元件中，更可包括第一摻雜區、第二摻雜區與基體區(body region)。第一摻雜區設置在閘極旁邊的基底結構中。第二摻雜區設置在第一摻雜區下方的基底結構中。基體區設置在第一摻雜區與第二摻雜區之間的基底結構中。According to an embodiment of the present invention, the transistor element may further include a first doped region, a second doped region and a body region. The first doped region is disposed in the base structure next to the gate. The second doped region is disposed in the base structure below the first doped region. The body region is disposed in the base structure between the first doped region and the second doped region.

依照本發明的一實施例所述，在上述電晶體元件中，基底結構可包括基底與半導體層。半導體層設置在基底上。溝渠可位在半導體層中。According to an embodiment of the present invention, in the above transistor element, the substrate structure may include a substrate and a semiconductor layer. The semiconductor layer is disposed on the substrate. The trench may be located in the semiconductor layer.

本發明提出一種電晶體元件的製造方法，包括以下步驟。提供基底結構。在基底結構中形成溝渠。在溝渠中形成屏蔽電極。在屏蔽電極與基底結構之間形成第一介電層。在溝渠中與屏蔽電極上形成閘極。在閘極與基底結構之間以及閘極與屏蔽電極之間形成閘極介電層。閘極介電層包括第二介電層與第三介電層。第二介電層設置在閘極的底部的轉角與基底結構之間。第三介電層設置在閘極與基底結構之間、閘極與第二介電層之間以及閘極與屏蔽電極之間。The present invention provides a method for manufacturing a transistor element, comprising the following steps. A substrate structure is provided. A trench is formed in the substrate structure. A shielding electrode is formed in the trench. A first dielectric layer is formed between the shielding electrode and the substrate structure. A gate is formed in the trench and on the shielding electrode. A gate dielectric layer is formed between the gate and the substrate structure and between the gate and the shielding electrode. The gate dielectric layer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the corner of the bottom of the gate and the substrate structure. The third dielectric layer is disposed between the gate and the substrate structure, between the gate and the second dielectric layer, and between the gate and the shielding electrode.

依照本發明的一實施例所述，在上述電晶體元件的製造方法中，第二介電層的形成方法可包括以下步驟。在溝渠的側壁上形成矽間隙壁。在矽間隙壁上形成間隙壁。間隙壁可暴露出矽間隙壁的底部。對由間隙壁所暴露出的矽間隙壁的底部進行熱氧化製程，而形成第二介電層。According to an embodiment of the present invention, in the manufacturing method of the transistor element, the method for forming the second dielectric layer may include the following steps: forming a silicon spacer on the sidewall of the trench; forming a spacer on the silicon spacer; the spacer may expose the bottom of the silicon spacer; performing a thermal oxidation process on the bottom of the silicon spacer exposed by the spacer to form the second dielectric layer.

依照本發明的一實施例所述，在上述電晶體元件的製造方法中，更可包括以下步驟。對屏蔽電極進行熱氧化製程，而在屏蔽電極上形成第四介電層。According to an embodiment of the present invention, the manufacturing method of the transistor element may further include the following steps: performing a thermal oxidation process on the shielding electrode to form a fourth dielectric layer on the shielding electrode.

依照本發明的一實施例所述，在上述電晶體元件的製造方法中，矽間隙壁可位在第一介電層上。矽間隙壁的頂面可低於基底結構的頂面。According to an embodiment of the present invention, in the manufacturing method of the transistor device, the silicon spacer may be located on the first dielectric layer. The top surface of the silicon spacer may be lower than the top surface of the base structure.

依照本發明的一實施例所述，在上述電晶體元件的製造方法中，更包括以下步驟。在溝渠的側壁上形成墊層。第二介電層可形成在第一介電層與墊層上。第三介電層可形成在第一介電層與墊層上上。According to an embodiment of the present invention, the manufacturing method of the transistor element further includes the following steps: forming a pad on the sidewall of the trench; forming a second dielectric layer on the first dielectric layer and the pad; and forming a third dielectric layer on the first dielectric layer and the pad.

基於上述，在本發明所提出的電晶體元件及其製造方法中，由於第二介電層設置在閘極的底部的轉角與基底結構之間，因此可增加位在閘極的底部的轉角處的閘極介電層的厚度。如此一來，可有效地防止閘極介電層被擊穿，進而防止電晶體元件失效。此外，由於第二介電層設置在閘極的底部的轉角與基底結構之間，所以可彈性地調整第三介電層的厚度，藉此可彈性地調整電晶體元件的臨界電壓(threshold voltage，Vt)。Based on the above, in the transistor element and the manufacturing method thereof proposed in the present invention, since the second dielectric layer is disposed between the corner of the bottom of the gate and the base structure, the thickness of the gate dielectric layer at the corner of the bottom of the gate can be increased. In this way, the gate dielectric layer can be effectively prevented from being broken down, thereby preventing the transistor element from failing. In addition, since the second dielectric layer is disposed between the corner of the bottom of the gate and the base structure, the thickness of the third dielectric layer can be flexibly adjusted, thereby flexibly adjusting the critical voltage (threshold voltage, Vt) of the transistor element.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

下文列舉實施例並配合附圖來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。為了方便理解，在下述說明中相同的構件將以相同的符號標示來說明。此外，附圖僅以說明為目的，並未依照原尺寸作圖。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。The following is a detailed description of the embodiments and accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be indicated by the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clarity.

圖1A至圖1R為根據本發明的一些實施例的電晶體元件的製造流程剖面圖。1A to 1R are cross-sectional views of the manufacturing process of transistor devices according to some embodiments of the present invention.

請參照圖1A，提供基底結構100。基底結構100可包括基底100a與半導體層100b。基底100a可具有第一導電型(如，N型)。以下，第一導電型與第二導電型可分別為N型導電型與P型導電型中的一者與另一者。在本實施例中，第一導電型是以N型導電型為例，且第二導電型是以P型導電型為例，但本發明並不以此為限。在另一些實施例中，第一導電型可為P型導電型，且第二導電型可為N型導電型。在一些實施例中，基底100a可為半導體基底，如矽基底。Referring to FIG. 1A , a substrate structure 100 is provided. The substrate structure 100 may include a substrate 100a and a semiconductor layer 100b. The substrate 100a may have a first conductivity type (e.g., N-type). Hereinafter, the first conductivity type and the second conductivity type may be one and the other of an N-type conductivity type and a P-type conductivity type, respectively. In the present embodiment, the first conductivity type is an N-type conductivity type, and the second conductivity type is an P-type conductivity type, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type. In some embodiments, the substrate 100a may be a semiconductor substrate, such as a silicon substrate.

半導體層100b設置在基底100a上。在一些實施例中，半導體層100b可為磊晶層。在一些實施例中，半導體層100b的材料可為磊晶矽。在一些實施例中，在半導體層100b中可具有摻雜區100c。摻雜區100c可具有第一導電型(如，N型)。The semiconductor layer 100b is disposed on the substrate 100a. In some embodiments, the semiconductor layer 100b may be an epitaxial layer. In some embodiments, the material of the semiconductor layer 100b may be epitaxial silicon. In some embodiments, a doped region 100c may be provided in the semiconductor layer 100b. The doped region 100c may have a first conductivity type (e.g., N-type).

接著，在基底結構100中形成溝渠T。在一些實施例中，溝渠T可形成在半導體層100b中。在一些實施例中，可藉由微影製程與蝕刻製程對基底結構100進行圖案化來形成溝渠T。Next, a trench T is formed in the base structure 100. In some embodiments, the trench T may be formed in the semiconductor layer 100b. In some embodiments, the trench T may be formed by patterning the base structure 100 through a lithography process and an etching process.

請參照圖1B，可在基底結構100上形成介電材料層102。在一些實施例中，介電材料層102的材料例如是氧化矽。在一些實施例中，介電材料層102的形成方法例如是熱氧化法。1B , a dielectric material layer 102 may be formed on the substrate structure 100. In some embodiments, the material of the dielectric material layer 102 is, for example, silicon oxide. In some embodiments, the dielectric material layer 102 is formed by, for example, thermal oxidation.

請參照圖1C，可在介電材料層102上形成屏蔽電極材料層104。屏蔽電極材料層104填入溝渠T。在一些實施例中，屏蔽電極材料層104的材料例如是摻雜多晶矽。在一些實施例中，屏蔽電極材料層104的形成方法例如是化學氣相沉積法。1C , a shielding electrode material layer 104 may be formed on the dielectric material layer 102. The shielding electrode material layer 104 fills the trench T. In some embodiments, the material of the shielding electrode material layer 104 is, for example, doped polysilicon. In some embodiments, the shielding electrode material layer 104 is formed by, for example, chemical vapor deposition.

接著，可移除部分屏蔽電極材料層104，而暴露出部分介電材料層102。在一些實施例中，可利用介電材料層102作為研磨終止層，對屏蔽電極材料層104進行化學機械研磨製程，而移除部分屏蔽電極材料層104，且暴露出部分介電材料層102。Next, a portion of the shielding electrode material layer 104 may be removed to expose a portion of the dielectric material layer 102. In some embodiments, the dielectric material layer 102 may be used as a polishing stop layer, and a chemical mechanical polishing process may be performed on the shielding electrode material layer 104 to remove a portion of the shielding electrode material layer 104 and expose a portion of the dielectric material layer 102.

請參照圖1D，可移除部分屏蔽電極材料層104，而形成屏蔽電極104a。藉此，可在溝渠T中形成屏蔽電極104a。在一些實施例中，屏蔽電極104a的材料例如是摻雜多晶矽。在一些實施例中，部分屏蔽電極材料層104的移除方法例如是乾式蝕刻法。1D , a portion of the shielding electrode material layer 104 may be removed to form a shielding electrode 104a. Thus, the shielding electrode 104a may be formed in the trench T. In some embodiments, the material of the shielding electrode 104a is, for example, doped polysilicon. In some embodiments, the method of removing a portion of the shielding electrode material layer 104 is, for example, dry etching.

接著，可移除部分介電材料層102，而形成介電層102a。藉此，可在屏蔽電極104a與基底結構100之間形成介電層102a。在一些實施例中，介電層102a的材料例如是氧化矽。在一些實施例中，部分介電材料層102的移除方法例如是濕式蝕刻法。Next, a portion of the dielectric material layer 102 may be removed to form a dielectric layer 102a. Thus, the dielectric layer 102a may be formed between the shielding electrode 104a and the substrate structure 100. In some embodiments, the material of the dielectric layer 102a is, for example, silicon oxide. In some embodiments, the method of removing a portion of the dielectric material layer 102 is, for example, wet etching.

請參照圖1E，可在基底結構100上形成墊材料層106。在一些實施例中，墊材料層106可形成在基底結構100的未被介電層102a所覆蓋的表面上。在一些實施例中，墊材料層106可形成在半導體層100b的未被介電層102a所覆蓋的表面上。在一些實施例中，墊材料層106更可形成在屏蔽電極104a上。在一些實施例中，墊材料層106的材料例如是氧化矽。在一些實施例中，墊材料層106的形成方法例如是熱氧化法。1E , a pad material layer 106 may be formed on the base structure 100. In some embodiments, the pad material layer 106 may be formed on the surface of the base structure 100 that is not covered by the dielectric layer 102a. In some embodiments, the pad material layer 106 may be formed on the surface of the semiconductor layer 100b that is not covered by the dielectric layer 102a. In some embodiments, the pad material layer 106 may be further formed on the shielding electrode 104a. In some embodiments, the material of the pad material layer 106 is, for example, silicon oxide. In some embodiments, the pad material layer 106 is formed by, for example, thermal oxidation.

接著，可在墊材料層106與介電層102a上形成矽間隙壁材料層108。在一些實施例中，矽間隙壁材料層108可共形地形成在墊材料層106與介電層102a上。在一些實施例中，矽間隙壁材料層108的材料例如是多晶矽。在一些實施例中，矽間隙壁材料層108的形成方法例如是化學氣相沉積法。Next, a silicon spacer material layer 108 may be formed on the pad material layer 106 and the dielectric layer 102a. In some embodiments, the silicon spacer material layer 108 may be conformally formed on the pad material layer 106 and the dielectric layer 102a. In some embodiments, the material of the silicon spacer material layer 108 is, for example, polysilicon. In some embodiments, the method of forming the silicon spacer material layer 108 is, for example, chemical vapor deposition.

請參照圖1F，可在矽間隙壁材料層108上形成間隙壁材料層110。在一些實施例中，間隙壁材料層110可共形地形成在矽間隙壁材料層108上。在一些實施例中，間隙壁材料層110的材料例如是氮化矽。在一些實施例中，間隙壁材料層110的形成方法例如是化學氣相沉積法。1F , a spacer material layer 110 may be formed on the silicon spacer material layer 108. In some embodiments, the spacer material layer 110 may be conformally formed on the silicon spacer material layer 108. In some embodiments, the material of the spacer material layer 110 is, for example, silicon nitride. In some embodiments, the spacer material layer 110 may be formed by, for example, chemical vapor deposition.

請參照圖1G，可移除部分間隙壁材料層110，而形成間隙壁110a。藉此，可在矽間隙壁材料層108上形成間隙壁110a。在一些實施例中，間隙壁110a的材料例如是氮化矽。在一些實施例中，部分間隙壁材料層110的移除方法例如是乾式蝕刻法。1G, a portion of the spacer material layer 110 may be removed to form a spacer 110a. Thus, the spacer 110a may be formed on the silicon spacer material layer 108. In some embodiments, the material of the spacer 110a is, for example, silicon nitride. In some embodiments, the method of removing a portion of the spacer material layer 110 is, for example, dry etching.

請參照圖1H，可移除部分矽間隙壁材料層108，而形成矽間隙壁108a。藉此，可在溝渠T的側壁SW1上形成矽間隙壁108a。在一些實施例中，矽間隙壁108a可形成在墊材料層106上。在一些實施例中，矽間隙壁108a可位在介電層102a上。在一些實施例中，矽間隙壁108a的頂面S2可低於基底結構100的頂面S1(如，半導體層100b的頂面S1)。在一些實施例中，矽間隙壁108a的底部BP可在介電層102a的頂面S3上延伸。在一些實施例中，間隙壁110a可位在矽間隙壁108a的底部BP與矽間隙壁108a的側壁SW2上。在一些實施例中，矽間隙壁108a的材料例如是多晶矽。在一些實施例中，部分矽間隙壁材料層108的移除方法例如是乾式蝕刻法。1H, a portion of the silicon spacer material layer 108 may be removed to form a silicon spacer 108a. Thus, the silicon spacer 108a may be formed on the sidewall SW1 of the trench T. In some embodiments, the silicon spacer 108a may be formed on the pad material layer 106. In some embodiments, the silicon spacer 108a may be located on the dielectric layer 102a. In some embodiments, the top surface S2 of the silicon spacer 108a may be lower than the top surface S1 of the base structure 100 (e.g., the top surface S1 of the semiconductor layer 100b). In some embodiments, the bottom BP of the silicon spacer 108a may extend on the top surface S3 of the dielectric layer 102a. In some embodiments, the spacer 110a may be located on the bottom BP of the silicon spacer 108a and the sidewall SW2 of the silicon spacer 108a. In some embodiments, the material of the silicon spacer 108a is, for example, polysilicon. In some embodiments, the method of removing part of the silicon spacer material layer 108 is, for example, dry etching.

請參照圖1I，可移除間隙壁110a。間隙壁110a的移除方例如是濕式蝕刻法。1I , the spacer 110 a may be removed. The spacer 110 a may be removed by, for example, wet etching.

請參照圖1J，可在墊材料層106、矽間隙壁108a與介電層102a上形成間隙壁材料層112。在一些實施例中，間隙壁材料層112可共形地形成在墊材料層106、矽間隙壁108a與介電層102a上。在一些實施例中，間隙壁材料層112的材料例如是氮化矽。在一些實施例中，間隙壁材料層112的形成方法例如是化學氣相沉積法。1J, a spacer material layer 112 may be formed on the pad material layer 106, the silicon spacer 108a, and the dielectric layer 102a. In some embodiments, the spacer material layer 112 may be conformally formed on the pad material layer 106, the silicon spacer 108a, and the dielectric layer 102a. In some embodiments, the material of the spacer material layer 112 is, for example, silicon nitride. In some embodiments, the spacer material layer 112 may be formed by, for example, chemical vapor deposition.

請參照圖1K，可移除部分間隙壁材料層112，而形成間隙壁112a。藉此，可在矽間隙壁108a上形成間隙壁112a。在一些實施例中，間隙壁112a可位在矽間隙壁108a的頂面S2、矽間隙壁108a的側壁SW2與矽間隙壁108a的底部BP上。在一些實施例中，間隙壁112a可暴露出矽間隙壁108a的底部BP。舉例來說，間隙壁112a可暴露出矽間隙壁108a的底部BP的側面。在一些實施例中，間隙壁112a的材料例如是氮化矽。部分間隙壁材料層112的移除方法例如是乾式蝕刻法。Referring to FIG. 1K , a portion of the spacer material layer 112 may be removed to form a spacer 112a. Thus, the spacer 112a may be formed on the silicon spacer 108a. In some embodiments, the spacer 112a may be located on the top surface S2 of the silicon spacer 108a, the side wall SW2 of the silicon spacer 108a, and the bottom BP of the silicon spacer 108a. In some embodiments, the spacer 112a may expose the bottom BP of the silicon spacer 108a. For example, the spacer 112a may expose the side of the bottom BP of the silicon spacer 108a. In some embodiments, the material of the spacer 112a is, for example, silicon nitride. The method for removing a portion of the spacer material layer 112 is, for example, dry etching.

在一些實施例中，在移除部分間隙壁材料層112的製程(如，乾式蝕刻製程)中，可同時移除位在基底結構100的頂面S1(如，半導體層100b的頂面S1)上的墊材料層106以及位在屏蔽電極104a上的墊材料層106，而形成墊層106a，且暴露出基底結構100的頂面S1與屏蔽電極104a。藉此，可在溝渠T的側壁SW1上形成墊層106a。在一些實施例中，墊層106a可位在矽間隙壁108a與溝渠T的側壁SW1之間。在一些實施例中，墊層106a的材料例如是氧化矽。In some embodiments, in a process (e.g., dry etching process) of removing a portion of the spacer material layer 112, the pad material layer 106 on the top surface S1 of the substrate structure 100 (e.g., the top surface S1 of the semiconductor layer 100b) and the pad material layer 106 on the shielding electrode 104a may be removed simultaneously to form a pad layer 106a, and expose the top surface S1 of the substrate structure 100 and the shielding electrode 104a. Thus, the pad layer 106a may be formed on the sidewall SW1 of the trench T. In some embodiments, the pad layer 106a may be located between the silicon spacer 108a and the sidewall SW1 of the trench T. In some embodiments, the material of the pad layer 106a is, for example, silicon oxide.

請參照圖1L，可對由間隙壁112a所暴露出的矽間隙壁108a的底部BP進行熱氧化製程，而形成介電層114。在一些實施例中，介電層114可形成在介電層102a與墊層106a上。在一些實施例中，介電層114的材料例如是氧化矽。舉例來說，當矽間隙壁108a的材料為多晶矽時，可藉由對由間隙壁112a所暴露出的矽間隙壁108a的底部BP進行熱氧化製程來形成材料為氧化矽的介電層114。1L, a thermal oxidation process may be performed on the bottom BP of the silicon spacer 108a exposed by the spacer 112a to form a dielectric layer 114. In some embodiments, the dielectric layer 114 may be formed on the dielectric layer 102a and the pad layer 106a. In some embodiments, the material of the dielectric layer 114 is, for example, silicon oxide. For example, when the material of the silicon spacer 108a is polysilicon, a thermal oxidation process may be performed on the bottom BP of the silicon spacer 108a exposed by the spacer 112a to form the dielectric layer 114 whose material is silicon oxide.

在一些實施例中，可對屏蔽電極104a進行熱氧化製程，而在屏蔽電極104a上形成介電層116。在一些實施例中，介電層114與介電層116可彼此分離。在一些實施例中，介電層116的材料例如是氧化矽。舉例來說，當屏蔽電極104a的材料為摻雜多晶矽時，可藉由對屏蔽電極104a進行熱氧化製程來形成材料為氧化矽的介電層116。在一些實施例中，介電層114與介電層116可藉由同一道熱氧化製程來同時形成。In some embodiments, a thermal oxidation process may be performed on the shielding electrode 104a to form a dielectric layer 116 on the shielding electrode 104a. In some embodiments, the dielectric layer 114 and the dielectric layer 116 may be separated from each other. In some embodiments, the material of the dielectric layer 116 is, for example, silicon oxide. For example, when the material of the shielding electrode 104a is doped polysilicon, the dielectric layer 116 whose material is silicon oxide may be formed by performing a thermal oxidation process on the shielding electrode 104a. In some embodiments, the dielectric layer 114 and the dielectric layer 116 may be formed simultaneously by the same thermal oxidation process.

在一些實施例中，可對基底結構100進行熱氧化製程，而在基底結構100的頂面S1上形成介電層118。在一些實施例中，可對半導體層100b進行熱氧化製程，而在半導體層100b的頂面S1上形成介電層118。在一些實施例中，介電層114與介電層118可彼此分離。在一些實施例中，介電層116與介電層118可彼此分離。在一些實施例中，介電層114、介電層116與介電層118可彼此分離。在一些實施例中，介電層118的材料例如是氧化矽。舉例來說，當半導體層100b的材料為磊晶矽時，可藉由對半導體層100b進行熱氧化製程來形成材料為氧化矽的介電層118。在一些實施例中，介電層114與介電層118可藉由同一道熱氧化製程來同時形成。在一些實施例中，介電層116與介電層118可藉由同一道熱氧化製程來同時形成。在一些實施例中，介電層114、介電層116與介電層118可藉由同一道熱氧化製程來同時形成。In some embodiments, a thermal oxidation process may be performed on the base structure 100 to form a dielectric layer 118 on the top surface S1 of the base structure 100. In some embodiments, a thermal oxidation process may be performed on the semiconductor layer 100b to form a dielectric layer 118 on the top surface S1 of the semiconductor layer 100b. In some embodiments, the dielectric layer 114 and the dielectric layer 118 may be separated from each other. In some embodiments, the dielectric layer 116 and the dielectric layer 118 may be separated from each other. In some embodiments, the dielectric layer 114, the dielectric layer 116, and the dielectric layer 118 may be separated from each other. In some embodiments, the material of the dielectric layer 118 is, for example, silicon oxide. For example, when the material of the semiconductor layer 100b is epitaxial silicon, the dielectric layer 118 made of silicon oxide can be formed by performing a thermal oxidation process on the semiconductor layer 100b. In some embodiments, the dielectric layer 114 and the dielectric layer 118 can be formed simultaneously by the same thermal oxidation process. In some embodiments, the dielectric layer 116 and the dielectric layer 118 can be formed simultaneously by the same thermal oxidation process. In some embodiments, the dielectric layer 114, the dielectric layer 116, and the dielectric layer 118 can be formed simultaneously by the same thermal oxidation process.

請參照圖1M，可移除間隙壁112a。間隙壁112a的移除方法例如是濕式蝕刻法。接著，可移除矽間隙壁108a。矽間隙壁108a的移除方法例如是濕式蝕刻法。1M, the spacer 112a may be removed. The spacer 112a may be removed by, for example, wet etching. Then, the silicon spacer 108a may be removed. The silicon spacer 108a may be removed by, for example, wet etching.

請參照圖1N，可在介電層118、墊層106a、介電層114、介電層102a與介電層116上形成介電材料層120。在一些實施例中，介電材料層120可共形地形成在介電層118、墊層106a、介電層114、介電層102a與介電層116上。在一些實施例中，介電材料層120的材料例如是氧化矽。在一些實施例中，介電材料層120的形成方法例如是化學氣相沉積法。1N , a dielectric material layer 120 may be formed on the dielectric layer 118, the pad layer 106a, the dielectric layer 114, the dielectric layer 102a, and the dielectric layer 116. In some embodiments, the dielectric material layer 120 may be conformally formed on the dielectric layer 118, the pad layer 106a, the dielectric layer 114, the dielectric layer 102a, and the dielectric layer 116. In some embodiments, the material of the dielectric material layer 120 is, for example, silicon oxide. In some embodiments, the dielectric material layer 120 may be formed by, for example, chemical vapor deposition.

請參照圖1O，在溝渠T中與屏蔽電極104a上形成閘極122。在一些實施例中，閘極122可形成在介電材料層120上。在一些實施例中，閘極122的材料例如是摻雜多晶矽。在一些實施例中，閘極122的形成方法可包括以下步驟。首先，可在介電材料層120上形成填入溝渠T的閘極材料層(未示出)。接著，可移除部分閘極材料層，而形成閘極122，且暴露出介電材料層120。部分閘極材料層的移除方法例如是化學機械研磨製程或回蝕刻製程。Referring to FIG. 1O , a gate 122 is formed in the trench T and on the shielding electrode 104 a. In some embodiments, the gate 122 may be formed on the dielectric material layer 120. In some embodiments, the material of the gate 122 is, for example, doped polysilicon. In some embodiments, the method for forming the gate 122 may include the following steps. First, a gate material layer (not shown) filling the trench T may be formed on the dielectric material layer 120. Then, a portion of the gate material layer may be removed to form the gate 122, and the dielectric material layer 120 may be exposed. The method for removing a portion of the gate material layer is, for example, a chemical mechanical polishing process or an etching back process.

請參照圖1P，可移除部分介電材料層120與介電層118，而形成介電層120a，且暴露出基底結構100的頂面S1。在一些實施例中，介電層120a可形成在介電層102a、墊層106a與介電層116上。藉由上述方法，可在閘極122與基底結構100之間以及閘極122與屏蔽電極104a之間形成閘極介電層124。閘極介電層124包括介電層114與介電層120a。介電層114設置在閘極122的底部的轉角與基底結構100之間。介電層120a設置在閘極122與基底結構100之間、閘極122與介電層114之間以及閘極122與屏蔽電極104a之間。在一些實施例中，介電層120a更可設置在閘極122與介電層102a之間。此外，介電層124更可包括墊層106a。墊層106a設置在介電層114與基底結構100之間以及介電層120a與基底結構100之間。在一些實施例中，介電層120a的材料例如是氧化矽。在一些實施例中，部分介電材料層120與介電層118的移除方法例如是乾式蝕刻法。1P, a portion of the dielectric material layer 120 and the dielectric layer 118 may be removed to form a dielectric layer 120a, and the top surface S1 of the substrate structure 100 is exposed. In some embodiments, the dielectric layer 120a may be formed on the dielectric layer 102a, the pad layer 106a, and the dielectric layer 116. By the above method, a gate dielectric layer 124 may be formed between the gate 122 and the substrate structure 100 and between the gate 122 and the shielding electrode 104a. The gate dielectric layer 124 includes the dielectric layer 114 and the dielectric layer 120a. The dielectric layer 114 is disposed between the bottom corner of the gate 122 and the substrate structure 100. The dielectric layer 120a is disposed between the gate 122 and the substrate structure 100, between the gate 122 and the dielectric layer 114, and between the gate 122 and the shielding electrode 104a. In some embodiments, the dielectric layer 120a may be further disposed between the gate 122 and the dielectric layer 102a. In addition, the dielectric layer 124 may further include a pad layer 106a. The pad layer 106a is disposed between the dielectric layer 114 and the substrate structure 100, and between the dielectric layer 120a and the substrate structure 100. In some embodiments, the material of the dielectric layer 120a is, for example, silicon oxide. In some embodiments, a method for removing portions of the dielectric material layer 120 and the dielectric layer 118 is, for example, dry etching.

請參照圖1Q，可在基底結構100的頂面S1上形成介電層126。在一些實施例中，介電層126可形成在半導體層100b的頂面S1上。在一些實施例中，介電層126的材料例如是氧化矽。在一些實施例中，介電層126的形成方法例如是熱氧化法。1Q, a dielectric layer 126 may be formed on the top surface S1 of the substrate structure 100. In some embodiments, the dielectric layer 126 may be formed on the top surface S1 of the semiconductor layer 100b. In some embodiments, the material of the dielectric layer 126 is, for example, silicon oxide. In some embodiments, the dielectric layer 126 may be formed by, for example, thermal oxidation.

此外，可在閘極122的頂面S4上形成介電層128。在一些實施例中，介電層128的材料例如是氧化矽。在一些實施例中，介電層128的形成方法例如是熱氧化法。在一些實施例中，介電層126與介電層128可藉由同一道熱氧化製程來同時形成。In addition, a dielectric layer 128 may be formed on the top surface S4 of the gate 122. In some embodiments, the material of the dielectric layer 128 is, for example, silicon oxide. In some embodiments, the dielectric layer 128 is formed by, for example, thermal oxidation. In some embodiments, the dielectric layer 126 and the dielectric layer 128 may be formed simultaneously by the same thermal oxidation process.

接著，可在閘極122旁邊的基底結構100中形成基體區130。在一些實施例中，基體區130可形成在閘極122旁邊的半導體層100b中。在一些實施例中，基體區130可具有第二導電型(如，P型)。基體區130的形成方法例如是離子植入法。Next, a base region 130 may be formed in the substrate structure 100 next to the gate 122. In some embodiments, the base region 130 may be formed in the semiconductor layer 100b next to the gate 122. In some embodiments, the base region 130 may have a second conductivity type (e.g., P type). The base region 130 may be formed by, for example, ion implantation.

此外，可在閘極122旁邊的基底結構100中形成摻雜區132。在一些實施例中，摻雜區132可形成在閘極122旁邊的半導體層100b中。在一些實施例中，基體區130可位在摻雜區132與摻雜區100c之間。在一些實施例中，摻雜區132可具有第一導電型(如，N型)。摻雜區132的形成方法例如是離子植入法。In addition, a doped region 132 may be formed in the base structure 100 next to the gate 122. In some embodiments, the doped region 132 may be formed in the semiconductor layer 100b next to the gate 122. In some embodiments, the base region 130 may be located between the doped region 132 and the doped region 100c. In some embodiments, the doped region 132 may have a first conductivity type (e.g., N-type). The doped region 132 may be formed by, for example, ion implantation.

請參照圖1R，可在介電層120a、介電層126與介電層128上形成介電層134。介電層134的材料例如是氧化矽。介電層134的形成方法例如是化學氣相沉積法。1R, a dielectric layer 134 may be formed on the dielectric layer 120a, the dielectric layer 126, and the dielectric layer 128. The material of the dielectric layer 134 is, for example, silicon oxide. The method of forming the dielectric layer 134 is, for example, chemical vapor deposition.

接著，可在介電層134中形成接觸窗136與接觸窗138。接觸窗136連接至摻雜區132。在一些實施例中，接觸窗136更可連接至基體區130。在一些實施例中，接觸窗136可穿過介電層126與摻雜區132而延伸至基體區130中。接觸窗136的材料例如是鎢。在一些實施例中，接觸窗136可藉由鑲嵌製程(damascene process)來形成。Next, a contact window 136 and a contact window 138 may be formed in the dielectric layer 134. The contact window 136 is connected to the doped region 132. In some embodiments, the contact window 136 may be further connected to the base region 130. In some embodiments, the contact window 136 may extend into the base region 130 through the dielectric layer 126 and the doped region 132. The material of the contact window 136 is, for example, tungsten. In some embodiments, the contact window 136 may be formed by a damascene process.

接觸窗138連接至閘極122。在一些實施例中，接觸窗138可穿過介電層128而延伸至閘極122中。接觸窗138的材料例如是鎢。在一些實施例中，接觸窗138可藉由鑲嵌製程來形成。在一些實施例中，接觸窗136與接觸窗138可同時形成。The contact window 138 is connected to the gate 122. In some embodiments, the contact window 138 may extend into the gate 122 through the dielectric layer 128. The material of the contact window 138 is, for example, tungsten. In some embodiments, the contact window 138 may be formed by a damascene process. In some embodiments, the contact window 136 and the contact window 138 may be formed simultaneously.

以下，藉由圖1R來說明上述實施例的電晶體元件10。此外，雖然電晶體元件10的形成方法是以上述方法為例來進行說明，但本發明並不以此為限。1R is used to illustrate the transistor device 10 of the above embodiment. In addition, although the method for forming the transistor device 10 is described using the above method as an example, the present invention is not limited thereto.

請參照圖1R，電晶體元件10包括基底結構100、屏蔽電極104a、介電層102a、閘極122與閘極介電層124。在一些實施例中，電晶體元件10可為屏蔽閘極溝渠式電晶體。在基底結構100中具有溝渠T。基底結構100可包括基底100a與半導體層100b。在一些實施例中，基底100a可具有第一導電型(如，N型)。半導體層100b設置在基底100a上。溝渠T位在半導體層100b中。1R, the transistor element 10 includes a substrate structure 100, a shielding electrode 104a, a dielectric layer 102a, a gate 122, and a gate dielectric layer 124. In some embodiments, the transistor element 10 may be a shielding gate trench transistor. A trench T is provided in the substrate structure 100. The substrate structure 100 may include a substrate 100a and a semiconductor layer 100b. In some embodiments, the substrate 100a may have a first conductivity type (e.g., N-type). The semiconductor layer 100b is disposed on the substrate 100a. The trench T is located in the semiconductor layer 100b.

屏蔽電極104a設置在溝渠T中。介電層102a設置在屏蔽電極104a與基底結構100之間。閘極122設置在溝渠T中與屏蔽電極104a上。閘極介電層124設置在閘極122與基底結構100之間以及閘極122與屏蔽電極104a之間。閘極介電層124包括介電層114與介電層120a。介電層114設置在閘極122的底部的轉角與基底結構100之間。在一些實施例中，介電層114可設置在介電層102a的頂面S3上。介電層120a設置在閘極122與基底結構100之間、閘極122與介電層114之間以及閘極122與屏蔽電極104a之間。在一些實施例中，介電層120a更可設置在閘極122與介電層102a之間。此外，介電層124更可包括墊層106a。墊層106a設置在介電層114與基底結構100之間以及介電層120a與基底結構100之間。The shielding electrode 104a is disposed in the trench T. The dielectric layer 102a is disposed between the shielding electrode 104a and the base structure 100. The gate 122 is disposed in the trench T and on the shielding electrode 104a. The gate dielectric layer 124 is disposed between the gate 122 and the base structure 100 and between the gate 122 and the shielding electrode 104a. The gate dielectric layer 124 includes a dielectric layer 114 and a dielectric layer 120a. The dielectric layer 114 is disposed between the bottom corner of the gate 122 and the base structure 100. In some embodiments, the dielectric layer 114 may be disposed on the top surface S3 of the dielectric layer 102a. The dielectric layer 120a is disposed between the gate 122 and the substrate structure 100, between the gate 122 and the dielectric layer 114, and between the gate 122 and the shielding electrode 104a. In some embodiments, the dielectric layer 120a may be further disposed between the gate 122 and the dielectric layer 102a. In addition, the dielectric layer 124 may further include a pad layer 106a. The pad layer 106a is disposed between the dielectric layer 114 and the substrate structure 100, and between the dielectric layer 120a and the substrate structure 100.

電晶體元件10更可包括介電層116。介電層116設置在介電層120a與屏蔽電極104a之間。在一些實施例中，介電層114與介電層116可彼此分離。The transistor device 10 may further include a dielectric layer 116. The dielectric layer 116 is disposed between the dielectric layer 120a and the shielding electrode 104a. In some embodiments, the dielectric layer 114 and the dielectric layer 116 may be separated from each other.

電晶體元件10更可包括摻雜區132、摻雜區100c與基體區130。摻雜區132設置在閘極122旁邊的基底結構100中。在一些實施例中，摻雜區132可設置在閘極122旁邊的半導體層100b中。在一些實施例中，摻雜區132可用以作為源極區。在一些實施例中，摻雜區132可具有第一導電型(如，N型)。在一些實施例中，屏蔽電極104a可藉由內連線結構(未示出)電性連接至摻雜區132。The transistor device 10 may further include a doped region 132, a doped region 100c, and a base region 130. The doped region 132 is disposed in the base structure 100 next to the gate 122. In some embodiments, the doped region 132 may be disposed in the semiconductor layer 100b next to the gate 122. In some embodiments, the doped region 132 may be used as a source region. In some embodiments, the doped region 132 may have a first conductivity type (e.g., N-type). In some embodiments, the shielding electrode 104a may be electrically connected to the doped region 132 via an internal connection structure (not shown).

摻雜區100c設置在摻雜區132下方的基底結構100中。摻雜區100c更可設置在介電層102a與屏蔽電極104a下方的基底結構100中。在一些實施例中，摻雜區100c可設置在摻雜區132、介電層102a與屏蔽電極104a下方的半導體層100b中。在一些實施例中，摻雜區100c可用以作為汲極區。在一些實施例中，摻雜區100c可具有第一導電型(如，N型)。The doped region 100c is disposed in the substrate structure 100 below the doped region 132. The doped region 100c may be further disposed in the substrate structure 100 below the dielectric layer 102a and the shielding electrode 104a. In some embodiments, the doped region 100c may be disposed in the semiconductor layer 100b below the doped region 132, the dielectric layer 102a and the shielding electrode 104a. In some embodiments, the doped region 100c may be used as a drain region. In some embodiments, the doped region 100c may have a first conductivity type (e.g., N-type).

基體區130設置在摻雜區132與摻雜區100c之間的基底結構100中。在一些實施例中，基體區130可設置在摻雜區132與摻雜區100c之間的半導體層100b中。在一些實施例中，基體區130可具有第二導電型(如，P型)。The base region 130 is disposed in the substrate structure 100 between the doped region 132 and the doped region 100c. In some embodiments, the base region 130 may be disposed in the semiconductor layer 100b between the doped region 132 and the doped region 100c. In some embodiments, the base region 130 may have a second conductivity type (eg, P type).

電晶體元件10更可包括介電層126與介電層128。介電層126設置在基底結構100的頂面S1(如，半導體層100b的頂面S1)上。介電層128設置在閘極122的頂面S4上。The transistor device 10 may further include a dielectric layer 126 and a dielectric layer 128. The dielectric layer 126 is disposed on the top surface S1 of the substrate structure 100 (eg, the top surface S1 of the semiconductor layer 100b). The dielectric layer 128 is disposed on the top surface S4 of the gate 122.

電晶體元件10更可包括介電層134、接觸窗136與接觸窗138。介電層134設置在閘極介電層124、介電層126與介電層128上。接觸窗136設置在介電層134中且連接至摻雜區132。在一些實施例中，接觸窗136更可連接至基體區130。在一些實施例中，接觸窗136可穿過介電層126與摻雜區132而延伸至基體區130中。接觸窗138設置在介電層134中且連接至閘極122。在一些實施例中，接觸窗138可穿過介電層128而延伸至閘極122中。The transistor device 10 may further include a dielectric layer 134, a contact window 136, and a contact window 138. The dielectric layer 134 is disposed on the gate dielectric layer 124, the dielectric layer 126, and the dielectric layer 128. The contact window 136 is disposed in the dielectric layer 134 and connected to the doped region 132. In some embodiments, the contact window 136 may be further connected to the body region 130. In some embodiments, the contact window 136 may extend through the dielectric layer 126 and the doped region 132 into the body region 130. The contact window 138 is disposed in the dielectric layer 134 and connected to the gate 122. In some embodiments, the contact window 138 may extend through the dielectric layer 128 into the gate 122 .

此外，電晶體元件10中的各構件的詳細內容(如，材料與形成方法等)已於上述實施例進行詳盡地說明，於此不再說明。In addition, the details of each component in the transistor element 10 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again here.

基於上述實施例可知，在電晶體元件10及其製造方法中，由於介電層114設置在閘極122的底部的轉角與基底結構100之間，因此可增加位在閘極122的底部的轉角處的閘極介電層124的厚度。如此一來，可有效地防止閘極介電層124被擊穿，進而防止電晶體元件10失效。此外，由於介電層114設置在閘極122的底部的轉角與基底結構100之間，所以可彈性地調整介電層120a的厚度，藉此可彈性地調整電晶體元件10的臨界電壓。Based on the above embodiments, it can be known that in the transistor device 10 and the manufacturing method thereof, since the dielectric layer 114 is disposed between the corner of the bottom of the gate 122 and the base structure 100, the thickness of the gate dielectric layer 124 at the corner of the bottom of the gate 122 can be increased. In this way, the gate dielectric layer 124 can be effectively prevented from being broken down, thereby preventing the transistor device 10 from failing. In addition, since the dielectric layer 114 is disposed between the corner of the bottom of the gate 122 and the base structure 100, the thickness of the dielectric layer 120a can be flexibly adjusted, thereby flexibly adjusting the critical voltage of the transistor device 10.

綜上所述，在上述實施例的電晶體元件及其製造方法中，第一介電層設置在屏蔽電極與基底結構之間。閘極介電層設置在閘極與基底結構之間以及閘極與屏蔽電極之間。閘極介電層包括第二介電層與第三介電層。第二介電層設置在閘極的底部的轉角與基底結構之間。第三介電層設置在閘極與基底結構之間、閘極與第二介電層之間以及閘極與屏蔽電極之間。由於第二介電層設置在閘極的底部的轉角與基底結構之間，因此可增加位在閘極的底部的轉角處的閘極介電層的厚度。如此一來，可有效地防止閘極介電層被擊穿，進而防止電晶體元件失效。此外，由於第二介電層設置在閘極的底部的轉角與基底結構之間，所以可彈性地調整第三介電層的厚度，藉此可彈性地調整電晶體元件的臨界電壓。In summary, in the transistor element and the manufacturing method thereof of the above-mentioned embodiment, the first dielectric layer is arranged between the shielding electrode and the base structure. The gate dielectric layer is arranged between the gate and the base structure and between the gate and the shielding electrode. The gate dielectric layer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is arranged between the corner of the bottom of the gate and the base structure. The third dielectric layer is arranged between the gate and the base structure, between the gate and the second dielectric layer, and between the gate and the shielding electrode. Since the second dielectric layer is disposed between the corner of the bottom of the gate and the base structure, the thickness of the gate dielectric layer at the corner of the bottom of the gate can be increased. In this way, the gate dielectric layer can be effectively prevented from being broken down, thereby preventing the transistor element from failing. In addition, since the second dielectric layer is disposed between the corner of the bottom of the gate and the base structure, the thickness of the third dielectric layer can be flexibly adjusted, thereby flexibly adjusting the critical voltage of the transistor element.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: 電晶體元件 100: 基底結構 100a: 基底 100b: 半導體層 100c, 132: 摻雜區 102, 120: 介電材料層 102a, 114, 116, 118, 120a, 126, 128, 134: 介電層 104: 屏蔽電極材料層 104a: 屏蔽電極 106: 墊材料層 106a: 墊層 108: 矽間隙壁材料層 108a: 矽間隙壁 110, 112: 間隙壁材料層 110a, 112a: 間隙壁 122: 閘極 124: 閘極介電層 130: 基體區 136, 138: 接觸窗 BP: 底部 S1, S2, S3, S4: 頂面 SW1, SW2: 側壁 T: 溝渠 10: transistor element 100: substrate structure 100a: substrate 100b: semiconductor layer 100c, 132: doped region 102, 120: dielectric material layer 102a, 114, 116, 118, 120a, 126, 128, 134: dielectric layer 104: shielding electrode material layer 104a: shielding electrode 106: pad material layer 106a: pad layer 108: silicon spacer material layer 108a: silicon spacer 110, 112: spacer material layer 110a, 112a: Spacer 122: Gate 124: Gate dielectric layer 130: Body 136, 138: Contact window BP: Bottom S1, S2, S3, S4: Top SW1, SW2: Sidewall T: Trench

圖1A至圖1R為根據本發明的一些實施例的電晶體元件的製造流程剖面圖。1A to 1R are cross-sectional views of the manufacturing process of transistor devices according to some embodiments of the present invention.

10: 電晶體元件 100: 基底結構 100a: 基底 100b: 半導體層 100c, 132: 摻雜區 102a, 114, 116, 120a, 126, 128, 134: 介電層 104a: 屏蔽電極 106a: 墊層 122: 閘極 124: 閘極介電層 130: 基體區 136, 138: 接觸窗 S1, S3, S4: 頂面 T: 溝渠 10: transistor element 100: substrate structure 100a: substrate 100b: semiconductor layer 100c, 132: doped region 102a, 114, 116, 120a, 126, 128, 134: dielectric layer 104a: shielding electrode 106a: pad layer 122: gate 124: gate dielectric layer 130: body region 136, 138: contact window S1, S3, S4: top surface T: trench

Claims (10)

一種電晶體元件，包括： 基底結構，其中在所述基底結構中具有溝渠； 屏蔽電極，設置在所述溝渠中； 第一介電層，設置在所述屏蔽電極與所述基底結構之間； 閘極，設置在所述溝渠中與所述屏蔽電極上；以及 閘極介電層，設置在所述閘極與所述基底結構之間以及所述閘極與所述屏蔽電極之間，其中所述閘極介電層包括： 第二介電層，設置在所述閘極的底部的轉角與所述基底結構之間；以及 第三介電層，設置在所述閘極與所述基底結構之間、所述閘極與所述第二介電層之間以及所述閘極與所述屏蔽電極之間。 A transistor element comprises: a substrate structure, wherein the substrate structure has a trench; a shielding electrode, disposed in the trench; a first dielectric layer, disposed between the shielding electrode and the substrate structure; a gate, disposed in the trench and on the shielding electrode; and a gate dielectric layer, disposed between the gate and the substrate structure and between the gate and the shielding electrode, wherein the gate dielectric layer comprises: a second dielectric layer, disposed between a corner of the bottom of the gate and the substrate structure; and a third dielectric layer, disposed between the gate and the substrate structure, between the gate and the second dielectric layer, and between the gate and the shielding electrode. 如請求項1所述的電晶體元件，其中所述閘極介電層更包括： 墊層，設置在所述第二介電層與所述基底結構之間以及所述第三介電層與所述基底結構之間。 The transistor element as described in claim 1, wherein the gate dielectric layer further comprises: A pad layer disposed between the second dielectric layer and the base structure and between the third dielectric layer and the base structure. 如請求項1所述的電晶體元件，更包括： 第四介電層，設置在所述第三介電層與所述屏蔽電極之間，其中所述第二介電層與所述第四介電層彼此分離。 The transistor element as described in claim 1 further comprises: A fourth dielectric layer disposed between the third dielectric layer and the shielding electrode, wherein the second dielectric layer and the fourth dielectric layer are separated from each other. 如請求項1所述的電晶體元件，更包括： 第一摻雜區，設置在所述閘極旁邊的所述基底結構中； 第二摻雜區，設置在所述第一摻雜區下方的所述基底結構中；以及 基體區，設置在所述第一摻雜區與所述第二摻雜區之間的所述基底結構中。 The transistor element as described in claim 1 further includes: a first doped region disposed in the base structure next to the gate; a second doped region disposed in the base structure below the first doped region; and a body region disposed in the base structure between the first doped region and the second doped region. 如請求項1所述的電晶體元件，其中所述基底結構包括： 基底；以及 半導體層，設置在所述基底上，其中所述溝渠位在所述半導體層中。 A transistor element as described in claim 1, wherein the substrate structure comprises: a substrate; and a semiconductor layer disposed on the substrate, wherein the trench is located in the semiconductor layer. 一種電晶體元件的製造方法，包括： 提供基底結構； 在所述基底結構中形成溝渠； 在所述溝渠中形成屏蔽電極； 在所述屏蔽電極與所述基底結構之間形成第一介電層； 在所述溝渠中與所述屏蔽電極上形成閘極；以及 在所述閘極與所述基底結構之間以及所述閘極與所述屏蔽電極之間形成閘極介電層，其中所述閘極介電層包括： 第二介電層，設置在所述閘極的底部的轉角與所述基底結構之間；以及 第三介電層，設置在所述閘極與所述基底結構之間、所述閘極與所述第二介電層之間以及所述閘極與所述屏蔽電極之間。 A method for manufacturing a transistor element, comprising: providing a substrate structure; forming a trench in the substrate structure; forming a shielding electrode in the trench; forming a first dielectric layer between the shielding electrode and the substrate structure; forming a gate in the trench and on the shielding electrode; and forming a gate dielectric layer between the gate and the substrate structure and between the gate and the shielding electrode, wherein the gate dielectric layer comprises: a second dielectric layer disposed between a corner of the bottom of the gate and the substrate structure; and a third dielectric layer disposed between the gate and the substrate structure, between the gate and the second dielectric layer, and between the gate and the shielding electrode. 如請求項6所述的電晶體元件的製造方法，其中所述第二介電層的形成方法包括： 在所述溝渠的側壁上形成矽間隙壁； 在所述矽間隙壁上形成間隙壁，其中所述間隙壁暴露出所述矽間隙壁的底部；以及 對由所述間隙壁所暴露出的所述矽間隙壁的底部進行熱氧化製程，而形成所述第二介電層。 The manufacturing method of the transistor element as described in claim 6, wherein the method for forming the second dielectric layer comprises: forming a silicon spacer on the sidewall of the trench; forming a spacer on the silicon spacer, wherein the spacer exposes the bottom of the silicon spacer; and performing a thermal oxidation process on the bottom of the silicon spacer exposed by the spacer to form the second dielectric layer. 如請求項7所述的電晶體元件的製造方法，更包括： 對所述屏蔽電極進行所述熱氧化製程，而在所述屏蔽電極上形成第四介電層。 The manufacturing method of the transistor element as described in claim 7 further includes: Performing the thermal oxidation process on the shielding electrode to form a fourth dielectric layer on the shielding electrode. 如請求項7所述的電晶體元件的製造方法，所述矽間隙壁位在所述第一介電層上，且所述矽間隙壁的頂面低於所述基底結構的頂面。In the method for manufacturing a transistor device as described in claim 7, the silicon spacer is located on the first dielectric layer, and the top surface of the silicon spacer is lower than the top surface of the base structure. 如請求項6所述的電晶體元件的製造方法，更包括： 在所述溝渠的側壁上形成墊層，其中 所述第二介電層形成在所述第一介電層與所述墊層上，且 所述第三介電層形成在所述第一介電層與所述墊層上。 The manufacturing method of the transistor element as described in claim 6 further includes: forming a pad on the sidewall of the trench, wherein the second dielectric layer is formed on the first dielectric layer and the pad, and the third dielectric layer is formed on the first dielectric layer and the pad.
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TW202027141A (en) * 2019-01-11 2020-07-16 力源半導體股份有限公司 Trench power transistor and manufacturing method of the same for enhancing voltage durability of device and providing with low conduction resistance
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* Cited by examiner, † Cited by third party
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TW201023363A (en) * 2008-09-29 2010-06-16 Fairchild Semiconductor Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
TW202027269A (en) * 2019-01-11 2020-07-16 力源半導體股份有限公司 Trench-type power transistor and manufacturing method thereof including a semiconductor substrate having at least one active portion provided with a trench gate structure
TW202027141A (en) * 2019-01-11 2020-07-16 力源半導體股份有限公司 Trench power transistor and manufacturing method of the same for enhancing voltage durability of device and providing with low conduction resistance
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