CN212085009U - Grid structure - Google Patents

Abstract

The utility model discloses a grid structure contains an active area, a first grid dielectric layer and is located on the active area, shield the layer and be located on the first grid dielectric layer and be located respectively edge part, the second grid dielectric layer conformal of grid structure both sides are located first grid dielectric layer with shield on the layer, a grid conducting layer is located on the second grid dielectric layer, wherein the second grid dielectric layer centers on grid conducting layer and a silicon nitride cap layer are located on the grid conducting layer. The utility model provides a grid dielectric layer with special design can restrain the GIDL problem, can not arouse other harmful effects simultaneously again.

Description

Grid structure

Technical Field

Embodiments of the present disclosure relate to a gate structure, and more particularly, to a gate structure having a special gate dielectric layer to suppress a gate induced drain leakage current (GIDL) effect.

Background

The Gate Induced Drain Leakage (GIDL) effect is the main off-state Leakage current of the MOSFET. The effect is originated from that when the MOSFET grid is in an off state (the NM0S grid is connected with a negative voltage, the PMOS grid is connected with a positive voltage) and the drain region is connected with a voltage (the NM0S drain region is connected with a positive voltage, and the PMOS drain region is connected with a negative voltage), an inversion layer is formed on the surface due to the fact that an energy Band at the position, close to an interface, of the overlapped part of the drain-end impurity diffusion layer and the grid is strongly bent, and a depletion layer is very narrow, so that Band-to-Band Tunneling effect occurs on conduction Band electrons and valence Band holes, and drain leakage current is formed. It is the main source of off-state leakage current and determines the lower limit of the thickness of the thin oxide layer of the gate oxide layer. When the MOS is provided with a thin gate, GIDL may cause holes to damage the gate oxide layer or be trapped by the thin gate through tunneling effect, which all may cause the performance degradation reliability of the MOSFET to be reduced. In addition to off-state leakage, gate-induced drain leakage may also cause other undesirable effects, such as hole damage to or trapping by the gate oxide layer through tunneling, resulting in MOSFET performance degradation and reliability degradation.

The conventional method for inhibiting GIDL mainly increases the thickness of a gate dielectric layer or diffuses drain-side impurities away from a gate, and obviously, in the semiconductor industry pursuing high integration, such a scheme is not beneficial to further reduction of devices and can cause other parasitic effects (such as hot carrier effect) and other adverse effects.

SUMMERY OF THE UTILITY MODEL

In view of the Gate Induced Drain Leakage (GIDL) problem encountered in the semiconductor devices described above, the present invention provides a novel gate structure and method for fabricating the same, wherein the gate structure is characterized by a special gate dielectric design to suppress the GIDL problem without causing other adverse effects.

One of the objectives of the present invention is to provide a gate structure, which comprises an active area, a first gate dielectric layer, a shielding layer, a gate conductive layer, and a silicon nitride cap layer, wherein the first gate dielectric layer is disposed on the active area, the shielding layer is disposed on the first gate dielectric layer, and the first gate dielectric layer is disposed on the shielding layer, the gate conductive layer is disposed on the second gate dielectric layer, and the second gate dielectric layer surrounds the gate conductive layer and the silicon nitride cap layer, and is disposed on the gate conductive layer.

Another aspect of the present invention is to provide a method for fabricating a gate structure, which includes providing a substrate, defining an active region on the substrate, sequentially forming a first gate dielectric layer and an interlayer dielectric layer on the substrate, forming a gate pattern in the interlayer dielectric layer and exposing the first gate dielectric layer, forming a shielding layer in the gate pattern, wherein the shielding layer is located on the first gate dielectric layer and respectively located at two sides of the gate pattern contact edges of the interlayer dielectric layer and in the gate pattern the shielding layer and exposing the first gate dielectric layer sequentially form a conformal second gate dielectric layer, a gate conductive layer and a silicon nitride cap layer.

These and other objects of the present invention will become more apparent to those skilled in the art after a reading of the following detailed description of the preferred embodiment illustrated in the various figures and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings depict some embodiments of the invention and, together with the description, serve to explain its principles. In these figures:

FIGS. 1-9 are cross-sectional views illustrating a process flow of a gate structure according to a preferred embodiment of the present disclosure;

FIG. 10 illustrates a cross-sectional view of a gate structure according to another embodiment of the present disclosure;

FIG. 11 is a cross-sectional view of a gate structure according to yet another embodiment of the present disclosure;

FIG. 12 is a cross-sectional view of a gate structure according to yet another embodiment of the present disclosure; and

FIG. 13 is a cross-sectional view of a gate structure according to yet another embodiment of the present disclosure.

Wherein the reference numerals are as follows:

100 semiconductor substrate

101 device isolation layer

101a silicon oxide liner

101b silicon nitride liner

101c silicon oxide fill layer

103 first gate dielectric layer

105 stop layer

107 interlayer dielectric layer

109 hard mask layer

111 advanced exposure patterned film

113 gate pattern

115 layer of a masking material

115a shielding layer

117 silicon nitride layer

119 second gate dielectric layer

119a second gate dielectric layer

121 barrier layer

121a barrier layer

123 metal layer

123a Metal layer

125 silicon nitride cap layer

127 grid structure

129 spacing wall

ACT active region

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, which will reference features described in order for a reader to understand and achieve a technical effect. It will be understood by the reader that the description herein is by way of illustration only and is not intended to be limiting. The various embodiments of the disclosure and the various features of the embodiments that are not mutually inconsistent can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the disclosure may be apparent to those skilled in the art without departing from the spirit and scope of the disclosure, and are intended to be included within the scope of the disclosure.

It should be readily understood by the reader that the meaning of "on …", "above …" and "above …" in this case should be read in a broad manner such that "on …" not only means "directly on" something "but also includes the meaning of" on "something with intervening features or layers therebetween, and" on … "or" above … "not only means" on "something" or "above" but also includes the meaning of "on" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Moreover, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the drawings, FIGS. 1-9 are cross-sectional views illustrating a process flow of a gate structure according to a preferred embodiment of the present disclosure.

Please refer to fig. 1. First, a semiconductor substrate 100 is provided, and a device isolation layer 101 defining an active region ACT is formed in the semiconductor substrate 100. The semiconductor substrate 100 may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The device isolation layer 101 may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling the recess between the active regions ACT with an isolation material. In an example, the device isolation layer 101 is a Shallow Trench Isolation (STI) structure, which may be composed of a silicon oxide liner layer 101a, a silicon nitride liner layer 101b, and a silicon oxide filling layer 101 c. The silicon oxide liner 101a and the silicon nitride liner 101b can prevent the shallow trench from being damaged by etching and radio frequency bias in the process of forming the device isolation layer 101. In an example, the active region ACT may be a peripheral region of the semiconductor memory device around the memory cell region, but is not limited thereto.

Refer back to fig. 1. A first gate dielectric layer 103, a stop layer 105, an interlayer dielectric layer 107, a hard mask layer 109, and an advanced exposure pattern film (APF)111 are sequentially formed on a surface of the semiconductor substrate 100. The first gate dielectric layer 103 may be a silicon oxide layer, which may be formed by an in-situ steam generation (ISSG) process, and the thickness of the first gate dielectric layer 103 may be different from the thickness of the first gate dielectric layer 103 on the active region ACT and the device isolation layer 101. The stop layer 105 may be a silicon nitride layer formed by an atomic layer deposition process. The ILD 107 may be a spin-on-dielectric (SOD), the hard mask layer 109 may be a silicon nitride layer, and the first-exposure-pattern film 111 may be an amorphous carbon mask.

Please refer to fig. 2. A photolithography process is performed to form a gate pattern 113 in the interlayer dielectric layer 107. The steps of the photolithography process may include: a photolithography mask, which may be a composite mask, may be formed on the advanced exposure patterning film 111, and may include a layer structure of an Organic Dielectric Layer (ODL), an anti-reflective coating (ARC), and a photoresist layer (PR) having a gate pattern defined therein, and then an etching process is performed using the photolithography mask as an etching mask and the stop layer 105 as an etching stop layer to remove portions of the hard mask layer 109 and the interlayer dielectric layer 107, thereby forming a gate pattern 113 in the interlayer dielectric layer 107. An etching process may be performed to remove the stop layer 105 in the gate pattern 113 to expose the first gate dielectric layer 103.

Please refer to fig. 3. After forming the gate pattern 113 in the interlayer dielectric layer 107, a shielding material layer 115 is formed on the first gate dielectric layer 103. The step of forming the masking material layer 115 may include performing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form the masking material layer 115, which may be undoped amorphous silicon, on the substrate surface, wherein the masking material layer 115 covers the ild layer 107 and fills the space in the gate pattern 113. A Chemical Mechanical Polishing (CMP) process may be further included to planarize the formed masking material layer 115. Then, an etch-back process is performed to remove the shielding material layer 115 outside the gate pattern 113 and remove the shielding material layer 115 in the gate pattern 113 to a height lower than the top surface of the interlayer dielectric layer 107, thereby forming the structure of the shielding material layer 115 as shown in the figure. A silicon nitride layer 117 is then formed on the surface of the substrate. The silicon nitride layer 117 may be formed by an atomic layer deposition process that is conformally formed over the surface and sidewalls of the interlayer dielectric layer 107 and the masking material layer 115. In other embodiments, the shielding material layer 115 may be replaced by other non-conductive material layers.

Please refer to fig. 4. After the formation of the silicon nitride layer 117, an etching process is performed to remove the silicon nitride layer 117 and the shielding material layer 115 on the bottom surface of the gate pattern 113, leaving only the silicon nitride layer 117 and the shielding layer 115a on the sidewall of the interlayer dielectric layer 107 and exposing the first gate dielectric layer 103. The etching process may comprise a plurality of etching steps. For example, an etch back step is performed to remove the silicon nitride layer 117 on the top surface and the sidewalls of the ild layer 107 and expose the masking material layer 115, and an etch step is performed to remove the exposed masking material layer 115 and expose the first gate dielectric layer 103.

Please refer to fig. 5. After the formation of the shielding layer 115a, an etching process with an etching selectivity to silicon nitride is performed to remove the remaining silicon nitride layer 117, so as to form the shielding layers 115a on the first gate dielectric layer 103 and at the edge portions of the gate patterns 113 at two sides thereof, respectively.

Please refer to fig. 6. After forming the shielding layer 115a on the two side edges of the gate pattern 113, a conformal second gate dielectric layer 119, a conformal barrier layer 121 and a metal layer 123 are sequentially formed on the surface of the interlayer dielectric layer 107, the shielding layer 115a and the first gate dielectric layer 103. The conformal first gate dielectric layer 103 may be formed by an atomic layer deposition process, and may be made of a high-k material such as silicon oxide or hafnium oxide. The step of forming barrier layer 121 and metal layer 123 may include performing a deposition process, such as a Physical Vapor Deposition (PVD) process, to form a conformal barrier layer 121 on the substrate surface, covering the top and sidewalls of ild layer 107 and the surfaces of shield layer 115a and first gate dielectric layer 103. The barrier layer 121 can be made of titanium or titanium nitride, which can prevent metal components of a subsequently formed metal layer from diffusing and contaminating peripheral devices and can also help the metal layer adhere to the barrier layer 121. Next, another deposition process, such as PVD or CVD, is performed to form a metal layer 123 on the barrier layer 121, wherein the metal layer 123 fills the space in the gate pattern 113. In addition, a CMP process may be further included to planarize the formed metal layer 123 to provide a subsequently planarized surface. In the embodiment of the present invention, the barrier layer 121 and the metal layer 123 may be collectively referred to as a gate conductive layer.

Please refer to fig. 7. After the conformal second gate dielectric layer 119, the conformal barrier layer 121 and the metal layer 123 are formed, an etch-back process is performed to remove the second gate dielectric layer 119, the barrier layer 121 and the metal layer 123 outside the gate pattern 113. The etch back process removes a portion of the second gate dielectric layer 119, the barrier layer 121 and the metal layer 123 in the gate pattern 113 to make the top surfaces thereof flush with and lower than the top surface of the interlayer dielectric layer 107, so as to form the second gate dielectric layer 119a, the barrier layer 121a and the metal layer 123a as shown in the figure, wherein the second gate dielectric layer 119a, the barrier layer 121a and the metal layer 123a are formed in an inverted convex shape as seen in a cross-sectional view. In other embodiments, the etch-back process may also etch a non-flush top surface due to the difference in etch rate for different materials, for example, the top surface of the metal layer 123a may be raised after etch-back.

Please refer to fig. 8. After the formation of the barrier layer 121 and the metal layer 123, a silicon nitride cap layer 125 is formed on the top surfaces of the second gate dielectric layer 119a, the barrier layer 121a and the metal layer 123a as a cap layer or a hard mask layer of the gate structure. The step of forming the silicon nitride cap layer 125 may include performing a deposition process, such as a CVD process, to form a silicon nitride layer on the substrate surface, covering the top and sidewalls of the ild layer 107 and the top surfaces of the second gate dielectric layer 119a, the barrier layer 121a and the metal layer 123a, the silicon nitride layer filling the space in the gate pattern 113, and a CMP process to planarize the silicon nitride layer. Finally, an etch back process is performed to remove the silicon nitride layer outside the gate pattern 113 and make the silicon nitride layer flush with the top surface of the interlayer dielectric layer 107, thereby forming a silicon nitride cap layer 125 as shown in the figure.

Finally, please refer to fig. 9. After the formation of the silicon nitride cap layer 125, an etching process is performed to remove the interlayer dielectric layer 107 and the stop layer 105 on the substrate surface, thereby obtaining the gate structure 127 shown in the figure. In the embodiment of the present invention, the gate structure 127 includes, in order from bottom to top, a first gate dielectric layer 103, a second gate dielectric layer 119a, a barrier layer 121a, a metal layer 123a, and a silicon nitride cap layer 125, wherein the second gate dielectric layer 119a surrounds the barrier layer 121a, and the barrier layer 121a surrounds the metal layer 123 a. More particularly, in the embodiment of the present invention, the gate structure 127 has a shielding layer 115a located on the first gate dielectric layer 103 and located at the edge portions of both sides of the gate, and as can be seen from the figure, the existence of the shielding layer 115a can increase the Equivalent Oxide Thickness (EOT) at the edge portion of the gate structure 127, which is the sum of the thicknesses of the first gate dielectric layer 103, the shielding layer 115a and the second gate dielectric layer 119a, so as to suppress the gate induced drain leakage current (GIDL) problem without causing other adverse effects such as parasitic capacitance, which is the advantage and efficacy of the gate structure provided by the present invention.

In other embodiments, the etch-back process shown in the embodiment of fig. 7 may remove only the barrier layer 121 and the metal layer 123 (i.e., the gate conductive layer) without removing the outermost second gate dielectric layer 119. After the above processes, the gate structure finally obtained can be as shown in fig. 10, in which the outermost side of the gate structure is the second gate dielectric layer 119 and the shielding layer 115a, and the inner barrier layer 121a is flush with the top surface of the metal layer 123a, and the top surface is the silicon nitride cap layer 125 surrounded by the second gate dielectric layer 119.

Please refer to fig. 11. In other embodiments, the first gate dielectric layer 103 may be formed only within the area of the gate structure 127. For example, as shown in fig. 11, the first gate dielectric layer 103 is formed only on the active region ACT between the two shielding layers 115a of the gate structure 127, instead of covering the entire substrate surface as in the previous embodiment.

In other embodiments, as shown in fig. 12, spacers 129 may be formed on two sides of the gate structure 127. The function of the spacer 129 may include protecting the gate of the device, increasing the equivalent gate length, improving the gate control capability, suppressing the short channel effect of the device and the leakage current problem in the off state. The material of the spacer 129 may be silicon oxide, silicon nitride or a multi-layer structure thereof. Spacers 129 may be formed by depositing a conformal spacer material layer on the substrate surface after gate structure 127 is formed as shown in fig. 9, followed by an etching process. It is noted that in this embodiment, the stop layer 105 is not removed as in the previous embodiment, and the etching process for etching the spacer material layer is stopped after the surface of the stop layer 105 is exposed. However, in other embodiments, as shown in fig. 13, the etching process may also etch the underlying stop layer 105 and the first gate dielectric layer 103 such that the walls of the spacers 129 are flush with the sidewalls of the stop layer 105 and the first gate dielectric layer 103. Spacer 129 may be formed, followed by formation of inter-level dielectric layer 107 and contacts.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (13)

1. A gate structure, comprising:

an active region;

a first gate dielectric layer on the active region;

two shielding layers which are positioned on the first grid dielectric layer and are respectively positioned at the edge parts at two sides of the grid pattern;

a second gate dielectric layer conformally disposed on the first gate dielectric layer and the two shielding layers;

a gate conductive layer on the second gate dielectric layer, wherein the second gate dielectric layer surrounds the gate conductive layer; and

and the silicon nitride cover layer is positioned on the grid conducting layer.

2. The gate structure of claim 1, wherein the gate conductive layer is flush with a top surface of the second gate dielectric layer.

3. The gate structure of claim 1, wherein the second gate dielectric layer is an inverse convex structure.

4. The gate structure of claim 1, wherein the gate conductive layer is an inverted convex structure.

5. The gate structure of claim 1, wherein the gate conductive layer comprises an outer barrier layer and an inner metal layer.

6. The gate structure of claim 5, wherein a top surface of the metal layer is upwardly convex.

7. The gate structure of claim 1, wherein the sidewall of the gate structure comprises the shielding layer, the second gate dielectric layer and the silicon nitride cap layer from bottom to top.

8. The gate structure of claim 1, wherein sidewalls of the masking layer, the second gate dielectric layer, and the silicon nitride cap layer are flush.

9. The gate structure of claim 1, wherein the second gate dielectric layer surrounds the silicon nitride cap layer.

10. The gate structure of claim 1, wherein the first gate dielectric layer is only over the active regions of the two masking layers.

11. The gate structure of claim 1, comprising a stop layer formed on the first gate dielectric layer on both sides of the gate pattern.

12. The gate structure of claim 11, comprising two spacers on the stop layer and on two sides of the gate pattern.

13. The gate structure of claim 12, wherein walls of the spacer are flush with sidewalls of the stop layer and sidewalls of the first gate dielectric layer.

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