CN211929495U - Grid structure - Google Patents

Abstract

The utility model discloses a grid structure contains an active area, a first dielectric layer is located on the active area and be located the marginal position of grid pattern both sides, a second dielectric layer is located in the middle of the grid pattern on the active area and the marginal position of grid pattern both sides on the first dielectric layer, wherein the second dielectric layer is located the thickness at the position on the first dielectric layer is greater than the second dielectric layer is located the thickness at the position on the active area, a conducting layer are located on the second dielectric layer, a barrier layer is located on the conducting layer, a metal level is located on the barrier layer, wherein the barrier layer centers on the bottom surface and the lateral wall of metal level and a silicon nitride layer is located on the metal level. The utility model discloses have special grid dielectric layer design, can restrain the GIDL problem, can not arouse other harmful effects simultaneously again.

Description

Grid structure

Technical Field

Embodiments of the present disclosure relate to a gate structure, and more particularly, to a gate structure having a special gate dielectric layer to suppress a gate induced drain leakage current (GIDL) effect.

Background

The Gate Induced Drain Leakage (GIDL) effect is the main off-state Leakage current of the MOSFET. The effect is originated from that when the MOSFET grid is in an off state (the NM0S grid is connected with a negative voltage, the PMOS grid is connected with a positive voltage) and the drain region is connected with a voltage (the NM0S drain region is connected with a positive voltage, and the PMOS drain region is connected with a negative voltage), an inversion layer is formed on the surface due to the fact that an energy Band at the position, close to an interface, of the overlapped part of the drain-end impurity diffusion layer and the grid is strongly bent, and a depletion layer is very narrow, so that Band-to-Band Tunneling effect occurs on conduction Band electrons and valence Band holes, and drain leakage current is formed. It is the main source of off-state leakage current and determines the lower limit of the thickness of the thin oxide layer of the gate oxide layer. When the MOS is provided with a thin gate, GIDL may cause holes to damage the gate oxide layer or be trapped by the thin gate through tunneling effect, which all may cause the performance degradation reliability of the MOSFET to be reduced. In addition to off-state leakage, gate-induced drain leakage may also cause other undesirable effects, such as hole damage to or trapping by the gate oxide layer through tunneling, resulting in MOSFET performance degradation and reliability degradation.

The conventional method for inhibiting GIDL mainly increases the thickness of a gate dielectric layer or diffuses drain-side impurities away from a gate, and obviously, in the semiconductor industry pursuing high integration, such a scheme is not beneficial to further reduction of devices and can cause other parasitic effects (such as hot carrier effect) and other adverse effects.

SUMMERY OF THE UTILITY MODEL

In view of the Gate Induced Drain Leakage (GIDL) problem encountered in the semiconductor devices described above, the present invention provides a novel gate structure and method for fabricating the same, wherein the gate structure is characterized by a special gate dielectric design to suppress the GIDL problem without causing other adverse effects.

One of the objectives of the present invention is to provide a gate structure, which comprises an active area, a first dielectric layer located on the active area and located at the edge of the two sides of the gate pattern, a second dielectric layer located in the middle of the gate pattern, on the active area and at the edge of the two sides of the gate pattern on the first dielectric layer, wherein the second dielectric layer is located at the position on the first dielectric layer, the thickness of the position on the first dielectric layer is greater than that of the second dielectric layer located at the position on the active area, a conductive layer located on the second dielectric layer, a barrier layer located on the conductive layer, a metal layer located on the barrier layer, wherein the barrier layer surrounds on the bottom surface and the sidewall of the metal layer, and a silicon nitride layer located on the metal layer.

Another aspect of the present invention is to provide a method for manufacturing a gate structure, which includes the steps of: providing a substrate, defining an active region thereon, sequentially forming a first dielectric layer and an interlayer dielectric layer on the substrate, forming a gate pattern in the interlayer dielectric layer above the active region, forming a silicon nitride layer on the gate pattern and the interlayer dielectric layer, performing an etch-back process to remove the silicon nitride layer and the first dielectric layer on the bottom surface of the gate pattern to expose the active region, removing the remaining silicon nitride layer to expose the first dielectric layer on both sides of the gate pattern, forming a second dielectric layer on the first dielectric layer in the gate pattern and the exposed active region, and forming a gate structure on the second dielectric layer.

These and other objects of the present invention will become more apparent to those skilled in the art after a reading of the following detailed description of the preferred embodiment illustrated in the various figures and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings depict some embodiments of the invention and, together with the description, serve to explain its principles. In these figures:

FIGS. 1-10 are cross-sectional views illustrating a process flow of a gate structure according to a preferred embodiment of the present disclosure;

fig. 11 is a cross-sectional view of a gate structure according to another embodiment of the present invention;

fig. 12 is a cross-sectional view of a gate structure according to yet another embodiment of the present invention; and

fig. 13 is a cross-sectional view of a gate structure according to yet another embodiment of the present invention.

Wherein the reference numerals are as follows:

100 semiconductor substrate

101 device isolation layer

101a silicon oxide liner

101b silicon nitride liner

101c silicon oxide fill layer

103 insulating layer

103a edge part

105 stop layer

107 interlayer dielectric layer

109 hard mask layer

111 advanced exposure patterned film

113 gate pattern

115 silicon nitride layer

117 gate insulating layer

119 conductive layer

121 barrier layer

123 metal layer

125 silicon nitride layer

127 grid structure

129 gate dielectric layer

131 recess

133 spacing wall

135 contact element

ACT active region

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, which will reference features described in order for a reader to understand and achieve a technical effect. It will be understood by the reader that the description herein is by way of illustration only and is not intended to be limiting. The various embodiments of the disclosure and the various features of the embodiments that are not mutually inconsistent can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the disclosure may be apparent to those skilled in the art without departing from the spirit and scope of the disclosure, and are intended to be included within the scope of the disclosure.

It should be readily understood by the reader that the meaning of "on …", "above …" and "above …" in this case should be read in a broad manner such that "on …" not only means "directly on" something "but also includes the meaning of" on "something with intervening features or layers therebetween, and" on … "or" above … "not only means" on "something" or "above" but also includes the meaning of "on" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Moreover, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the drawings, fig. 1-10 are cross-sectional views illustrating a process flow of a gate structure according to a preferred embodiment of the present invention, and fig. 11 is a cross-sectional view illustrating a gate structure according to another embodiment of the present invention.

Please refer to fig. 1. First, a semiconductor substrate 100 is provided, and a device isolation layer 101 defining an active region ACT is formed in the semiconductor substrate 100. The semiconductor substrate 100 may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The device isolation layer 101 may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling the recess between the active regions ACT with an isolation material. In an example, the device isolation layer 101 is a Shallow Trench Isolation (STI) structure, which may be composed of a silicon oxide liner layer 101a, a silicon nitride liner layer 101b, and a silicon oxide filling layer 101 c. The silicon oxide liner 101a and the silicon nitride liner 101b can prevent the shallow trench from being damaged by etching and radio frequency bias in the process of forming the device isolation layer 101. In an example, the active region ACT may be a peripheral region of the semiconductor memory device around the memory cell region, but is not limited thereto.

Refer back to fig. 1. On the surface of the semiconductor substrate 100, a layer structure of an insulating layer 103, a stop layer 105, an interlayer dielectric layer 107, a hard mask layer 109, and an advanced exposure pattern film (APF)111 are sequentially formed. The insulating layer 103 may be a silicon oxide layer formed by an in-situ steam generation (ISSG) process, and the thickness of the insulating layer 103 may be different from that of the insulating layer 103 on the active region ACT. The stop layer 105 may be a silicon nitride layer formed by an atomic layer deposition process. The ILD 107 may be a spin-on-dielectric (SOD), the hard mask layer 109 may be a silicon nitride layer, and the first-exposure-pattern film 111 may be an amorphous carbon mask.

Please refer to fig. 2. A photolithography process is performed to form a gate pattern 113 in the interlayer dielectric layer 107. The steps of the photolithography process may include: a photolithography mask, which may be a composite mask, may be formed on the advanced exposure patterning film 111, and may include a layer structure of an Organic Dielectric Layer (ODL), an anti-reflective coating (ARC), and a photoresist layer (PR) having a gate pattern defined therein, and then an etching process is performed using the photolithography mask as an etching mask and the stop layer 105 as an etching stop layer to remove portions of the hard mask layer 109 and the interlayer dielectric layer 107, so as to form a gate pattern 113 in the interlayer dielectric layer 107.

Please refer to fig. 3. After forming the gate pattern 113 in the interlayer dielectric layer 107, a silicon nitride layer 115 is formed on the surface of the substrate. The silicon nitride layer 115 may be formed in an atomic layer deposition process that conformally covers the surface of the hard mask layer 109, the sidewalls of the interlayer dielectric layer 107, and the surface of the stop layer 105.

Please refer to fig. 4. After the formation of the silicon nitride layer 115, an etch-back process is performed to remove the stop layer 105 and the insulating layer 103 in the gate pattern 113 to expose the active region ACT therebelow. The etch-back process also removes the silicon nitride layer 115 overlying the hard mask layer 109, leaving only the portion thereof overlying the sidewalls of the ild layer 107. The etch-back process may also include more than two etching processes, such as a first etching process to remove the silicon nitride layer 115, and a second etching process to remove the insulating layer 103.

Please refer to fig. 5. After the active region ACT is exposed, an etching process is performed to remove the silicon nitride material exposed on the substrate surface, which includes the hard mask layer 109 on the interlayer dielectric layer 107, the silicon nitride layer 115 on the sidewall of the interlayer dielectric layer 107, and the stop layer 105 partially under the silicon nitride layer 115. In this manner, the edge portion 103a of the insulating layer 103 protruding laterally from below the interlayer dielectric layer 107 in the gate pattern 113 as shown in the drawing is obtained.

Please refer to fig. 6. After the edge portion 103a of the insulating layer 103 is formed, a gate insulating layer 117 is formed on the bottom surface of the gate pattern 113. In the example, the gate insulating layer 117 may be formed using an in-situ steam generation (ISSG) process, and it is noted that, for the formed gate insulating layer 117, the thickness of the portion of the gate insulating layer 117 directly contacting the active region ACT is greater than the thickness of the portion thereof contacting the edge portion 103a of the insulating layer 103, because the ISSG process can generate more thick silicon oxide reactant from the silicon active region ACT, and can generate less silicon oxide reactant from the silicon oxide insulating layer 103. It is noted that in the present embodiment, a layer structure of two layers of insulating materials is formed in the gate pattern 113, including the insulating layer 103 and the gate insulating layer 117 located on the insulating layer 103 and the active region ACT. Both of these two layers will subsequently serve as the gate dielectric layer of the gate structure.

Please refer to fig. 7. After the gate insulating layer 117 is formed, a conductive layer 119 is then formed on the gate insulating layer 117. The step of forming the conductive layer 119 may include performing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form the conductive layer 119, which may be amorphous silicon, on the substrate surface, wherein the conductive layer 119 covers the ild layer 107 and fills the space in the gate pattern 113. A Chemical Mechanical Polishing (CMP) process may be further included to planarize the formed conductive layer 119. Then, an etch-back process is performed to remove the conductive layer 119 outside the gate pattern 113 and remove the conductive layer 119 in the gate pattern 113 to a certain height, so as to form the conductive layer 119 structure as shown in the figure.

Please refer to fig. 8. After the conductive layer 119 is formed, a barrier layer 121 and a metal layer 123 are formed over the conductive layer 119. The step of forming barrier layer 121 and metal layer 123 may include performing a deposition process, such as a Physical Vapor Deposition (PVD) process, to form a conformal barrier layer 121 on the substrate surface, covering the top and sidewalls of ild layer 107 and the top surface of conductive layer 119. The barrier layer 121 can be made of titanium or titanium nitride, which can prevent metal components of a subsequently formed metal layer from diffusing and contaminating peripheral devices and can also help the metal layer adhere to the barrier layer 121. Next, another deposition process, such as PVD or CVD, is performed to form a metal layer 123 on the barrier layer 121, wherein the metal layer 123 covers the ild layer 107 and fills the space in the gate pattern 113. A CMP process may be further included to planarize the formed metal layer 123. Finally, an etch back process is performed to remove the metal layer 123 and the barrier layer 121 outside the gate pattern 113 and remove the metal layer 123 and the barrier layer 121 in the gate pattern 113 to a certain height, so that the barrier layer 121 and the metal layer 123 are formed as shown in the figure, and the formed barrier layer 121 is a U-shaped structure as seen from the cross-sectional view.

Please refer to fig. 9. After the formation of the barrier layer 121 and the metal layer 123, a silicon nitride layer 125 is formed on the barrier layer 121 and the metal layer 123 as a cap layer of the gate structure. The step of forming the silicon nitride layer 125 may include performing a deposition process, such as a CVD process, to form a silicon nitride layer 125 on the substrate surface, covering the top and sidewalls of the ild layer 107 and the top surfaces of the barrier layer 121 and the metal layer 123, wherein the silicon nitride layer 125 fills the space in the gate pattern 113, and a CMP process to planarize the formed silicon nitride layer 125. Finally, an etch back process is performed to remove the silicon nitride layer 125 outside the gate pattern 113 and to make the silicon nitride layer 125 flush with the top surface of the interlayer dielectric layer 107, thereby forming the silicon nitride layer 125 structure as shown in the figure.

Finally, please refer to fig. 10. After the formation of the silicon nitride layer 125, an etching process is performed to remove the interlayer dielectric layer 107 and the stop layer 105 on the substrate surface, thereby obtaining the gate structure 127 shown in the figure. In the embodiment of the present invention, the gate structure 127 sequentially includes a conductive layer 119, a barrier layer 121, a metal layer 123 and a silicon nitride layer 125 from bottom to top. More particularly, in the embodiment of the present invention, the gate dielectric layer 129 between the gate structure 127 and the active region ACT is formed by the edge portion 103a of the insulating layer 103 and the gate insulating layer 117, which are respectively referred to as a first dielectric layer and a second dielectric layer. As can be seen from the figure, the thickness of the gate dielectric layer 129 (including the sum of the thicknesses of the insulating layer 103 and the gate insulating layer 117) at the edge portions of the gate structure 127 is greater than the thickness of the gate dielectric layer at the middle portion of the gate structure 127 (only the thickness of the gate insulating layer 117), so that the structure design can suppress the gate induced drain leakage current (GIDL) problem without causing other adverse effects such as parasitic capacitance.

In other embodiments, as shown in fig. 11, spacers 133 may be further formed on two sides of the gate structure 127. The function of the spacer 133 may include protecting the gate of the device, increasing the equivalent gate length, improving the gate control capability, suppressing the short channel effect of the device and the leakage current problem in the off state. The material of the spacer 133 may be silicon oxide, silicon nitride or a multi-layer structure thereof. The spacers 133 may be formed by depositing a conformal spacer material layer on the substrate surface after the gate structure 127 of fig. 10 is formed, and then performing an etching process. In this embodiment, the etching process is stopped after the surface of the stop layer 105 is exposed. However, in other embodiments, as shown in FIG. 12, the etching process may also etch the underlying stop layer 105 and insulating layer 103 such that the walls of the spacer 133 are flush with the sidewalls of the stop layer 105 and insulating layer 103. Spacers 133 may be formed, followed by formation of inter-level dielectric layers 107 and contacts 135 in inter-level dielectric layers 107 on both sides of gate structure 127. The contact 135 may be connected to the underlying device isolation layer 101 or active region ACT through the stop layer 105 and the insulating layer 103 (if present).

The structure of the present invention has other embodiment variations, for example, as shown in fig. 11, the etching process in fig. 4 may be performed to remove the stop layer 105 and the insulating layer 103 in the gate pattern 113, so that a portion of the active region ACT is also removed to form the recess 131. Thus, the middle portion of the formed gate dielectric layer 129 is formed in the recess 131, and the bottom surface thereof is lower than the top surface of the surrounding active region ACT. The structure design can further improve the inhibition effect of GIDL.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A gate structure, comprising:

an active region;

a first dielectric layer on the active region and at the edge parts of both sides of the gate pattern;

a second dielectric layer on the active region in the middle of the gate pattern and on the first dielectric layer at the edge portions of both sides of the gate pattern, wherein the thickness of the portion of the second dielectric layer on the first dielectric layer is greater than the thickness of the portion of the second dielectric layer on the active region;

a conductive layer on the second dielectric layer;

a barrier layer on the conductive layer;

a metal layer on the barrier layer, wherein the barrier layer surrounds the bottom surface and the side wall of the metal layer; and

and the silicon nitride layer is positioned on the metal layer.

2. The gate structure of claim 1, comprising an interlayer dielectric layer disposed around the gate structure, wherein the first dielectric layer is partially between the interlayer dielectric layer and the active region.

3. The gate structure of claim 1, wherein the barrier layer is a U-shaped structure.

4. The gate structure of claim 1, wherein a bottom surface of the portion of the second dielectric layer overlying the active region is lower than a top surface of the active region.

5. The gate structure of claim 1, wherein a boundary of the gate pattern is on the first dielectric layer.

6. The gate structure of claim 1, wherein the conductive layer is a silicon layer.

7. The gate structure of claim 1, comprising a stop layer formed on the first dielectric layer and on both sides of the gate pattern.

8. The gate structure of claim 7, comprising two spacers on the stop layer and on two sides of the gate pattern.

9. The gate structure of claim 8, wherein walls of the spacer are flush with sidewalls of the stop layer and sidewalls of the first dielectric layer.

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