CN216435902U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The utility model discloses a semiconductor storage device. The semiconductor memory device includes a substrate, a plurality of bit line contacts, a plurality of bit lines, a contact plug, a first spacer, and a second spacer. The substrate comprises a plurality of active regions; each bit line contact part is respectively positioned on the active region; each bit line is positioned on the substrate and extends along a preset direction, and each bit line covers each bit line contact part on the extending path of the bit line; the contact plugs are positioned between the adjacent bit lines; first spacers located between the contact plugs and the bit lines and covering sidewalls of the bit line contacts and sidewalls of the bit lines; the second spacer is located between the contact plug and the first spacer.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The utility model relates to the field of semiconductor technology, in particular to semiconductor storage device.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a buried gate structure, it has gradually replaced a DRAM cell with a planar gate structure due to the longer channel length of carriers within the same semiconductor substrate to reduce the leakage of the capacitor structure.

As semiconductor memory devices are highly integrated, the conventional DRAM cell with the buried gate structure still has many defects due to process technology limitations, and further improvements and improvements are needed to effectively improve the performance and reliability of the related semiconductor memory device.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor memory device to avoid leakage current between a bit line and a contact plug in the memory device.

To this end, the utility model provides a semiconductor storage device, include:

a substrate including a plurality of active regions and isolation regions;

a plurality of bit line contacts respectively located on the plurality of active regions;

a plurality of bit lines on the substrate and extending in a predetermined direction, and each of the bit lines covering the plurality of bit line contacts on an extending path thereof;

contact plugs located between adjacent bit lines;

a first spacer located between the contact plug and each of the plurality of bit lines and covering a sidewall of each of the bit line contacts and a sidewall of each of the bit lines, wherein a composition of the first spacer includes a metal nitride, the metal nitride being in contact with the isolation region; and

a second spacer located between the contact plug and the first spacer, wherein a composition of the second spacer is different from a composition of the first spacer.

Another object of the present invention is to provide a method for forming a semiconductor memory device, including:

providing a substrate, wherein the substrate comprises a plurality of active regions and isolation regions;

forming a plurality of bit line contact recessed regions in the substrate, wherein the bottom of each bit line contact recessed region exposes each active region;

forming a plurality of bit line contact parts respectively positioned in the bit line contact concave regions;

forming a plurality of bit lines on the substrate and extending along a predetermined direction, and each of the bit lines covering the plurality of bit line contacts on an extending path thereof;

forming a first spacer layer covering sidewalls of each of the plurality of bit line contacts and sidewalls of each of the plurality of bit lines and filling the plurality of bit line contact recesses, wherein a composition of the first spacer layer includes a metal nitride, the metal nitride contacting the isolation region;

etching the first gap wall layer to form a first gap wall; and

forming a second spacer to cover the first spacer, wherein a composition of the second spacer is different from a composition of the first spacer.

The semiconductor memory device of the present invention is to cover the sidewall of the bit line contact portion with the first spacer formed of tungsten nitride to cover the metal residue remaining on the sidewall of the bit line contact portion, thereby avoiding the metal residue from directly contacting the contact plug adjacent to the bit line contact portion. Since the first spacer has higher compactness and capability of blocking diffusion of metal atoms, metal residues generated during formation of the bit line, such as conductive residues of tungsten, can be prevented from diffusing out of the first spacer during operation of the semiconductor memory device to cause short circuit between the bit line and the contact plug. Therefore, the performance and reliability of the semiconductor memory device of the present invention can be effectively improved.

Drawings

Fig. 1 to 8 are schematic cross-sectional views illustrating a structure of a method of forming a semiconductor memory device in a manufacturing process thereof according to an embodiment of the present invention;

fig. 9 is a schematic cross-sectional view of a semiconductor memory device according to another embodiment of the present invention;

fig. 10 is a top view of a semiconductor memory device according to an embodiment of the present invention.

Wherein the reference numerals are as follows:

100 substrate

110 isolation region

120 active region

121 first source/drain region

122 second source/drain region

130 bit line contact recess

140 insulating layer

200 bit line contact

300 bit line

310 bottom polysilicon layer

320 thin film metal nitride layer

330 metallic material layer

340 mask layer

400 first spacer layer

410 first spacer

420 second spacer layer

430 second spacer

432 layer of conductive material

440 contact plug

441 bond pad

442 storage node contact

450 groove

460 insulating layer

500 strip-shaped insulating structure

D1 first direction

D2 second direction

Third direction D3

Detailed Description

The memory device and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to precise scale, and are provided for convenience and clarity in assisting the practice of the embodiments of the present invention.

Fig. 1 to 8 are schematic cross-sectional views illustrating a structure of a method for forming a semiconductor memory device in a manufacturing process thereof according to an embodiment of the present invention. First, as shown in fig. 1, at a processing stage of fig. 1, a substrate 100, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other semiconductor substrate, is provided, wherein the substrate includes a plurality of active regions 120 (e.g., including a first source/drain region 121 and a second source/drain region 122) and isolation regions 110. The active region 120 may be a doped region and has the same conductivity type, such as an n-type doped region or a p-type doped region, and may be formed on the upper portion of the substrate 100 by an ion implantation process. Adjacent active regions 120 may be separated by isolation regions 110 such that adjacent active regions 120 do not directly contact. The isolation region 110 is made of an insulating material, and may surround the periphery of each active region 120, so that adjacent active regions 120 are electrically insulated from each other.

An isolation layer 140, preferably comprising an oxide-nitride-oxide (ONO) structure, may be further disposed on the substrate 100, the isolation layer 140 covering the plurality of active regions 120 and the plurality of isolation regions 110 thereunder. The isolation layer 140 can prevent the active region 120 thereunder from being damaged by the manufacturing process, or prevent the active region 120 thereunder from being unnecessarily electrically connected to a bit line (not shown) subsequently formed on the isolation layer 140.

In the isolation layer 140 and the substrate 100, a plurality of bit line contact recesses 130 may be formed such that a plurality of bit line contact recesses 130 are formed in the substrate 100, and the bottom of each bit line contact recess 130 exposes each active region 120. The bit line contact recess 130 may be formed, for example, by using a photolithography process and further performing an etching process on the substrate 100. In this embodiment, the bit line contact recess 130 penetrates through the isolation layer 140 and extends downward into the substrate 100. Further, the opening size of the bit line contact recess 130 is larger than the size of the first source/drain region 121, so that the first source/drain region 121 can be exposed to a greater extent, so that the first source/drain region 121 can be electrically contacted with a subsequently formed bit line contact portion with a larger area. For example, in the present embodiment, the width dimension of the bit line contact recess region 130 is greater than the width dimension of the first source/drain region 121 in both the direction perpendicular to the extension direction of the active region and in the extension direction along the active region. That is, the bit line contact recess region 120 exposes the first source/drain region 121 and also laterally expands to expose the trench isolation structure 110 adjacent to the active region. When viewed from a top view, the opening shape of the bitline contact recess 130 may be an ellipse, a circle, a rectangle, a diamond, or other polygons, which is not limited herein.

A deposition process may then be used to form a stack of layers (not shown) on the substrate 100, and the patterned mask layer may then be used as an etching mask to etch the stack of layers, thereby forming a structure similar to that shown in fig. 2. Referring to fig. 2, at the stage of the process of fig. 2, a plurality of bit line contacts 200 extending along a predetermined direction are respectively formed in the plurality of bit line contact recesses 130. The bit line contact 200 is a conductive material, such as doped semiconductor polysilicon, and the bit line contact 200 preferably makes ohmic contact with the underlying active region 120. A plurality of bit lines 300 are formed on the substrate 100 and extend along a predetermined direction, and each of the bit lines 300 covers the plurality of bit line contacts 200 on its extending path. Preferably, each of the plurality of bit lines 300 includes a bottom polysilicon layer 310, a thin film metal nitride layer 320, a metal material layer 330, and a mask layer 340. The kind and number of stacked layers in each bit line 300 are not limited to the above, and may be adjusted according to actual needs.

Specifically, the method of forming the bit line contact 200 and the bit line 300 may include the steps of: first, a bit line contact material layer (not shown) is globally deposited on the substrate 100, such that the bit line contact material layer, for example, a polysilicon material layer, is filled into the bit line contact recess 130. A chemical mechanical polishing process is performed to remove the bit line contact material layer protruding from the bit line contact recess 130 by using the isolation layer 140 as a polishing stop layer, so that the polished bit line contact material layer fills the bit line contact recess 130, and the top surface of the bit line contact material layer is flush with the top surface of the isolation layer 140. A stack of layers (not shown) is then formed over the substrate 100, wherein each sub-layer in the stack may correspond to each layer in a subsequently formed bit line. An etching mask layer is then formed on the stack layer, and an etching process is performed to sequentially pattern the stack layer and the bit line contact material layer, thereby respectively forming the bit line 300 and the bit line contact 200 including the mask layer 340, the conductive layer (including the underlying polysilicon layer 310, the thin-film metal nitride layer 320, and the metal material layer 330) as shown in fig. 2. Preferably, the bottom surface of the bit line 300, the bit line contact 200 and the top surface of the isolation layer 140 are flush, and the sidewall of the bit line 300 along the predetermined direction and the sidewall of the bit line contact 200 along the predetermined direction are substantially aligned.

In one embodiment, since the bit lines 300 are formed by etching the stacked layers stacked on the substrate 100, when the plurality of bit lines 300 are formed, residues or byproducts (e.g., metal residues or metal byproducts, hereinafter generally referred to as metal residues) in the etching process may remain or adhere to the sidewalls of the bit line contacts 200 in the plurality of bit line contact recesses 130 or to the sidewalls of the respective bit lines 300, wherein the metal component of the metal residues includes the metal component of the metal material layer 330.

After the formation of the bit line 300, an appropriate cleaning process, such as dry etching or wet etching, may be performed to remove the photoresist and/or the etching residues. However, the residue cannot be completely removed even though the cleaning process is performed due to the cleaning ability or the adhesion of the residue. In addition, when the metal residues are conductive and located on the sidewalls of the bit line contact 200, the conductive metal residues may be unnecessarily electrically connected to adjacent conductive structures (e.g., conductive contact plugs), thereby adversely affecting the electrical performance.

Referring next to fig. 3, at the stage of the process of fig. 3, a first spacer layer 400 is formed to conformally cover the sidewalls of each of the bit line contacts 200 and the bit lines 300 and fill the bit line contact recesses 130. The composition of the first spacer layer 400 includes a metal nitride, which is in contact with the isolation region 110, and the metal nitride may be tungsten nitride, but is not limited thereto. Preferably, the first spacer layer 400 also covers the top surfaces of the plurality of bit lines 300 and the isolation layer 140. The step of forming the first barrier rib layer 400 may include using an atomic layer deposition process (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD), but is not limited thereto. In one embodiment, the thickness of the first spacer layer 400 is less than 10 nm, but is not limited thereto, so that even though the material includes tungsten nitride, the resistance value is high enough not to make unnecessary electrical connection with the adjacent components.

Referring next to FIG. 4, at the stage of the process of FIG. 4, the first spacer layer 400 is etched to form first spacers 410. Preferably, the first spacer 410 may be formed by etching the first spacer layer 400 covering the top surface and a portion of the sidewalls of the mask layer 340, the bit line contact recess 130, and the top surface of the isolation layer 140 to form the first spacer 410, wherein the first spacer 410 completely covers the sidewalls of the bit line contact 200, the bottom polysilicon layer 310, the thin film metal nitride layer 320, and the metal material layer 330, and a portion of the sidewalls of the mask layer 340. In other words, the sidewalls of the bit line contact 200, the bottom polysilicon layer 310, the thin film metal nitride layer 320, and the metal material layer 330 are covered by the first spacers 410, and the top surface of the mask layer 340 is higher than the top surface of the first spacers 410. The first spacer 410 can cover the etching residue (e.g., metal residue) on the sidewall of the bit line contact 200, thereby preventing the etching residue from directly contacting the conductive plug formed between the bit lines 300, and improving the electrical performance of the device. In addition, since the first spacer 410 has higher compactness and capability of blocking diffusion of metal atoms, the metal residue can be prevented from being gradually diffused to other peripheral components in the operation process of the device, so that the performance and reliability of the semiconductor memory device of the present invention can be effectively improved.

In one embodiment, the thickness of the first spacer 410 is less than 10 nm to ensure the electrical insulation of the first spacer 410, but not limited thereto. According to other embodiments, the first spacer 410 with other thickness can be used, as long as the first spacer 410 can be electrically insulated and can avoid electrical connection with other peripheral components.

Referring next to fig. 5, at the processing stage of fig. 5, a second spacer layer 420 is formed to conformally cover the first spacers 410, wherein the composition of the second spacer layer 420 is different from the composition of the first spacers 410, and the composition of the second spacer layer 420 may be, but is not limited to, an insulating material such as oxide, silicon nitride, oxynitride, or a combination thereof. Alternatively, the thickness of the second spacer layer 420 may be greater than the thickness of the first spacer 410, but is not limited thereto.

In one embodiment, the second spacer layer 420 covers the first spacers 410, the top surface and a portion of the sidewalls of the mask layer 340, the bit line contact recesses 130, and the top surface of the isolation layer 140.

Referring next to fig. 6, at the processing stage of fig. 6, the second spacer layer 420 is etched to form second spacers 430, and a layer of conductive material 432 is filled between the bit lines 330. Preferably, the second spacers 430 are formed by etching the second spacer layer 420 covering the top surface of the mask layer 340, the surface of the bit line recess 130 and the top surface of the isolation layer 140 to form the second spacers 430, and the portions of the isolation layer 140 not covered by the bit lines 300 may be etched at the same time or after the formation of the second spacers 430 to expose the active regions 120. Next, a conductive material layer 432 is formed between adjacent bit lines 300 and covers the top surface of the masking layer 340 and the sidewalls of the second spacer 430. Preferably, the conductive material layer 432 fills the bit line recess 130, but is separated by the first and second spacers 410 and 430 without directly contacting the bit line contact 200, so as to prevent the contact plug 440 from electrically connecting to the bit line 300.

In an embodiment, the conductive material layer 432 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and/or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), and a metal-semiconductor compound (e.g., a metal silicide).

Referring next to fig. 7, at the processing stage of fig. 7, the conductive material layer 432 and portions of the mask layer 340 are etched to form a plurality of trenches 450 and contact plugs 440. The contact plugs 440 are electrically separated from each other, and each contact plug 440 may include a bonding pad 441 and a storage node contact 442. Preferably, each of the plurality of bonding pads 441 is located on the mask layer 340, and each of the plurality of storage node contacts 442 is located between adjacent ones of the plurality of bit lines 300. In an embodiment, at least a bottom of each of the plurality of trenches 450 exposes a portion of the first spacers 410, the second spacers 430, and the mask layer 340. It is noted that although the cross-sectional view of the semiconductor memory device shown in fig. 7 has a plurality of trenches 450 separated from each other, the trenches 450 actually communicate with each other in the top view of the semiconductor memory device and surround the sidewalls of the bonding pads 441.

Referring next to fig. 8, at the processing stage of fig. 8, a deposition process may be performed to form an insulating layer (not shown) covering the contact plug 440 and filling the trench 450. Then, an insulating layer (not shown) is polished by a chemical mechanical polishing process, so that the insulating layer 460 is formed only in the trenches 450, and the top surface of the insulating layer 460 is flush with the top surface of the contact plugs 440 (or the bonding pads 441). The insulating layer 460 can prevent the adjacent contact plugs 440 from being unnecessarily electrically connected.

Through the above-mentioned manufacturing process, a semiconductor memory device as shown in fig. 8 can be obtained, which includes at least the following components: a substrate 100, such as a silicon substrate, an epitaxial silicon substrate, or a Silicon On Insulator (SOI) substrate, includes a plurality of active regions 120; a plurality of bit line contacts 200 disposed on the plurality of active regions 120, respectively; a plurality of bit lines 300 located on the substrate 100 and extending along a predetermined direction, and each of the plurality of bit lines 300 covering the plurality of bit line contacts 200 located on an extending path thereof; contact plugs 440 between adjacent ones of the plurality of bit lines 300; a first spacer 410 between the contact plug 440 and the plurality of bit lines 300 and covering sidewalls of the bit line contacts 200 and sidewalls of the bit lines 300, wherein the composition of the first spacer 410 includes a metal nitride, which is in contact with the isolation region 110, and may be tungsten nitride; a second spacer 430 between the contact plug 440 and the first spacer 410, wherein the composition of the second spacer 430 is different from the composition of the first spacer 410. A portion of the second spacer 430 covers sidewalls of the first spacers 410 and directly contacts sidewalls of each of the plurality of bit lines 300.

The semiconductor memory device of the present invention is not limited to the semiconductor memory device shown in the embodiment of fig. 8, and may have other variations. For example, fig. 9 is a schematic cross-sectional view of a semiconductor memory device according to another embodiment of the present invention. As shown in fig. 9, the difference from the embodiment of fig. 8 is that the second spacer 430 covers the sidewalls of the first spacers 410, and does not directly contact the sidewalls of each of the plurality of bit lines 300.

Referring next to fig. 10, fig. 10 is a top view of a semiconductor memory device according to an embodiment of the present invention. The cross-sectional views shown in fig. 8 and 9 may be considered as cross-sectional views taken along the cross-sectional line a-a' of fig. 10. In the present embodiment, the bit lines 300 extend in the first direction D1 in parallel with each other and spaced apart from each other. The plurality of active regions 120 extend along the second direction D2 in parallel and spaced apart from each other, and preferably, the second direction D2 is not perpendicular to the first direction D1 and the third direction D3, so that the plurality of active regions 120 may be integrally arranged in a specific arrangement, such as an array arrangement (array arrangement) shown in fig. 10, but not limited thereto. Both ends of each active region 120 may correspond to and be electrically connected to each contact plug 440 (as shown in fig. 8 and 9), and the center of each active region 120 may correspond to one bit line contact recess 130. In addition, a plurality of stripe insulation structures 500 may be disposed on the substrate 100, wherein the stripe insulation structures 500 are separated from each other and are alternately arranged with the bit lines 300 in the third direction D3. The space surrounded by the stripe insulation structures 500 and the bit lines 300 is filled with the contact plugs 440 (as shown in fig. 8 and 9), i.e., each of the contact plugs 440 is disposed between adjacent stripe insulation structures 500 and between adjacent bit lines 300. The plurality of stripe-shaped insulating structures 500 may be formed of an insulating material having an etching selectivity with respect to the contact plugs 440, such as silicon nitride and/or silicon oxynitride, but is not limited thereto. The bonding pad 441 is an upper structure of the contact plug 440, and a portion of the bonding pad 441 covers a top surface of the bit line 300 and a top surface of the bar-shaped insulating structure 500, and the whole may exhibit an array arrangement as shown in fig. 10, but is not limited thereto. An insulating layer 460 (shown in fig. 8 and 9) surrounds the sidewalls of the bonding pad 441 and is disposed on the bit line 300, the stripe-shaped insulating structure 500 and the storage node contact 442, but is not limited thereto.

In one embodiment, the material of each of the plurality of bit line contacts 200 comprises polysilicon.

In one embodiment, each of the plurality of bit lines 300 includes a mask layer 340, and a top surface of the mask layer 340 is higher than a top surface of the first spacer 410.

In one embodiment, each of the plurality of bit lines 300 includes a metal material layer 330, and sidewalls of the metal material layer 330 are covered by the first spacers 410.

In one embodiment, each of the plurality of bit lines 300 includes a thin film metal nitride layer 320, and sidewalls of the thin film metal nitride layer 320 are covered by the first spacers 410.

In one embodiment, each of the plurality of bit lines 300 includes a bottom polysilicon layer 310, the bottom polysilicon layer 310 is located on each of the bit line contacts 200, and sidewalls of the bottom polysilicon layer 310 are covered by the first spacer layer.

In one embodiment, the thickness of the first spacer 410 is less than 10 nm to ensure electrical isolation and avoid electrical connection with other peripheral components.

In one embodiment, the thickness of the second spacer 430 is greater than the thickness of the first spacer 410.

In one embodiment, the semiconductor memory device further comprises a plurality of bit line contact recesses 130, a bottom surface of each of the plurality of bit line contact recesses 130 exposing each of the plurality of active regions 120, wherein each of the plurality of bit line contacts 200 is located in each of the plurality of bit line contact recesses 130.

In one embodiment, the first spacers 410 and the contact plugs 440 are located in each of the bit line contact recess regions 130.

In one embodiment, the semiconductor memory device further includes a plurality of isolation regions 110 disposed in the substrate 100 to define and surround the plurality of active regions 120 within the substrate 100, wherein each of the plurality of bit line contact recesses 130 exposes the isolation layer 140.

In one embodiment, the semiconductor memory device further includes a metal residue in each of the bit line contact recess regions 130 and between the bit line contact 200 and the first spacer 410.

The semiconductor memory device of the present invention is to cover the sidewall of the bit line contact portion with the first spacer formed of tungsten nitride to cover the metal residue remaining on the sidewall of the bit line contact portion, thereby avoiding the metal residue from directly contacting the contact plug adjacent to the bit line contact portion. Since the first spacer has higher compactness and capability of blocking diffusion of metal atoms, metal residues, such as conductive residues of tungsten and the like, generated during formation of the bit line can be avoided from diffusing out of the first spacer to cause short circuit between the bit line and the contact plug during operation of the semiconductor memory device. Therefore, the performance and reliability of the semiconductor memory device of the present invention can be effectively improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A semiconductor memory device, comprising:

a substrate comprising a plurality of active regions;

a plurality of bit line contacts respectively located on the plurality of active regions;

a plurality of bit lines on the substrate and extending in a predetermined direction, and each of the bit lines covering the plurality of bit line contacts on an extending path thereof;

contact plugs located between adjacent bit lines;

a first spacer positioned between the contact plug and each of the plurality of bit lines and covering a sidewall of each of the bit line contacts and a sidewall of each of the bit lines; and

a second spacer located between the contact plug and the first spacer, wherein a composition of the second spacer is different from a composition of the first spacer.

2. The semiconductor memory device according to claim 1, wherein each of the plurality of bit lines includes a mask layer having a top surface higher than a top surface of the first spacer.

3. The semiconductor memory device according to claim 1, wherein each of the plurality of bit lines includes a metal material layer, and sidewalls of the metal material layer are covered with the first spacers.

4. The semiconductor memory device according to claim 1, wherein each of the plurality of bit lines includes a bottom polysilicon layer on each of the bit line contacts, and sidewalls of the bottom polysilicon layer are covered by the first spacers.

5. The semiconductor memory device according to claim 1, wherein a thickness of the first spacer is less than 10 nm.

6. The semiconductor memory device according to claim 1, wherein a thickness of the second spacer is larger than a thickness of the first spacer.

7. The semiconductor memory device of claim 1, further comprising a plurality of bit line contact recesses, a bottom surface of each of said plurality of bit line contact recesses exposing each of said plurality of active regions, wherein each of said plurality of bit line contacts is located in each of said bit line contact recesses.

8. The semiconductor memory device according to claim 7, wherein the first spacer and the contact plug are located in each of the bit line contact recess regions.

9. The semiconductor memory device according to claim 1, wherein the first spacer is in direct contact with the substrate.

10. The semiconductor memory device of claim 7, further comprising a metal residue in each of said bit line contact recess regions and between said bit line contact and said first spacer.

11. The semiconductor memory device according to claim 1, wherein a portion of the second spacers wraps around sidewalls of the first spacers and directly contacts sidewalls of the bit lines.

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