CN111968977B

CN111968977B - Semiconductor memory device and method of forming the same

Info

Publication number: CN111968977B
Application number: CN202010901360.4A
Authority: CN
Inventors: 张钦福; 冯立伟; 洪士涵; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-04-22
Anticipated expiration: 2040-08-31
Also published as: CN111968977A

Abstract

The invention discloses a semiconductor memory device and a forming method thereof. The dummy bit line is disposed outside the bit lines along the second direction, a sidewall of the dummy bit line is provided with a plurality of protrusions, the protrusions extend from top surfaces to bottom surfaces of the bit lines, and the protrusions have the same length in the second direction. Therefore, the protruding parts can be used for isolating the gates extending out of the bit lines, and the semiconductor memory device with better component reliability is formed under the condition of simplified manufacturing process.

Description

Semiconductor memory device and method of forming the same

Technical Field

The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to semiconductor memory devices and methods of forming the same.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it has gradually replaced the DRAM cell with a planar gate structure under the current trend of mainstream development because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure.

Generally, a DRAM cell with a recessed gate structure includes a transistor element and a charge storage device to receive voltage signals from the bit line and the word line. However, due to the limitations of the process technology, the conventional DRAM cell with the recessed gate structure still has many drawbacks, and further improvements and improvements are needed to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

An objective of the present invention is to provide a semiconductor memory device and a method for forming the same, in which an insulating structure between a plurality of plugs and a plurality of protrusions on sidewalls of dummy bitlines are simultaneously formed by a self-aligned double patterning process. Therefore, the insulating structures can be used for isolating each plug, and the word lines extending to the peripheral area are further isolated through the protruding parts, so that the semiconductor memory device with better component reliability is formed under the condition of simplified manufacturing process, and the efficiency of the semiconductor memory device is improved.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate; a plurality of gates; a plurality of bit lines; and two dummy bitlines. A plurality of gates are disposed in the substrate along a first direction. The bit lines are arranged on the substrate along a second direction, and the second direction is perpendicular to the first direction. Two dummy bit lines are disposed outside the bit lines along the second direction, a sidewall of each dummy bit line is provided with a plurality of protrusions, the protrusions extend from a top surface to a bottom surface of each bit line, and the protrusions have the same length in the second direction.

To achieve the above objective, one embodiment of the present invention provides a method for forming a semiconductor memory device, which includes the following steps. First, a substrate is provided, and a plurality of gates are formed in the substrate, wherein the gates are arranged along a first direction. A plurality of bit lines are formed on the substrate and arranged along a second direction, wherein the second direction is perpendicular to the first direction. Then, two dummy bit lines are formed outside the bit lines, the dummy bit lines are arranged along the second direction, a plurality of protrusions are formed on the sidewalls of the dummy bit lines, the protrusions extend from the top surface to the bottom surface of the bit lines, and the protrusions have the same length in the second direction.

Drawings

FIGS. 1 to 7 are schematic diagrams illustrating a method for forming a semiconductor memory device according to a first preferred embodiment of the present invention; wherein

FIG. 1 is a schematic top view of a semiconductor memory device according to the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a cross-sectional view of a semiconductor memory device after forming a bit line according to the present invention;

FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 5 is a schematic top view of a semiconductor memory device according to the present invention undergoing a self-aligned double layer patterning process;

FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 5; and

FIG. 7 is a perspective view of a semiconductor memory device after forming an insulating structure according to the present invention;

FIGS. 8 to 9 are schematic diagrams illustrating a method for forming a semiconductor memory device according to a second preferred embodiment of the present invention; wherein

FIG. 8 is a top view of a semiconductor memory device undergoing a self-aligned double layer patterning process; and

FIG. 9 is a schematic perspective view of a semiconductor memory device after forming an insulating structure according to the present invention;

FIGS. 10 to 11 are schematic diagrams illustrating a method of forming a semiconductor memory device according to a third preferred embodiment of the present invention; wherein the content of the first and second substances,

FIG. 10 is a top view of a semiconductor memory device undergoing a self-aligned double layer patterning process; and

fig. 11 is a perspective view of the semiconductor memory device of the present invention after forming an insulating structure.

Wherein the reference numerals are as follows:

100. a substrate; 101. an active region; 102. a storage area; 104. a peripheral region; 106. shallow trench isolation; 108. a trench; 110. a word line; 112. a dielectric layer; 113. a gate dielectric layer; 114. a gate electrode; 116. a first insulating layer; 124. a second insulating layer; 130. a plug hole; 160. a bit line; 160a, bit line contact plugs; 161. a semiconductor layer; 163. a barrier layer; 165. a metal layer; 167. a shielding layer; 169. a dummy bit line; 170. a sidewall layer; 180. a third insulating layer; 181a, a first patterned sacrificial pattern; 181b, a second patterned sacrificial pattern; 181d, patterning the sacrificial pattern; 182. a spacer; 190. an insulating structure; 191. a first portion; 193. a second portion; 200. and (4) plugging.

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below to explain the present invention and its intended effects.

Referring to fig. 1 to 7, a method for forming a semiconductor memory device according to a first preferred embodiment of the present invention is shown, wherein fig. 1, 3 and 5 are top views of a semiconductor memory device in a manufacturing process, and fig. 2, 4 and 6 are cross-sectional views along a cut line a-a' in fig. 1, 3 and 5, respectively.

In the present embodiment, the semiconductor memory device is, for example, a recessed gate random access memory (DRAM), which includes at least one transistor element (not shown) and at least one capacitor structure (not shown) as a minimum unit in a DRAM array and receives voltage signals from a Word Line (WL) 110 and a Bit Line (BL) 160. First, as shown in fig. 1 and 2, the semiconductor memory device includes a memory cell region 102 and a peripheral region 104 surrounding the memory cell region 102. Specifically, the semiconductor memory device includes a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, etc., a plurality of Active Areas (AA) 101 are defined in a memory region 102 of the substrate 100, and the active areas 101 extend in parallel and spaced apart from each other along a first direction D1 and are arranged in a matrix. A plurality of buried gates 114 are formed in the substrate 100 and can be used as a Buried Word Line (BWL) 110. The gates 114 extend parallel to each other along a second direction D2, and cross under the active regions 101 (in the first direction D1), as shown in fig. 1.

In one embodiment, the semiconductor memory device can be formed by the following steps, but is not limited thereto. First, at least one Shallow Trench Isolation (STI) 106 is formed in the substrate 100 to define each active region 101 shown in fig. 1 in the substrate 100. Next, a plurality of trenches 108 are formed in the substrate 100, each trench 108 is parallel to each other and extends toward the second direction D2, and a dielectric layer 112 covering the entire surface of each trench 108, a gate dielectric layer 113 and a buried gate 114 filling the bottom half of each trench 108, and a first insulating layer 116 filling the top half of each trench 108 are sequentially formed in each trench 108, wherein the top surface of the first insulating layer 116 is flush with the surface of the substrate 100, as shown in fig. 2. Thus, the gates 114 in each trench 108 are similarly parallel to each other and extend toward the second direction D2 to form the word line 110 shown in fig. 1.

Then, as shown in fig. 2, a second insulating layer 124 and a plurality of plug holes 130 are formed on the surface of the substrate 100, wherein the plug holes 130 are located between two adjacent word lines 110 and expose a portion of the substrate 100. The second insulating layer 124 includes, for example, an oxide-nitride-oxide (ONO) structure to cover the substrate 100 and the word lines 110 therein. The plug hole 130 may be formed using the following steps, but is not limited thereto. First, a mask structure (not shown) is formed on the substrate 100, the mask structure may have at least one opening (not shown) for defining the plug hole 130, and a portion of the second insulating layer 124 is exposed, an etching process is performed using the mask structure to remove the second insulating layer 124 exposed from the opening and a portion of the substrate 100 therebelow, so as to form the plug hole 130 in the substrate 100, and then the mask structure is completely removed. In one embodiment, an ion implantation process, such as an anti-punch-through (anti-punch-through) ion implantation process, may be performed during the formation of the plug hole 130 to further form a doped region (not shown) in the substrate 100 exposed by the plug hole 130, so as to achieve the effect of avoiding current leakage.

As shown in fig. 3 to 4, a plurality of bit lines 160 and dummy bit lines 169 are formed on the substrate 100. In the present embodiment, the bit lines 160 and the dummy bit lines 169 may be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but not limited thereto. In detail, a semiconductor layer (not shown, for example, a polysilicon layer) is first formed on the substrate 100, the plug hole 130 is filled and further covered on the substrate 100, and then a barrier layer (not shown, for example, including a titanium layer and/or a titanium nitride layer), a metal layer (not shown, for example, a low-resistance metal such as tungsten, aluminum or copper), and a shielding layer (not shown, for example, an insulating material such as silicon nitride, silicon oxide or silicon carbonitride) are sequentially formed on the semiconductor layer, but not limited thereto. Then, the self-aligned double patterning process or the self-aligned reverse patterning process is performed to pattern the semiconductor layer, the barrier layer, the metal layer and the shielding layer to form a plurality of bit lines 160 and two dummy bit lines 169 on the substrate 100. As shown in fig. 3, a plurality of bit lines 160 are formed in the memory region 102, and two dummy bit lines 169 are formed in the peripheral region 104 and located on opposite sides of the plurality of bit lines 160 in the second direction D2. The bit lines 160 and the dummy bit lines 169 extend in parallel along a third direction D3, such that the bit lines 160 can simultaneously cross the active regions 101 in the first direction D1 and the word lines 110 in the second direction D2, wherein the third direction D3 is different from the first direction D1 and the second direction D2, and is preferably perpendicular to the second direction D2 and not perpendicular to the first direction D1, but not limited thereto. In the present embodiment, the width (e.g., the width in the second direction D2) W2 of each dummy bit line 169 is preferably greater than the width of each bit line 160, but not limited thereto. Thus, when the fabrication process of the bit line 160 and the dummy bit line 169 is performed, the fabrication process of the bit line 160 is less affected by the fabrication process of the adjacent dummy bit line 169, and a bit line with better device reliability can be formed.

In addition, as shown in fig. 4, each bit line 160 is composed of the semiconductor layer 161, the barrier layer 163, the metal layer 165 and the shielding layer 167 after the patterning process, and the semiconductor layer 161 filled in each plug hole 130 forms each Bit Line Contact (BLC) 160a, which is located below each bit line 160 and between two adjacent word lines 110. Thus, the bit line contact plug 160a and the bit line 160 can be integrally formed, and the bit line 160 and the word line 110 can be isolated from each other by the second insulating layer 124 and can be further electrically connected to a source/drain region of the at least one transistor element in the semiconductor memory device through the bit line contact plug 160 a. On the other hand, each dummy bit line 169 is composed of a patterned semiconductor layer (not shown), a barrier layer (not shown), a metal layer (not shown), and a shielding layer (not shown). Then, a sidewall layer 170 is formed on the sidewalls of the bit lines 160 and the dummy bit lines 169. In one embodiment, the sidewall layer 170 may have a single layer structure (as shown in fig. 3), for example, comprising a dielectric material that is the same as the whole, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or a composite layer structure, for example, comprising a first sidewall layer, a second sidewall layer, etc., which are sequentially formed, and the first sidewall layer and the second sidewall layer may comprise different dielectric materials.

Next, as shown in fig. 5 to 7, an insulating structure 190 is formed on the substrate 100. In the present embodiment, the insulating structure 190 may be formed by a self-aligned double patterning process, but is not limited thereto. In detail, a third insulating layer 180 is formed on the substrate 100 to fill the space between the bit line 160 and the dummy bit line 169, and further covers the substrate 100 on both sides of the dummy bit line 169. Also, the top surface of the third insulating layer 180 may be flush with the top surfaces of the bit lines 160 and the dummy bit lines 169, as shown in fig. 6. In one embodiment, the third insulating layer 180 may comprise a suitable insulating material, such as silicon nitride, silicon oxide, or silicon carbonitride, preferably, but not limited to, the same insulating material as the mask layer 167 over the bit line 160. Then, a plurality of first patterned sacrificial patterns (mangrels) 181a and a plurality of second patterned sacrificial patterns 181b are formed in a stripe shape above the third insulating layer 180, the bit lines 160 and the dummy bit lines 169 by a photolithography process, and then deposition and etch-back processes are sequentially performed to form a sidewall spacer 182 on sidewalls of each of the first patterned sacrificial patterns 181a and each of the second patterned sacrificial patterns 181b, as shown in fig. 5 and 6. The first sacrificial pattern 181a and the second sacrificial pattern 181b extend in parallel in the second direction D2 and have the same length (not shown). Also, each of the first sacrificial pattern 181a and each of the second sacrificial pattern 181b are preferably formed between two adjacent word lines 110, such that a portion of the sidewall portion 182 (i.e., a portion in the second direction D2) formed on the sidewall of the first sacrificial pattern 181a and the second sacrificial pattern 181b can be aligned with the word line 110 in the substrate 100, as shown in fig. 6.

It is noted that two ends of the first sacrificial pattern 181a and the second sacrificial pattern 181b may respectively extend to the dummy bit lines 169 at two sides (i.e., to the peripheral region 104), such as to the outer side (the side away from the bit lines 160) or the inner side (the side adjacent to the bit lines 160) of the dummy bit lines 169. In other words, in the embodiment, although the first sacrificial patterns 181a (or the second sacrificial patterns 181b) are aligned with each other, the first sacrificial patterns 181a and the second sacrificial patterns 181b are not aligned with each other but are arranged in a staggered manner. For example, the two ends of the adjacent first sacrificial pattern 181a and the second sacrificial pattern 181b are staggered in the second direction D2 by a distance, such as a distance about equal to or less than the line width of the dummy bit line 169, as shown in fig. 5, but not limited thereto. In this case, a portion of the sidewall sub-patterns 182 (the portion in the third direction D3, i.e., the horizontal portion) formed on the sidewalls of the first patterned sacrificial pattern 181a and a portion of the sidewall sub-patterns 182 (the portion in the third direction D3, i.e., the horizontal portion) formed on the sidewalls of the second patterned sacrificial pattern 181b are also staggered by a distance, e.g., a distance about equal to or less than the line width of the dummy bit line 169, as shown in fig. 5. Also, the portion (i.e., horizontal portion) of the sidewall sub-region 182 may fall just above the sidewall outside the dummy bit line 169 or above the dummy bit line 169, as shown in FIG. 5. The portion of the sidewall sub-region 182 that falls over the sidewall outside the dummy bit line 169 may have a thickness in the second direction D2.

Subsequently, the first sacrificial pattern 181a and the second sacrificial pattern 181b are completely removed, and an etching process is performed on the underlying third insulating layer 180 through the coverage of the spacer 182, so as to form an insulating structure 190, as shown in fig. 7. As such, the insulating structure 190 may include a plurality of first portions 191 extending in the second direction D2, and a plurality of second portions 193 extending in the third direction D3, each second portion 193 being located opposite to two adjacent first portions 191. In detail, the first portions 191 are formed corresponding to the portions (i.e., vertical portions) of the sidewall portions 182 in the second direction D2, however, the portions of the sidewall portions 182 are partially shielded by the bit lines 160 in the third direction D3 during the pattern transfer, so that the formed first portions 191 extend in the second direction D2 in parallel and are separated from each other, and adjacent first portions 191 have the same interval to present a matrix arrangement, as shown in fig. 7. In other words, the first portions 191 of the insulating structures and the bit lines 160 disposed in the third direction D3 are disposed alternately. On the other hand, the second portion 193 is formed to correspond to the portion (i.e., horizontal portion) of the sidewall sub 182 in the third direction D3 and have the same thickness as the portion of the sidewall sub 182, however, the portion of the sidewall sub 182 is blocked by the dummy bit line 169 in the third direction D3 during the pattern transfer, so that the second portion 193 is formed only on the sidewall outside the dummy bit line 169, and there is a larger space between the adjacent second portions 193, as shown in fig. 7.

It should be noted that the second portion 193 of the insulating structure 190 may be formed on the sidewall of the dummy bit line 169 at a position just outside the dummy bit line 169, so as to form a plurality of protrusions on the sidewall of the dummy bit line 169. Wherein the top surfaces of the first and second portions 191 and 193 (i.e., the protrusions) of the insulating structure 190 are coplanar with the top surface of the dummy bit line 169, so that the first and second portions 191 and 193 (i.e., the protrusions) of the insulating structure 190 have the same height as the dummy bit line 169 on the substrate 100, and the second portions 193 (i.e., the protrusions) of the insulating structure 190 have the same length in the third direction D3, as shown in fig. 7. The second portion 193 (i.e., the protrusion) of the isolation structure 190, which is located in the peripheral region 104, can further isolate the dummy bit line 169 from the word line 110 extending into the peripheral region 104, so as to prevent short circuit caused by too close arrangement of the plug electrically connecting the dummy bit line 169 and the plug electrically connecting the word line 110 in the back-end process. Then, as shown in fig. 7, a plurality of plugs 200 may be formed on the substrate 100 to directly contact a portion of the substrate 100. Plugs 200 are formed in the memory region 102, wherein the plugs 200 are alternately arranged with the bit lines 160 in the second direction D2 and are isolated from each other by the sidewall layers 170 on both sides of the bit lines 160, and the plugs 200 are alternately arranged with the first portions 191 of the insulating structures 190 in the third direction D3 and are isolated from the plugs 200 by the first portions 191.

Thus, the method of forming the semiconductor memory device according to the first preferred embodiment of the present invention is completed. The method of forming the present embodiment forms the insulating structure 190 by the self-aligned double patterning process, wherein each plug 200 is isolated by the first portion 191 of the insulating structure 190, and the word line 110 extending into the peripheral region 104 is isolated by the second portion 193 of the insulating structure 190. Thus, a semiconductor memory device with better device reliability can be formed under the simplified manufacturing process, so as to improve the performance of the semiconductor memory device.

It should be readily apparent to those skilled in the art that the semiconductor memory device of the present invention may have other aspects or be formed by other manufacturing processes without limitation to the above embodiments so as to meet the actual product requirements. For example, in the above-described embodiments, the insulating structure 190 is formed by the self-aligned double patterning process, but the invention is not limited thereto, and in another embodiment, the insulating structure may be formed by a self-aligned reverse patterning process. Therefore, further description will be made below with respect to other embodiments or variations of the semiconductor memory device and the method of forming the same. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 8 to 9, a method for forming a semiconductor memory device according to a second preferred embodiment of the present invention is shown, in which fig. 8 is a top view of a semiconductor memory device in a manufacturing process, and fig. 9 is a perspective view of a semiconductor memory device in the manufacturing process. The forming method of this embodiment is substantially the same as the forming method of the first preferred embodiment, as shown in fig. 1 to 5, and the description of the same parts is omitted. The main difference between the present embodiment and the previous embodiments is the fabrication of the insulating structure 190.

In the present embodiment, the insulating structure 190 may also be formed by a self-aligned double patterning process, and the self-aligned double patterning process of the present embodiment is substantially the same as that of the previous embodiments, except that the first patterned sacrificial pattern 181a and the second patterned sacrificial pattern 181b are staggered in the second direction D2, for example, from about 1/2 to about 1/3 with respect to the line width of the dummy bit line 169, as shown in fig. 8, but not limited thereto. That is, the two ends of the first sacrificial pattern 181a and the second sacrificial pattern 181b respectively extend to the outer sidewall (the side away from the bit line 160) of the dummy bit line 169 or extend to the dummy bit line 169, so that a portion of the sidewall portion 182 (the portion in the third direction D3, i.e., the horizontal portion) formed on the sidewall of the first sacrificial pattern 181a and a portion of the sidewall portion 182 (the portion in the third direction D3, i.e., the horizontal portion) formed on the sidewall of the second sacrificial pattern 181b can be completely above the sidewall outside the dummy bit line 169 or partially above the sidewall outside the dummy bit line 169 and have different thicknesses, T2, as shown in fig. 8.

Subsequently, the first sacrificial pattern 181a and the second sacrificial pattern 181b are completely removed, and an etching process is performed on the underlying insulating layer (not shown) through the coverage of the spacer 182, so as to form an insulating structure 190, as shown in fig. 9. As such, the insulating structure 190 may include a plurality of first portions 191 extending in the second direction D2, and a plurality of second portions 193 extending in the third direction D3. In detail, the first portions 191 of the first portions 191 are formed corresponding to the portions (i.e. vertical portions) of the sidewall portions 182 in the second direction D2, however, the portions of the sidewall portions 182 are partially shielded by the bit lines 160 in the third direction D3 during the pattern transfer, so that the first portions 191 of the first portions 191 are formed to extend in the second direction D2 in parallel and separated from each other, and adjacent first portions 191 have the same interval to form a matrix arrangement, as shown in fig. 9. In other words, the first portions 191 of the insulating structures and the bit lines 160 disposed in the third direction D3 are disposed alternately. On the other hand, the second portion 193 is formed corresponding to the portion of the sidewall spacer 182 in the third direction D3 (i.e., the horizontal portion), however, the portion of the sidewall spacer 182 is partially blocked by the dummy bit line 169 in the third direction D3 during the pattern transfer, so that the second portion 193 is formed with a different thickness, T2. The second portions 193 having a larger thickness and the second portions 193 having a smaller thickness are alternately arranged in this order in the third direction D3, as shown in fig. 9.

In this way, the second portions 193 (i.e., the protrusions) of the insulating structure 190 of the present embodiment can also be a plurality of protrusions on the sidewalls of the dummy bit line 169, wherein the top surfaces of the first portions 191 and the second portions 193 (i.e., the protrusions) of the insulating structure 190 are coplanar with the top surface of the dummy bit line 169, so that the first portions 191 and the second portions 193 (i.e., the protrusions) of the insulating structure 190 have the same height on the substrate 100 as the dummy bit line 169, and the second portions 193 (i.e., the protrusions) of the insulating structure 190 have the same length in the third direction D3, as shown in fig. 9. The second portion 193 (i.e., the protrusion) of the isolation structure 190 may further isolate the dummy bit line 169 and the word line 110 extending into the peripheral region 104, so as to prevent short circuit caused by the proximity of the plug electrically connected to the dummy bit line 169 and the plug electrically connected to the word line 110 in the back end fabrication process. Thereafter, a plurality of plugs 200 may be formed on the substrate 100 as well. Plugs 200 are formed in the memory region 102, wherein the plugs 200 are alternately arranged with the bit lines 160 in the second direction D2 and are isolated from each other by the sidewall layers 170 on both sides of the bit lines 160, and the plugs 200 are alternately arranged with the first portions 191 of the insulating structures 190 in the third direction D3 and are isolated from the plugs 200 by the first portions 191.

Thus, the method of forming the semiconductor memory device according to the second preferred embodiment of the present invention is completed. The present embodiment also forms the insulating structure 190 by the self-aligned double patterning process, isolating the plugs 200 through the first portion 191 of the insulating structure 190, and isolating the word lines 110 extending into the peripheral region 104 through the second portion 193 of the insulating structure 190. Thus, a semiconductor memory device having improved device reliability can be formed with a simplified manufacturing process to improve the performance thereof.

Referring to fig. 10 to 11, a method for forming a semiconductor memory device according to a third preferred embodiment of the present invention is shown, in which fig. 10 is a top view of a semiconductor memory device in a manufacturing process, and fig. 11 is a perspective view of a semiconductor memory device in the manufacturing process. The forming method of this embodiment is substantially the same as the forming method of the first or second preferred embodiment, as shown in fig. 1 to 5, and the description of the same parts will not be repeated. The main difference between the present embodiment and the previous embodiments is the fabrication of the insulating structure 190.

In the present embodiment, the insulating structure 190 can also be formed by a self-aligned double patterning process, and the self-aligned double patterning process of the present embodiment is substantially the same as that of the previous embodiments, except that the plurality of sacrificial patterns 181d are aligned and arranged side by side, and both ends of each sacrificial pattern 181d can extend to the outer sidewalls (the side away from the bit lines 160) of the dummy bit lines 169 on both sides. As such, a portion of the sidewall sub-regions 182 (i.e., the horizontal portion in the third direction D3) formed on the sidewalls of the sacrificial pattern 181D may be completely located above the sidewalls outside the dummy bit lines 169 and have a thickness, as shown in fig. 10.

Subsequently, the sacrificial pattern 181d is completely removed, and an etching process is performed on the underlying insulating layer (not shown) through the coverage of the spacer 182, so as to form an insulating structure 190, as shown in fig. 11. As such, the insulating structure 190 may include a plurality of first portions 191 extending in the second direction D2, and a plurality of second portions 193 extending in the third direction D3. In detail, the first portions 191 are formed corresponding to the portions (i.e. vertical portions) of the sidewall portions 182 in the second direction D2, however, the portions of the sidewall portions 182 are partially shielded by the bit lines 160 in the third direction D3 during the pattern transfer, so that the first portions 191 are formed to extend in parallel and separated in the second direction D2 to form a matrix arrangement, as shown in fig. 11. On the other hand, the second portion 193 is formed corresponding to the portion (i.e., horizontal portion) of the sidewall portion 182 in the third direction D3, such that the second portion 193 can be formed on the sidewall just outside the dummy bit line 169, and thus become a plurality of protrusions on the sidewall of the dummy bit line 169, wherein the top surfaces of the first portion 191 and the second portion 193 (i.e., each protrusion) of the insulating structure 190 are coplanar with the top surface of the dummy bit line 169, such that the height of the first portion 191 and the second portion 193 (i.e., each protrusion) of the insulating structure 190 is the same as the height of the dummy bit line 169 on the substrate 100, and each second portion 193 (i.e., each protrusion) of the insulating structure 190 has the same length in the third direction D3 and the same thickness in the second direction D2, as shown in fig. 11. The protrusion is located in the peripheral region 104, and therefore, the dummy bit line 169 and the word line 110 extending to the peripheral region 104 can be further isolated, so as to prevent short circuit caused by too close arrangement of the plug electrically connected to the dummy bit line 169 and the plug electrically connected to the word line 110 in the back end fabrication process.

Thereafter, a plurality of plugs 200 may be formed on the substrate 100 as well. Plugs 200 are formed in the memory region 102, wherein the plugs 200 are alternately arranged with the bit lines 160 in the second direction D2 and are isolated from each other by the sidewall layers 170 on both sides of the bit lines 160, and the plugs 200 are alternately arranged with the first portions 191 of the insulating structures 190 in the third direction D3 and are isolated from the plugs 200 by the first portions 191. Thus, the method of forming the semiconductor memory device according to the third preferred embodiment of the present invention is completed. The method of forming the present embodiment also forms the insulating structure 190 by the self-aligned double patterning process, wherein each plug 200 is isolated by the first portion 191 of the insulating structure 190, and the word line 110 extending into the peripheral region 104 is isolated by the second portion 193 of the insulating structure 190. Thus, a semiconductor memory device having improved device reliability can be formed with a simplified manufacturing process to improve the performance thereof.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a plurality of gates disposed in the substrate along a first direction;

a plurality of bit lines disposed on the substrate along a second direction, the second direction being perpendicular to the first direction; and

the dummy bit line is arranged outside the plurality of bit lines along the second direction, a plurality of protruding parts are arranged on the side wall of the dummy bit line, and the top surfaces of the protruding parts are coplanar with the top surfaces of the dummy bit line;

each bit line contact plug is respectively positioned below each bit line and between two adjacent word lines.

2. The semiconductor memory device according to claim 1, wherein the protruding portions have the same length in the second direction.

3. The semiconductor memory device according to claim 1, wherein each of the protruding portions has a different thickness in the first direction.

4. The semiconductor memory device according to claim 3, wherein the respective protruding portions different in thickness are alternately arranged in the second direction.

5. The semiconductor memory device according to claim 1, further comprising:

and a plurality of insulation structures arranged on the substrate along the first direction and arranged on the plurality of gates, wherein the plurality of bit lines and the plurality of insulation structures are arranged in a staggered manner.

6. The semiconductor memory device according to claim 5, wherein each of the pairs of protruding portions is located in any two adjacent ones of the plurality of insulating structures.

7. The semiconductor memory device according to claim 5, wherein the plurality of insulating structures and the plurality of protruding portions comprise the same material.

8. The semiconductor memory device according to claim 5, wherein a plurality of the insulating structures and a plurality of the protrusions have the same height on the substrate.

9. The semiconductor memory device according to claim 5, further comprising:

and a plurality of plugs disposed on the substrate, the plurality of plugs being alternately disposed with the plurality of bit lines in the first direction and alternately disposed with the plurality of insulating structures in the second direction.

10. The semiconductor memory device according to claim 1, wherein each of the bit lines comprises a semiconductor layer, a barrier layer, a metal layer, and a shield layer stacked in sequence, and the shield layer and the plurality of protrusions comprise the same material.

11. The semiconductor memory device according to claim 1, wherein a line width of the dummy bit line is larger than a line width of each of the bit lines.

12. A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming a plurality of gates in the substrate, wherein the plurality of gates are arranged along a first direction;

forming a plurality of bit lines on the substrate, wherein the bit lines are arranged along a second direction, and the second direction is perpendicular to the first direction; and

and forming a dummy bit line outside the bit lines, wherein the dummy bit line is arranged along the second direction, a plurality of protruding parts are formed on the side wall of the dummy bit line, and the top surfaces of the protruding parts are coplanar with the top surface of the dummy bit line.

13. The method of claim 12, further comprising:

and forming a plurality of insulation structures on the substrate, wherein the insulation structures are arranged along the first direction and are positioned on the gates, and the bit lines penetrate through the insulation structures.

14. The method of claim 13, wherein the plurality of isolation structures and the plurality of protrusions are formed together by a self-aligned double patterning process.

15. The method of claim 13, further comprising:

and forming a plurality of plugs on the substrate, wherein the plurality of plugs are alternately arranged with the plurality of bit lines in the first direction and are alternately arranged with the plurality of insulating structures in the second direction.

16. The method of claim 13, wherein a plurality of the insulating structures and a plurality of the protrusions have the same height above the substrate.

17. The method of claim 12, wherein each of the protruding portions has a different thickness in the first direction.

18. The method of forming a semiconductor memory device according to claim 16, wherein the respective protruding portions different in thickness are alternately provided in the second direction.