CN212136449U

CN212136449U - Memory device

Info

Publication number: CN212136449U
Application number: CN202021203646.7U
Authority: CN
Inventors: 童宇诚; 张钦福; 詹益旺
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2020-12-11
Anticipated expiration: 2030-06-24

Abstract

The utility model provides a memory, which directly utilizes a bit line structure to define a plurality of node contact windows, and because the height and the depth-width ratio of the node contact windows are lower, the requirements on the forming process of a first electrical transmission layer are lower when the first electrical transmission layer is formed in the node contact windows; the first electrical transmission layer is formed, then the interval patterns are formed, the adjacent interval patterns are separated by the opening, the opening at least exposes part of the top of the first electrical transmission layer, the second electrical transmission layer is formed in the opening, the height and the depth-to-width ratio of the opening are lower at the moment, when the second electrical transmission layer is formed in the opening, the forming process requirement on the second electrical transmission layer is lower, and the node contact structure is formed after the second electrical transmission layer is electrically connected with the first electrical transmission layer, so that the adverse effect on a memory can not be caused in the step.

Description

Memory device

Technical Field

The utility model relates to a semiconductor manufacturing technology field especially relates to a memory.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory further comprises a plurality of bit line structures, each bit line structure is electrically connected with a corresponding memory cell, the memory further comprises a capacitor structure, the capacitor structure is used for storing charges representing stored information, and the memory cells can be electrically connected with the capacitor structure through a node contact structure, so that the storage function of each memory cell is realized.

At present, the method for forming the memory comprises the following steps: forming a stacked bit line conductive layer, a bit line shielding layer and a dielectric layer on a substrate and imaging, wherein the rest of the bit line conductive layer and the bit line shielding layer form a bit line structure, the rest of the dielectric layer forms an insulating pattern, and a node contact window is defined by using the bit line structure and the insulating pattern; then filling a conductive material in the node contact window, wherein the conductive material also extends the insulating pattern; and finally, etching the conductive material to form a plurality of openings so as to divide the conductive material into a plurality of node contact structures at intervals. The insulating pattern is used for protecting the bit line structure when the conductive material is etched to form the opening, so that the bit line structure is prevented from being damaged by etching, but the insulating pattern can increase the height of the node contact window, so that the depth-to-width ratio of the node contact window is increased, the difficulty of filling the conductive material in the node contact window is increased, and the process requirement for forming the conductive material is extremely high; in addition, when the bit line conducting layer, the bit line shielding layer and the dielectric layer are patterned, the stacked film layers are thick, so that the etching difficulty is very high, and the requirement on the etching process is extremely high.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a memory has reduced the technological requirement when preparing the memory to can not produce harmful effects to the performance of memory.

In order to achieve the above object, the present invention provides a memory, including:

a substrate;

the bit line structures are positioned on the substrate and define a plurality of node contact windows, and each bit line structure comprises a bit line conductive layer and a bit line shielding layer covering the bit line conductive layer;

a first electrical transmission layer located in the node contact, the first electrical transmission layer at least filling a part of the depth of the node contact;

the second electric transmission layer covers part of the top of the first electric transmission layer and part of the top of the bit line shielding layer and is electrically connected with the first electric transmission layer; and the number of the first and second groups,

and the spacing pattern covers the rest top of the bit line shielding layer and the rest top of the first electric transmission layer so as to space the adjacent second electric transmission layers.

Optionally, the first electrical transmission layer completely fills the node contact, wherein a bottom of the second electrical transmission layer is flush with a top of the bit line shielding layer.

Optionally, the spacer pattern comprises a layer of insulating material.

Optionally, the spacer pattern further includes a buffer material layer, and the buffer material layer is located between the insulating material layer and the first electrical transmission layer and between the insulating material layer and the bit line shielding layer.

Optionally, the material of the buffer material layer is a material having an etching selection ratio with the bit line shielding layer.

Optionally, the material of the buffer material layer is a conductive material, and the memory further includes:

and the insulating side wall at least covers the side wall of the interval pattern so as to electrically isolate the buffer material layer from the first electrical transmission layer and the second electrical transmission layer.

The utility model also provides a memory, include:

a substrate;

the second electrical transmission layer fills the node contact window with the residual depth and extends upwards, and the second electrical transmission layer is also electrically connected with the first electrical transmission layer;

the interval pattern covers the top of the bit line shielding layer to interval the adjacent second electric transmission layers; and the number of the first and second groups,

and the insulating side wall is at least positioned on the side wall of the interval pattern so as to electrically isolate the interval pattern from the first electrical transmission layer and the second electrical transmission layer.

Optionally, the spacer pattern includes a buffer material layer and an insulating material layer covering the buffer material layer, and the buffer material layer is made of a conductive material having an etching selection ratio with respect to the bit line shielding layer.

Optionally, the material of the buffer material layer is a conductive material.

Optionally, the buffer material layer further extends from the bit line shielding layer to the node contact window of the remaining depth, and the insulating sidewall is further located between the buffer material layer and the first electrical transmission layer.

The utility model provides a memory has following beneficial effect:

1) the bit line structure is directly utilized to define a plurality of node contact windows, and because the height and the depth-to-width ratio of the node contact windows are lower, the requirements on the forming process of a first electrical transmission layer are lower when the first electrical transmission layer is formed in the node contact windows; forming a first electrical transmission layer and then forming spacing patterns, wherein the adjacent spacing patterns are spaced by an opening, the opening at least exposes part of the top of the first electrical transmission layer, and a second electrical transmission layer is formed in the opening, because the height and the aspect ratio of the opening are lower at the moment, when the second electrical transmission layer is formed in the opening, the forming process requirement on the second electrical transmission layer is lower, and the second electrical transmission layer is electrically connected with the first electrical transmission layer to form a node contact structure, so that the adverse effect on a memory can not be caused in the step;

2) the second electrical transmission layer can extend to cover the top of the part of the bit line structure, and the width of the top surface of the second electrical transmission layer is increased, so that the area of a capacitor structure formed on the second electrical transmission layer subsequently can be increased, and the storage performance of the memory is improved;

3) the interval pattern comprises a buffer material layer and an insulating material layer covering the buffer material layer, and the buffer material layer can provide a buffer effect in an opening formed by etching, so that the first electric transmission layer and the bit line shielding layer are protected from being excessively etched;

4) when the buffer material layer is made of a conductive material, the etching selection ratio of the buffer material layer to the bit line shielding layer can be increased, so that the bit line structure is better protected.

Drawings

Fig. 1 is a flowchart of a method for forming a memory according to an embodiment of the present invention;

fig. 2a is a simplified layout of a memory according to a first embodiment of the present invention, and fig. 2b to fig. 2g are schematic structural diagrams corresponding to corresponding steps of a method for forming a memory according to a first embodiment of the present invention, wherein fig. 2b to fig. 2f are schematic cross-sectional diagrams of the structure in fig. 2a along aa 'and bb' directions;

fig. 3a and fig. 3b are schematic structural diagrams of a memory according to a second embodiment of the present invention;

fig. 4a to fig. 4c are schematic structural diagrams of a memory according to a third embodiment of the present invention;

fig. 5a and 5b are schematic structural diagrams of a memory according to a fourth embodiment of the present invention;

wherein the reference numerals are:

100-a substrate; AA-active region; SIT-trench isolation structure; 500-node contact window; 510-an opening; 610-an insulating layer; 620-stacking material layers; 630-electrode grooves;

a WL-word line structure;

a BL-bit line structure; 200 a-a first bit line conductive layer; 200 b-a second bit line conductive layer; 200 c-a third bitline conductive layer; 200 d-bit line shield layer; 200 e-spacer sidewalls;

an SC-node contact structure; 300 a-a conductive contact layer; 300 b-a first signal transmission layer; 300 c-a second signal transmission layer; 300 d-conductive barrier layer;

400-space pattern, 400 a-buffer material layer; 400 b-a layer of insulating material; 400 c-insulating side walls.

Detailed Description

The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

Fig. 1 is a schematic structural diagram of a method for forming a memory according to an embodiment of the present invention. As shown in fig. 1, the method for forming the memory includes:

step S100: providing a substrate, wherein a plurality of bit line structures are formed on the substrate, and the bit line structures define a plurality of node contact windows;

step S200: forming a first electrical transmission layer in the node contact window, wherein the first electrical transmission layer at least fills a part of the depth of the node contact window;

step S300: forming spacing patterns on the bit line structure, wherein the spacing patterns at least cover part of the top of the bit line structure, and the adjacent spacing patterns are spaced by an opening, and the opening at least exposes part of the top of the first electrical transmission layer; and the number of the first and second groups,

step S400: and forming a second electric transmission layer in the opening, and electrically connecting the second electric transmission layer with the first electric transmission layer.

Specifically, please refer to fig. 2a to 2g, which are schematic structural diagrams corresponding to corresponding steps of a method for forming a memory according to the present embodiment, wherein fig. 2b to 2g are schematic cross-sectional diagrams in the aa 'direction and the bb' direction of fig. 2a, and the method for forming a memory according to the present embodiment will be described in detail with reference to fig. 2a to 2 f.

Referring to fig. 2a and 2b, step S100 is performed to provide a substrate 100, wherein a trench isolation structure STI is formed in the substrate 100, and a plurality of active areas AA extending along a first predetermined direction (Z direction) are defined by the trench isolation structure SIT.

Referring to fig. 2a and 2b, word line structures WL are formed in the substrate 100, extending in a second predetermined direction (X-direction) and passing through the respective active areas AA and trench isolation structures STI. Optionally, a lateral width (width dimension in a direction perpendicular to the height direction) of the word line structure WL located in the active area AA is smaller than a lateral width of the word line structure WL located in the trench isolation structure STI; the bottom of the word line structure WL located in the active area AA is lower than the bottom of the word line structure WL located in the trench isolation structure STI.

The steps of forming the word line structure WL may be as follows:

forming a word line trench (not shown) in the substrate 100 and extending in a second predetermined direction;

forming a gate dielectric layer on the substrate 100, wherein the gate dielectric layer covers the inner wall of the word line trench and can be used as an insulating layer for isolating the word line from the active area AA;

then, a gate conductive layer is formed in the word line trench, wherein the gate conductive layer is a conductive film, such as polysilicon or tungsten. The grid conducting layer fills the word line groove with partial depth; specifically, the height of the gate conductive layer in the word line trench may be reduced, for example, by an etch-back process, so that the top surface of the gate conductive layer is lower than the upper surface of the substrate. Thus, the lower part of the word line groove is filled with the gate conductive layer, and the upper part of the word line groove is still in an empty state;

and forming a gate insulating layer on the gate conducting layer, wherein the gate insulating layer covers the gate conducting layer 200b and completely fills the word line groove, and the gate dielectric layer, the gate conducting layer and the gate insulating layer jointly form the word line structure WL.

It should be noted that although the drawings of the present embodiment do not show a mask layer on the surface of the substrate 100, it should be appreciated that, during the etching process of the substrate 100 to form the word line trench, a mask layer is usually formed on the surface of the substrate 100 to prevent the etching of the region of the substrate 100 that is not corresponding to the trench.

With continued reference to fig. 2b, the method of forming the memory further comprises: forming a source/drain region in the substrate 100, wherein a side edge boundary of the source/drain region extends to a side wall of the word line trench close to the top opening, and a bottom boundary of the source/drain region is lower than the top position of the gate conductive layer, so that the source/drain region and the gate conductive layer have an overlapped region which is opposite to each other, and in the overlapped region, the gate conductive layer and the source/drain region are separated from each other by the gate dielectric layer.

Specifically, the source and drain regions include a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line structure WL. In this embodiment, the side edge boundary of the first source/drain region further extends to the sidewall of the trench isolation structure STI.

It should be noted that, in this embodiment, after the word line trench is formed and the word line structure WL is formed, the source and drain regions are prepared. However, in other embodiments, the source and drain regions may be formed first, and then the word line trench and the word line structure WL are sequentially prepared, which is not limited herein.

Referring to fig. 2a and 2b, a plurality of bit line structures BL are formed on the substrate 100, the bit line structures BL extend along a third predetermined direction (Y direction), a plurality of node contacts 500 are defined by the plurality of bit line structures BL on the substrate 100, and the plurality of node contacts 500 are aligned and arranged in multiple rows in the second predetermined direction and the third predetermined direction. The node contact 500 in this embodiment refers to the area between the adjacent bit line structures BL and below the top of the bit line structures BL, that is, the top of the node contact 500 is flush with the top of the bit line structures BL.

Specifically, when the bit line structure BL is formed, the bit line trench needs to be formed first, and since the bit line trench forms the bit line structure BL in a subsequent step, the bit line trench needs to extend along the third predetermined direction. A part of the bit line trench extends into an active area AA of the substrate 100 and is located between two word line structures WL in the active area AA, and another part is located above the shallow trench isolation structure STI.

A bit line structure BL is then formed in the bit line trench. The bit line structure BL comprises three layers of conductive material layers which are sequentially stacked. Based on this, the formed bit line structure BL includes the first bit line conductive layer 200a, the second bit line conductive layer 200b, and the third bit line conductive layer 200 c. Further, the bit line structure BL further includes a bit line shielding layer 200d, and the bit line shielding layer 200d may be a patterned film layer and is formed above the three conductive material layers. Alternatively, for example, the patterned bit line shielding layer 200d is used to sequentially perform a patterning process on the underlying conductive material layer. In this embodiment, the method for forming the bit line structure BL further includes: and forming an interval side wall 200e on the side walls of the first bit line conductive layer 200a, the second bit line conductive layer 200b, the third bit line conductive layer 200c and the bit line shielding layer 200 d.

Referring to fig. 2b, after the node contact 500 is defined, further etching the substrate 100 at the bottom of the node contact 500 is further included, so that at least a portion of the bottom of the node contact 500 further extends into the active region of the substrate 100, so that the subsequently formed node contact structure has a better electrical connection effect with the active region AA.

Referring to fig. 2c, step S200 is performed to form a conductive contact layer 300a in the node contact 500, wherein the conductive contact layer 300a fills a portion of the depth of the node contact 500. In the present embodiment, the conductive contact layer 300a is filled in the node contact 500 to be electrically connected to the active region exposed in the node contact 500.

As shown in fig. 2c, a first electrical transmission layer 300b is formed, and the second conductive layer 300b covers the top of the conductive contact layer 300a and fills the node contact 500 with a partial depth. That is, in the present embodiment, when the first electrical transmission layer 300b is formed, the first electrical transmission layer 300b is formed on the conductive contact layer 300a, and the first electrical transmission layer 300b does not fill the node contact 500, and the top height of the first electrical transmission layer 300b is lower than the height of the opening of the node contact 500.

Optionally, the forming method of the first electrical transmission layer 300b may be:

forming a first electrical transmission material layer, wherein the first electrical transmission material layer fills the node contact window 500 and extends to cover the top of the bit line structure BL;

the first electrical transmission material layer is etched back, the first electrical transmission material layer on the top of the bit line structure BL is removed, a part of the height of the first electrical transmission material layer in the node contact window 500 is removed, and the remaining first electrical transmission material layer constitutes the first electrical transmission layer 300 b.

It should be understood that the larger the aspect ratio of the node contact 500, the higher the process requirement for preparing the first electrical transmission layer 300b, the more air gaps can be avoided from occurring in the first electrical transmission layer 300b, and the air gaps can be prevented from affecting the electrical conductivity of the subsequently formed node contact structure. In this embodiment, the bit line structure BL is directly used to define the node contact 500, and at this time, no additional dielectric layer is formed on the top of the bit line structure BL, and the height of the node contact 500 is small, which does not have strict requirements on the process for forming the first electrical transmission layer 300 b.

Referring to fig. 2c and 2d, step S300 is performed to form a spacer material layer on the bit line structure BL, wherein the spacer material layer covers the bit line structure BL and fills the node contact 500 with the remaining depth. Specifically, the spacer material layer includes a buffer material layer 400a and an insulating material layer 400b, the buffer material layer 400a covers the bit line structure BL and extends to cover the inner wall of the node contact window 500 at the remaining depth, and the insulating material layer 400b is located on the buffer material layer 400a and fills the node contact window 500 at the remaining depth.

In this embodiment, the thickness of the buffer material layer 400a is much smaller than that of the insulating material layer 400b, the buffer material layer 400a and the insulating material layer 400b are made of insulating materials having different materials, for example, the material of the buffer material layer 400a is silicon oxide, the material of the insulating material layer 400b is nitride, the material of the buffer material layer 400a and the material of the insulating material layer 400b have a larger etching selection ratio, but should not be limited thereto, the buffer material layer 400a and the insulating material layer 400b may be other insulating materials, the material of the insulating material layer 400b may also be a carbon-doped nitride (e.g., carbon-doped silicon nitride), the material of the buffer material layer 400a may also be carbide (e.g., silicon carbide) or other oxides (e.g., tantalum oxide, titanium oxide), etc., without limitation.

Referring to fig. 2e, the insulating material layer 400b and the buffer material layer 400a are etched to form a plurality of openings 510, the openings 510 penetrate through the spacer material layer to separate the spacer material layer into independent spacer patterns 400, and each of the spacer patterns 400 includes the insulating material layer 400b and the buffer material layer 400 a.

In this embodiment, the opening 510 is formed by etching the spacer material layer by using a dry etching process, when the insulating material layer 400b is etched, the insulating material layer 400b above the bit line structure BL is smaller in thickness and is preferentially etched, while the insulating material layer 400b above the first electrical transmission layer 300b is larger in thickness, and when the insulating material layer 400b above the bit line structure BL is etched, the insulating material layer 400b above the first electrical transmission layer 300b remains and needs to be etched continuously. Further, since the material of the buffer material layer 400a and the material of the insulating material layer 400b have a larger etching selection ratio (the etching rate of the insulating material layer 400b is greater than the etching rate of the buffer material layer 400 a), at this time, the buffer material layer 400a can be used as an anti-etching film layer to protect the bit line structure BL and prevent the bit line structure BL from being damaged; when the insulating material layer 400b on the first electrical transmission layer 300b is etched, the buffer material layer 400a can also protect the first electrical transmission layer 300b to prevent the first electrical transmission layer 300b from being damaged.

Finally, the etching gas is changed to etch and remove a portion of the buffer material layer 400a to form the opening 510. It can be understood that, in order to avoid adverse effects on the bit line structure BL when a portion of the buffer material layer 400a is removed by etching, the material of the buffer material layer 400a is different from the material of the bit line shielding layer 200d, and the material of the buffer material layer 400a and the material of the bit line shielding layer 200d have a larger etching selection ratio, so as to prevent the bit line structure BL from being damaged when the buffer material layer 400a is removed.

As an alternative embodiment, the spacer material layer in this embodiment may only include the insulating material layer 400b, so as to simplify the etching process, and at this time, there is no buffer of the buffer material layer, and the etching selection ratio of the materials of the insulating material layer 400b and the bit line shielding layer 200d is higher.

Referring to fig. 2b and fig. 2e, in the direction perpendicular to the depth direction, the position of the opening 510 is offset from the position of the node contact 500, that is, the center line of the opening 510 is not coincident with the center line of the node contact 500, but has a certain offset (in this embodiment, the opening 510 is offset to the right with respect to the node contact 500), and the planar shape of the opening 510 is honeycomb-shaped in the top view, so that the area can be saved and the device size can be reduced. As such, a portion of the opening 510 is located above the first electrical transmission layer 300b and a portion is located above the bit line structure BL, such that the opening 510 simultaneously exposes the first electrical transmission layer 300b and the top of the bit line structure BL.

With reference to fig. 2e and fig. 2f, step S400 is performed to sequentially form a conductive barrier layer 300d and a second electrical transmission layer 300c in the opening 510, wherein the conductive barrier layer 300d covers an inner wall of the opening 510, and the second electrical transmission layer 300c covers the conductive barrier layer 300d and fills the opening 510. The second electrical transmission layer 300c is electrically connected to the first electrical transmission layer 300b through the conductive barrier layer 300d, the electrically connected conductive contact layer 300a, the first electrical transmission layer 300b, the conductive barrier layer 300d and the second electrical transmission layer 300c form a node contact structure SC, and the adjacent node contact structures SC are electrically isolated by the spacing pattern 400. The process requirements for forming the second electrical transmission layer 300c are not critical due to the low height of the opening 510.

Further, the second electrical transmission layer 300c is a planarized film layer, and the top of the space pattern 400 is flush with the top of the second electrical transmission layer 300 c.

It is understood that, since the opening 510 also exposes the top of the bit line structure BL, the opening 510 widens laterally to the top of the bit line structure BL, and after the second electrical transmission layer 300c is formed in the opening 510, a portion of the second electrical transmission layer 300c covers the first electrical transmission layer 300b and is electrically connected to the first electrical transmission layer 300b, and another portion extends laterally to cover the bit line structure BL. In this way, the width of the top of the node contact structure SC is widened, and the area of the capacitor structure formed on the node contact structure SC subsequently can be increased, thereby improving the storage performance of the memory.

As an alternative embodiment, the opening 510 may only expose the top of the first electrical transmission layer 300b and not expose the top of the bit line structure BL, so that the second electrical transmission layer 300c only covers the top of the first electrical transmission layer 300b and does not extend to cover the top of the bit line structure BL, which is not described herein in detail.

It should be understood that, compared to the prior art in which the insulation pattern is formed on the bit line structure first and the bit line structure and the insulation pattern are used to define the node contact with a larger aspect ratio, in the embodiment, the bit line structure is directly used to define the node contact with a lower height first, so that the process requirement for forming the first electrical transmission layer 300b can be reduced; forming the spacing pattern 400 to increase the height of the bit line structure BL, so as to form the second electrical transmission layer 300c, and the height of the spacing pattern 400 is not very high, which can reduce the process requirement for forming the second electrical transmission layer 300 c; further, when the bit line structure BL is formed, the etching difficulty may also be reduced because only the stacked film layer of the bit line structure BL exists. Alternatively, it can be understood that, in the embodiment, the spacer pattern 400 is used to separate the conventional node contact window into an upper portion and a lower portion, the first electrical transmission layer 300b and the second electrical transmission layer 300c are filled in the node contact window step by step, and the first electrical transmission layer 300b and the second electrical transmission layer 300c are electrically connected to form the node contact structure SC, so that the performance of the memory is not affected, and the first electrical transmission layer 300b and the second electrical transmission layer 300c have low heights, which can reduce the requirement on the manufacturing process.

Optionally, referring to fig. 2g, after the memory in fig. 2f is formed, the method for forming the memory further includes a step of forming a capacitor structure. Specifically, an insulating layer 610 is formed on the space pattern 400, the insulating layer 610 covers the space pattern 400, and the insulating layer 610 is a patterned film layer. The insulating layer 610 and the bit line shielding layer 200d may be made of the same material, such as silicon nitride.

Then, a stacked material layer 620 is formed on the insulating layer 610, the stacked material layer 620 covers the insulating layer 610, and the stacked material layer 620 is a patterned film layer. Electrode grooves 630 are formed between adjacent stacked material layers 620, and the electrode grooves 630 are used for forming the cylindrical lower electrode of the capacitor structure in the subsequent step. The insulating layer 610 in this embodiment may serve as a mask layer for forming the stacked material layer 620. Fig. 2a is a simplified layout of the memory in fig. 2f, wherein fig. 2f is a schematic cross-sectional view of the memory in fig. 2a in the aa 'and bb' directions.

As shown in fig. 2a and 2f, the memory includes a substrate 100 and a word line structure WL formed in the substrate 100. The substrate 100 has a plurality of active areas AA extending along a first predetermined direction (Z direction) and trench isolation structures STI formed therein, the trench isolation structures STI separating adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.

Further, a word line trench is formed in the substrate 100, and the word line trench is used for accommodating the word line structure WL. Specifically, the word line trench extends along a second predetermined direction (X direction) to pass through the corresponding active area AA and the trench isolation structure STI, and the word line trench has a portion located in the trench isolation structure STI and a portion located in the active area AA.

In this embodiment, the size of the opening of the word line trench in the trench isolation structure STI is larger than the size of the opening of the word line trench in the active area AA. Further, the bottom position of the word line trench in the trench isolation structure STI is also lower than the bottom position of the word line trench in the active area AA.

As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, and thus the word line structure WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active area AA, and the top position of the word line structure WL is located at the same height position. The word line structure WL is formed in the word line trench, so a channel region buried in the active region AA to have a bent structure may be formed. Thus, the curved channel region can have a relatively large length as compared with the linear channel region, and short channel effects of the transistor can be improved.

With continued reference to fig. 2a and 2f, the word line structure WL includes a gate dielectric layer, a gate conductive layer and a gate insulating layer, wherein the gate dielectric layer covers an inner wall of the word line trench, the gate conductive layer is located on the gate dielectric layer and fills the word line trench with a partial depth, and the gate insulating layer is located on the gate conductive layer and fills a remaining depth of the word line trench.

Further, the active area AA is used to form a memory transistor, for example, a source/drain region may be further formed in the active area AA, where the source/drain region includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line structure WL to jointly form the memory transistor. It is to be understood that the bottom portions of the first and second source/drain regions are lower than the top portion of the gate conductive layer, so that there is an overlapping area between the first and second source/drain regions and the gate conductive layer.

With continued reference to fig. 2a and 2f, a plurality of bit line structures BL are formed on the substrate 100 and extend along a third predetermined direction (Y direction) to pass through the respective active areas AA. Referring to fig. 2f, the bit line structure BL includes a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c stacked in sequence. The material of the first bit line conductive layer 200a includes, for example, doped polysilicon, the material of the second bit line conductive layer 200b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

Further, the bit line structure BL may further include a bit line shielding layer 200d and a spacer 200 e. The bit line shielding layer 200d is formed above the bit line conductive layers stacked in sequence, and the spacer 200e at least covers the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line shielding layer 200 d.

The bit line structure BL has a portion located on the trench isolation structure STI and a portion located in the active area AA. That is, a portion of the bit line structure BL is located on the substrate 100 and directly above the trench isolation structure STI; another portion of the bit line structures BL extend from above the substrate 100 into the active area AA and are located between adjacent word line structures WL.

The bit line structure BL defines a node contact 500, and the node contact 500 is used for accommodating a node contact structure SC. Wherein, at least a portion of the bottom of the node contact 500 may further extend into the substrate 100. The defined node contact windows 500 are aligned in both the second predetermined direction and the third predetermined direction, and the node contact windows 500 are arranged in an array to form a node contact window array, for example. At this time, it can be considered that the plurality of node contact windows 500 are arranged in a plurality of rows in both the second predetermined direction and the third predetermined direction.

With continued reference to fig. 2b and 2f, the node contact structure SC includes a conductive contact layer 300a, and the conductive contact layer 300a fills a partial depth of the node contact window 500 to electrically connect with the active area AA.

Further, the node contact structure SC further includes a first electrical transmission layer 300b, a conductive barrier layer 300d and a second electrical transmission layer 300c, the first electrical transmission layer 300b fills a part of the depth of the node contact 500 and is formed on the conductive contact layer 300a to be electrically connected with the conductive contact layer 300a, the conductive barrier layer 300d is formed on the first electrical transmission layer 300b and covers the inner wall of the node contact 500 at the remaining depth, and the second electrical transmission layer 300c is formed on the conductive barrier layer 300d and fills the node contact 500 at the remaining depth and extends upward to be higher than the node contact 500.

The conductive barrier layer 300d serves to prevent diffusion of the material of the second electrical transmission layer 300c, thereby increasing the reliability of the memory. Alternatively, the conductive barrier layer 300d may be formed of a Ti/TiN stack structure.

Of course, other conductive film layers such as metal silicide may also be formed between the first electrical transmission layer 300b and the conductive barrier layer 300d, which is not illustrated herein.

In addition, in the direction perpendicular to the depth direction, the second electrical transmission layer 300c and the first electrical transmission layer 300b have an offset (right offset), so that the second electrical transmission layer 300c further extends to cover a portion of the top of the bit line structure BL, so that the width of the top of the second electrical transmission layer 300c is increased, thereby increasing the area of a capacitor structure formed on the second electrical transmission layer 300c in the following step.

With continued reference to fig. 2f, adjacent second electrical transport layers 300c are separated by a spacer pattern 400, wherein the spacer pattern 400 covers a portion of the top of the bit line structure BL and a portion of the top of the first electrical transport layer 300 b. That is, the spacer pattern 400 also fills the node contact 500 of the remaining depth and extends upward to be higher than the node contact 500, and the spacer pattern 400 also extends laterally to cover the top of the portion of the bit line structure BL.

Further, the sidewalls of the spacer pattern 400 contact the adjacent second electrical transmission layer 300c, and the spacer pattern 400 also electrically isolates the adjacent second electrical transmission layer 300c, thereby electrically isolating the adjacent node contact structures SC. As can be seen from fig. 2f, the spacing patterns 400 are spaced apart from the second electrical transmission layer 300c and are L-shaped, and the spacing patterns 400 are flush with the top of the second electrical transmission layer 300 c.

With continued reference to fig. 2f, the spacing pattern 400 includes a stack of a layer of buffer material 400a and a layer of insulating material 400b, the layer of insulating material 400b overlying the layer of buffer material 400 a. In this embodiment, the insulating material layer 400b and the buffer material layer 400a are both made of insulating materials, and the insulating material layer 400b and the buffer material layer 400a have a larger etching selection ratio, and the buffer material layer 400a and the bit line shielding layer 200d have a larger etching selection ratio, so that the buffer material layer 400a can protect the first electrical transmission layer 300b and the bit line shielding layer 200d from being excessively etched in the etching process, thereby better protecting the bit line structure BL and preventing the bit line structure BL from being damaged.

In this embodiment, the material of the buffer material layer 400a is silicon oxide, the material of the insulating material layer 400b is silicon nitride, and the material of the bit line shielding layer 200d may be another insulating material different from silicon oxide and silicon nitride, but not limited thereto.

As an alternative embodiment, the spacing pattern 400 may also only include the insulating material layer 400b, and the embodiment is not limited thereto.

Example two

Fig. 3a and fig. 3b are schematic structural diagrams corresponding to respective steps of the method for forming a memory provided in this embodiment. As shown in fig. 3a and 3b, the difference from the first embodiment is that in the present embodiment, when the opening 510 is formed, the position of the opening 510 corresponds to the position of the node contact in the depth direction, so that the planar shape of the opening 510 is checkered in a plan view.

With reference to fig. 3a, the center line of the opening 510 and the center line of the node contact are overlapped within an error tolerance range, such that the opening 510 only exposes the top portion of the first electrical transmission layer 300 b. After forming the second electrical transmission layer 300c in the opening 510, the second electrical transmission layer 300c fills the node contact 500 with the remaining depth and extends upward, and the second electrical transmission layer 300c is confined between the adjacent bit line structures BL.

As shown in fig. 3b, compared to the first embodiment, the first electrical transmission layer 300b and the second electrical transmission layer 300c of the memory formed by the method for forming a memory provided in the present embodiment correspond to each other in position in the depth direction. That is, the second electrical transmission layer 300c entirely covers the top of the first electrical transmission layer 300b and does not extend to cover the top of the bit line structure BL, and the spacer pattern 400 entirely covers the top of the bit line structure BL and does not extend to cover the top of the electrical transmission layer 300 c. Compared to the first embodiment, in the present embodiment, the material of the spacer pattern 400 and the bit line shielding layer 200d need not be considered, and the material of the spacer pattern 400 is selected in a wider range.

Further, as shown in fig. 3b, in the present embodiment, when the opening 510 is formed by etching, the buffer material layer 400a on the sidewall of the node contact 500 is not removed, so that the buffer material layer 400a of the memory extends downward from the top of the bit line shielding layer 200d to cover a portion of the sidewall of the bit line structure BL and stays above the first electrical transmission layer 300 b. In this way, the lateral width of the second electrical transmission layer 300c is slightly smaller than the lateral width of the first electrical transmission layer 300b, but the implementation of the present invention is not affected.

As an alternative embodiment, when the opening 510 is formed by etching, the buffer material layer 400a on the sidewall of the node contact window 500 may also be completely removed, so that the buffer material layer 400a of the memory is only located on the top of the bit line structure BL. In this way, the lateral width of the second electrical transmission layer 300c is equal to the lateral width of the first electrical transmission layer 300b, which is not limited by the present invention.

EXAMPLE III

Fig. 4a to 4d are schematic structural diagrams corresponding to corresponding steps of the method for forming a memory according to this embodiment. As shown in fig. 4a to 4d, the difference between the first embodiment and the second embodiment is that in the present embodiment, the material of the buffer material layer 400a is a conductive material, so as to increase the etching selectivity between the buffer material layer 400a and the bit line shielding layer 200d, thereby better protecting the bit line structure BL.

Specifically, referring to fig. 4a, when the opening 510 is formed, the position of the opening 510 corresponds to the position of the node contact. At this time, when the opening 510 is formed by etching, the buffer material layer 400a on the sidewall of the node contact 500 is completely removed, and before the second electrical transmission layer 300c is formed, an insulating sidewall 400c is formed on the sidewall of the opening 510. The insulating sidewall 400c is made of an insulating medium, and the buffer material layer 400a can be electrically isolated from the first electrical transmission layer 300b and the second electrical transmission layer 300c by the insulating sidewall 400c, so as to prevent the adjacent node contact structure SC from being short-circuited.

As shown in fig. 4b, compared to the second embodiment, in the memory formed by the memory forming method of the present embodiment, the buffer material layer 400a and the insulating material layer are sequentially stacked on the bit line structure BL, the insulating sidewall 400c is formed on the sidewall of the opening 510, and the buffer material layer 400a is electrically isolated from the first electrical transmission layer 300b and the buffer material layer 400a is electrically isolated from the second electrical transmission layer 300c by the insulating sidewall 400c, so as to prevent the adjacent node contact structures SC from being shorted.

It should be understood that, when the opening 510 is formed by etching, the buffer material layer 400a on the sidewall of the node contact window 500 is not removed, so that the buffer material layer 400a of the memory extends from the top of the bit line shielding layer 200d down to the portion of the sidewall covering the bit line structure BL and stays above the first electrical transmission layer 300 b. In this way, before forming the insulating sidewall spacers 400c, a portion of the height of the first electrical transmission layer 300b needs to be removed, and when forming the buffer material layer 400a, the buffer material layer 400a needs to cover the sidewall of the opening 510 and be located between the buffer material layer 400a and the first electrical transmission layer 300b to completely electrically isolate the buffer material layer 400a from the first electrical transmission layer 300b and the buffer material layer 400a from the second electrical transmission layer 300 c.

Referring to fig. 4c, when the opening 510 is formed, the positions of the opening 510 and the node contact 500 are offset in a direction perpendicular to the depth direction. At this time, after the opening 510 is formed by etching, part of the top of the bit line shielding layer 200d and part of the top of the electrical transmission layer 300b are exposed, and then before the second electrical transmission layer 300c is formed, an insulating sidewall 400c is formed on the sidewall of the opening 510. The insulating sidewall 400c is made of an insulating medium, and the buffer material layer 400a can be electrically isolated from the first electrical transmission layer 300b and the second electrical transmission layer 300c by the insulating sidewall 400c, so as to prevent the adjacent node contact structure SC from being short-circuited.

As shown in fig. 4d, compared to the first embodiment, in the memory formed by the memory forming method provided in this embodiment, the buffer material layer 400a and the insulating material layer 400b are sequentially stacked on top of a portion of the bit line structure BL and on top of a portion of the first electrical transmission layer 300 b. The insulating side wall 400c is formed on the sidewall of the opening 510, and the insulating side wall 400c covers the sidewall of the opening 510. That is, the left sidewall of the opening 510 is a whole, the insulating sidewall 400c covers the entire left sidewall of the opening 510, the right sidewall of the opening 510 has a step, and the insulating sidewall 400c covers the step side of the right sidewall of the opening 510, but it should be understood that in practice, the buffer material layer 400a can be electrically isolated from the first electrical transmission layer 300b and the second electrical transmission layer 300d only by covering the sidewall of the insulating sidewall 400c with the insulating sidewall 400 c. The insulating spacers 400c electrically isolate the buffer material layer 400a from the first electrical transmission layer 300b and the buffer material layer 400a from the second electrical transmission layer 300c, thereby preventing the adjacent node contact structures SC from being shorted.

In this embodiment, the insulating sidewall 400c may be made of conductive materials such as silicon, germanium, undoped polysilicon, or doped polysilicon, so that the insulating sidewall 400c may have a larger etching selection ratio with the bit line shielding layer 200d and may also have a larger etching selection ratio with the first electrical transmission layer 300b (usually made of metal), so as to better protect the first electrical transmission layer 300b and the bit line structure BL in the etching step.

Example four

Fig. 5a and 5b are schematic structural diagrams corresponding to respective steps of the method for forming a memory provided in this embodiment. As shown in fig. 5b, the difference from the first, second and third embodiments is that in this embodiment, the first electrical transmission layer 300b completely fills the node contact 500.

With reference to fig. 5b, since the first electrical transmission layer 300b completely fills the node contact 500, the top of the first electrical transmission layer 300b is flush with the top of the bit line structure BL (the top of the bit line shielding layer 200 d), so that the bottom of the spacing pattern 400 and the bottom of the second electrical transmission layer 300c are flush with the top of the bit line structure BL. As can be seen in fig. 5b, the spacing pattern 400 and the first electrical transmission layer 300b are rectangular.

With reference to fig. 5a and 5b, in the process of forming the memory according to the present embodiment, the difference from the first embodiment, the second embodiment and the third embodiment is that when the node contact 500 is filled with the first electrical transmission layer 300b, the node contact 500 is directly filled with a conductive material (a planarization process may be performed subsequently), so that the formed first electrical transmission layer 300b completely fills the node contact 500, and at this time, the top of the first electrical transmission layer 300b is flush with the top of the bit line structure BL. Thus, after the first electrical transmission layer 300b is formed, the substrate surface is flat, which is beneficial to the formation of the second electrical transmission layer 300 c.

To sum up, the memory provided by the utility model defines a plurality of node contact windows directly by using the bit line structure, because the height of the node contact windows is lower and the depth-to-width ratio is smaller, when the first electrical transmission layer is formed in the node contact windows, the forming process requirement on the first electrical transmission layer is smaller; forming a first electrical transmission layer and then forming spacing patterns, wherein the adjacent spacing patterns are spaced by an opening, the opening at least exposes part of the top of the first electrical transmission layer, and a second electrical transmission layer is formed in the opening, because the height and the aspect ratio of the opening are lower at the moment, when the second electrical transmission layer is formed in the opening, the forming process requirement on the second electrical transmission layer is lower, and the second electrical transmission layer is electrically connected with the first electrical transmission layer to form a node contact structure, so that the adverse effect on a memory can not be caused in the step; the second electrical transmission layer can extend to cover the top of the part of the bit line structure, and the width of the top surface of the second electrical transmission layer is increased, so that the area of a capacitor structure formed on the second electrical transmission layer subsequently can be increased, and the storage performance of the memory is improved; the interval pattern comprises a buffer material layer and an insulating material layer covering the buffer material layer, and the buffer material layer can provide a buffer effect in an opening formed by etching, so that the first electric transmission layer and the bit line shielding layer are protected from being excessively etched; when the buffer material layer is made of a conductive material, the etching selection ratio of the buffer material layer to the bit line shielding layer can be increased, so that the bit line structure is better protected.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims

1. A memory, comprising:

a substrate;

2. The memory of claim 1, wherein the first electrically conductive layer completely fills the node contact, and wherein a bottom of the second electrically conductive layer is flush with a top of the bitline shielding layer.

3. The memory of claim 1 or 2, wherein the spacing pattern comprises a layer of insulating material.

4. The memory of claim 3, wherein the spacing pattern further comprises a layer of buffer material between the layer of insulating material and the first electrical transmission layer and between the layer of insulating material and the bitline shielding layer.

5. The memory of claim 4, wherein the material of the buffer material layer is a material having an etch selectivity ratio with respect to the bit line masking layer.

6. The memory of claim 5, wherein the material of the buffer material layer is a conductive material, and further comprising:

7. A memory, comprising:

a substrate;

8. The memory of claim 7, wherein the spacer pattern comprises a buffer material layer and an insulating material layer covering the buffer material layer, the buffer material layer being made of a conductive material having an etching selectivity with respect to the bit line shielding layer.

9. The memory of claim 8, wherein the material of the buffer material layer is a conductive material.

10. The memory of claim 8, wherein the buffer material layer further extends from the bit line shielding layer to the node contact in the remaining depth, and the insulating sidewall is further between the buffer material layer and the first electrical transmission layer.