CN211555887U - Memory device - Google Patents

Abstract

The utility model provides a memory forms a plurality of shielding patterns on the substrate, at least partial shielding pattern is located the structural word line slot that just extends to the filling residual depth of word line, shielding pattern can regard as shielding layer and protection on the substrate simultaneously the grid insulating layer of word line structure, compare in current memory, the utility model provides a memory can omit the step of getting rid of grid insulating layer, grid dielectric layer on the substrate and reforming shielding layer on the substrate again, and the preparation technology is simpler, has improved the efficiency of preparation to can not exert an influence to the performance of memory; and, the first air gap and the second air gap can reduce the parasitic capacitance between the conductive patterns, improve the performance of the memory.

Description

Memory device

Technical Field

The utility model relates to a semiconductor manufacturing technology field especially relates to a memory.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory has a plurality of word line structures and bit line structures, the word line structures are buried in a substrate, the bit line structures are formed on the substrate and are electrically connected with corresponding memory cells, the memory further comprises a storage capacitor, the storage capacitor is used for storing charges representing stored information, and the memory cells can be electrically connected with the storage capacitor through a node contact structure, so that the storage function of each memory cell is realized.

Fig. 1a to 1c are schematic structural diagrams formed by a conventional memory forming method. Referring to fig. 1a to 1c, a conventional memory forming method includes: as shown in fig. 1a, after a word line trench is formed in a substrate 100 ', a gate dielectric layer 201a ' is formed on the substrate 100 ', wherein the gate dielectric layer 201a ' covers the substrate 100 ' and extends to cover an inner wall of the word line trench; then filling a word line structure WL 'in the word line groove, wherein the top surface of the word line structure WL' is lower than the top surface of the word line groove; next, a gate insulating layer 201b 'is formed on the gate dielectric layer 201 a', and the gate insulating layer 201b 'covers the gate dielectric layer 201 a' and fills the word line trench. Then, as shown in fig. 1b, grinding is performed to remove the gate dielectric layer 201a ' and the gate insulating layer 201b ' on the substrate 100 '. Finally, as shown in fig. 1c, a shielding layer 200 'is formed on the substrate 100' again to perform the isolation function. The existing memory forming method has many steps and is relatively complex, and how to provide a memory with simple preparation process is a technical problem which needs to be solved urgently at present.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a memory, it is also fairly simple not to influence the preparation technology under the condition of performance.

In order to achieve the above object, the present invention provides a memory, including:

a substrate including a plurality of word line trenches extending along a first predetermined direction therein;

a plurality of word line structures located in the word line trenches and filling a portion of the deep word line trenches; and the number of the first and second groups,

and a plurality of shielding patterns located on the substrate, wherein at least part of the shielding patterns are located on the word line structures and extend to the word line grooves filled with the residual depth.

Optionally, a first air gap extending in the depth direction is formed in the at least part of the shielding pattern.

Optionally, the shielding pattern includes a first film layer, a second film layer and a third film layer, where the first film layer at least covers the sidewall of the word line trench with the remaining depth, and the second film layer and the third film layer are sequentially stacked to fill the word line trench with the remaining depth and extend to a position higher than the top of the word line trench.

Optionally, the second film layer fills the inner wall of the word line trench with the remaining depth, and the third film layer covers the opening of the word line trench, so that a gap between the lower surface of the third film layer and the upper surface of the second film layer forms the first air gap.

Optionally, the second film layer fills the word line trench with the remaining depth and extends to a position higher than the top of the word line trench, the third film layer covers the second film layer, and the first air gap is located in the second film layer in the word line trench with the remaining depth.

Optionally, in the depth direction, the thickness of the second film layer is greater than the thickness of the third film layer.

Optionally, the first film layer and the third film layer are made of silicon oxide, and the second film layer is made of silicon nitride.

Optionally, the method further includes:

and the isolation columns are positioned on the substrate and extend along a second preset direction, and each pattern in the at least partial shielding patterns is positioned between the isolation columns and the word line structure.

Optionally, a surface of each of the at least partial shielding patterns is recessed in a direction close to the substrate, so that a second air gap extending in a depth direction is provided between each pattern and the isolation pillar.

Optionally, the method further includes:

and the bit line structures extend along the second preset direction, the parts of the bit line structures, which are positioned on the substrate, form first bit line structures, the parts of the bit line structures, which extend from the substrate into the substrate, form second bit line structures, and the rest shielding patterns are positioned between each first bit line structure and the substrate.

Optionally, in a direction perpendicular to the depth direction, a width dimension of each pattern in the at least partial shielding pattern is larger than a width dimension of the word line trench.

The utility model provides a memory has following beneficial effect:

1) compared with the prior memory, the memory provided by the utility model utilizes the shielding pattern to replace the shielding layer on the gate insulating layer, the gate dielectric layer and the substrate, thereby simplifying the forming process, improving the preparation efficiency and having no influence on the performance of the memory;

2) the first air gap and the second air gap are formed in the memory, so that the parasitic capacitance between the conductive patterns can be reduced, and the performance of the memory can be improved.

Drawings

FIGS. 1a to 1c are schematic structural diagrams formed by a conventional memory forming method;

fig. 2 is a flowchart of a method for forming a memory according to an embodiment of the present invention;

fig. 3a to fig. 4d are schematic structural diagrams formed by a method for forming a memory according to a first embodiment of the present invention;

fig. 4e is a schematic partial structural diagram of a memory according to a first embodiment of the present invention;

FIG. 4f is an enlarged view of a portion of FIG. 4 e;

fig. 4g is a simplified layout of a memory according to a first embodiment of the present invention, wherein fig. 3a to 4e are schematic cross-sectional views of the semiconductor structure in fig. 4g along a-a 'and/or b-b';

fig. 5a is a schematic structural diagram of a memory in a forming process according to a second embodiment of the present invention;

fig. 5b is a schematic partial structural diagram of a memory according to a second embodiment of the present invention;

FIG. 5c is an enlarged view of a portion of FIG. 5 b;

fig. 6a is a schematic structural diagram of a memory in a third embodiment of the present invention in a forming process;

fig. 6b is a schematic partial structural diagram of a memory according to a third embodiment of the present invention;

FIG. 6c is an enlarged view of a portion of FIG. 6 b;

wherein the reference numerals are:

100' -a substrate; WL' -word line structure; 201 a' -a gate dielectric layer; 201 b' -a gate insulating layer; 200' -a shielding layer;

100-a substrate; AA-active region; SIT-trench isolation structure; 300-an isolation column; 500-a layer of isolating material; 510-an isolation layer; 600-node contact window; 800-a patterned mask layer; 900-spacer insulating layer;

a WL-word line structure; a BL-bit line structure; BL1 — first bitline structure; BL2 — second bit line structure; tr-bit line trenches; 400 a-a first bit line conductive layer; 400 b-a second bit line conductive layer; 400 c-a third bitline conductive layer; 400 d-bit line masking layer; 400 e-isolation side wall;

200-a shielding layer; 200 a-a first material layer; 200 b-a second material layer; 200 c-a third material layer;

201-a first shielding pattern; 202-a second shielding pattern; 201a, 202 a-first film layer; 201b, 202 b-second film layer; 201c, 202 c-third film layer;

an SC-node contact structure; 700 a-a first layer of conductive material; 700 b-a second layer of conductive material; 700 c-a conductive contact layer;

g1 — first air gap;

g2 — second air gap;

d1 — opening size of upper trench located in active area;

d2 — opening size of upper trench located in trench isolation structure;

h1 — first depth position;

h2 — second depth position;

h3-third depth position.

Detailed Description

The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

Fig. 4e is a schematic diagram of a partial structure of the memory in this embodiment, fig. 4f is an enlarged view of a partial structure of the memory in fig. 4e, fig. 4g is a simplified layout of the memory in fig. 4e, wherein fig. 4e is a schematic cross-sectional diagram of the memory in fig. 4g in the directions of a-a 'and b-b'. As shown in fig. 4 e-4 g, the memory includes: a substrate 100 and a word line structure WL formed within the substrate 100.

Wherein a plurality of active areas AA extending in a third predetermined direction (Z-direction) and trench isolation structures STI are formed in the substrate 100, the trench isolation structures STI separating adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.

Further, a word line trench is formed in the substrate 100, and the word line trench is used for accommodating the word line structure WL. Specifically, the word line trench extends along a first predetermined direction (X direction) to pass through the respective active area AA and the trench isolation structure STI, and the word line trench has a portion therein located in the trench isolation structure STI and a portion therein located in the active area AA.

In this embodiment, the size of the opening of the word line trench in the trench isolation structure STI is larger than the size of the opening of the word line trench in the active area AA. Further, the bottom position of the word line trench in the trench isolation structure STI is also lower than the bottom position of the word line trench in the active area AA. Referring to fig. 4e, the bottom of the word line trench in the trench isolation structure STI is located at a first depth position H1 in the substrate 100, the bottom of the word line trench in the active area AA is located at a second depth position H2 in the substrate 100, and the first depth position H1 is lower than the second depth position H2.

As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, and thus the word line structure WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active area AA, and the top position of the word line structure WL is located at the same height position. The word line structure WL is formed in the word line trench, so a channel region buried in the active region AA to have a bent structure may be formed. Thus, the curved channel region can have a relatively increased length compared to the linear channel region, and thus the short channel effect of the transistor can be improved.

With continued reference to fig. 4e, the word line structure WL is located in the word line trench and fills a partial depth of the word line trench, in particular, a top surface of the word line structure WL is located at a third depth position H3 in the substrate 100, the third depth position H3 being higher than the first depth position H1 and the second depth position H2 and lower than the surface of the substrate. If the word line trench is divided into an upper trench and a lower trench bounded by the third depth position H3, the word line structure WL is located in the lower trench.

Further, the active area AA is used to form a memory transistor, for example, a source drain area may also be formed in the active area AA, where the source drain area includes a first source/drain area and a second source/drain area, and the first source/drain area and the second source/drain area are respectively located at two sides of the word line structure WL to form the memory transistor together. It is understood that the bottom of the first and second source/drain regions is lower than the top of the word line structure WL, so that there is an overlapping area between the first and second source/drain regions and the word line structure WL.

With continuing reference to fig. 4e and fig. 4g, a plurality of bit line structures BL are formed on the substrate 100 and extend along the second predetermined direction (Y) to pass through the corresponding active areas AA, and with continuing reference to fig. 4e, the bit line structures BL include a first bit line conductive layer 400a, a second bit line conductive layer 400b and a third bit line conductive layer 400c stacked in sequence. The material of the first bit line conductive layer 400a includes, for example, doped polysilicon, the material of the second bit line conductive layer 400b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

Further, the bit line structure BL may further include a bit line shielding layer 400d and an isolation sidewall spacer 400 e. The bit line shielding layer 400d is formed above the bit line conductive layers stacked in sequence, and the isolation sidewall 400e at least covers the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line shielding layer 400 d.

The bit line structure BL has a portion located on the trench isolation structure STI and a portion located in the active area AA. For convenience of description, a portion of the bit line structure BL located on the trench isolation structure STI is referred to as a first bit line structure BL1, and a portion of the bit line structure BL located in the active area AA is referred to as a second bit line structure BL 2. The first bit line structure BL1 is located on the substrate 100 and directly above the trench isolation structure STI; the second bit line structure BL2 extends from the substrate 100 into the active area AA, and the second bit line structure BL2 is located between adjacent word line structures WL in the active area.

With continuing reference to fig. 4e and fig. 4g, a plurality of isolation pillars 300 are formed on the substrate 100 and extend along a second predetermined direction, and each of the isolation pillars 300 is located directly above the word line structure WL. The isolation pillar 300 and the bit line structure BL define a node contact for accommodating a node contact structure SC. Wherein the bottom of at least a portion of the node contact may further extend into the substrate 100. The plurality of defined node contact windows are aligned in a first preset direction and a second preset direction, and are arranged in an array form to form a node contact window array. At this time, it can be considered that the plurality of node contact windows are arranged in a plurality of rows in both the first predetermined direction and the second predetermined direction.

With continued reference to fig. 4e, the node contacts fill the node contact windows and are correspondingly arranged in a plurality of rows, and the node contact structures SC are electrically connected to the corresponding active regions.

Referring next to fig. 4e, the memory further includes an isolation layer 510, where the isolation layer 510 covers a top surface of the bit line structure BL, and in this embodiment, the isolation layer 510 covers the bit line shielding layer 400d of the bit line structure BL. As described above, the adjacent bit line structures BL are used to define node contact windows, and it is considered that the height of the node contact windows can be further increased by the isolation layer 510 above the bit line structures BL.

With continued reference to fig. 4f, the node contact structures SC fill the node contact windows, and in the present embodiment, the node contact structures SC may be correspondingly arranged in an array to form a node contact structure array. Further, the top position of each node contact structure SC is further higher than the top position of the node contact window.

With continued reference to fig. 4e, the node contact structure SC includes a conductive contact layer 700c, and the conductive contact layer 700c fills the node contact window to electrically connect with the active area AA. Further, the node contact structure SC further includes an electrically conductive layer filling the node contact window and formed on the conductive contact layer 700c to be electrically connected to the conductive contact layer 700 c. In this embodiment, the electrically conductive material layers include a first conductive material layer 700a and a second conductive material layer 700 b.

Referring to fig. 4e, a plurality of shielding patterns are formed on the substrate 100, a part of the shielding patterns is a first shielding pattern 201, and the remaining part is a second shielding pattern 202, and each of the first shielding pattern 201 and the second shielding pattern 202 includes three layers, i.e., a first layer 201a, a second layer 201b, a second layer 202b, and a third layer 201c, 202 c.

With continued reference to fig. 4e, the first shielding patterns 201 are located between the substrate 100 and the isolation pillars 300, and each of the first shielding patterns 201 is aligned with a position of one of the isolation pillars 300, such that the first shielding pattern 201 is located directly above the word line structure WL and the isolation pillar 300 is located directly above the word line structure WL. In this embodiment, the width of the isolation pillar 300 and the first shielding pattern 201 in the direction perpendicular to the depth direction are both greater than the width of the upper trench in the direction perpendicular to the depth direction, so that the first shielding pattern 201 also extends to cover a portion of the substrate 100 after filling the upper trench.

With continued reference to fig. 4e and 4f, in the first shielding pattern 201, the first film layers 201a and 202a cover a portion of the substrate and extend to cover the sidewall of the upper trench, a gate dielectric layer is formed between the lower trench and the word line structure WL, and the first film layer 201a and the gate dielectric layer are integrally formed. The second film 201b is located on the first film 201a and extends to cover the inner wall of the upper trench, so that a gap is formed between the second film 201b on the two sidewalls of the upper trench. The third film 201c is located on the second film 201b and covers the gap, thereby closing the word line trench. In this embodiment, the first film 201a, the second film 201b, and the third film 201c are stacked sequentially and then are higher than the top of the word line trench (naturally, higher than the top surface of the substrate 100).

In this embodiment, since the first shielding pattern 201 fills the upper trench and covers the word line structure WL, the first shielding pattern 201 may serve as a gate insulating layer of the word line structure WL, so as to protect the word line structure WL from external intrusion such as water vapor, and achieve an isolation effect. Therefore, the gate insulating layer for protecting the word line structure WL and the shielding layer on the substrate can be formed synchronously, and the forming process is simplified.

Referring to fig. 4e and 4f, since the third film 201c covers the gap, a first air gap G1 is formed after the gap is closed, and the first air gap G1 is located between the lower surface of the third film 201c and the upper surface of the second film 201b and is located in the upper trench. Two sides of the first air gap G1 are two node contact structures SC, so the first air gap G1 with low dielectric constant can reduce the parasitic capacitance between the adjacent node contact structures SC, and improve the performance of the memory.

With continued reference to fig. 4e and 4f, the portion of the third film 201c covering the gap is also recessed into the gap to form a recessed portion, so that the entire first shielding pattern 201 has a valley shape, and it is understood that the third film 201c is not recessed to fill the gap, but is in a state of covering the gap, so that the first air gap G1 is remained. The isolation pillar 300 is located on the third film layer 201c and closes the recess, so that a second air gap G2 is formed between the lower surface of the isolation pillar 300 and the upper surface of the third film layer 201c, and like the first air gap G1, the second air gap G2 may also reduce the parasitic capacitance between adjacent node contact structures SC, thereby further improving the performance of the memory.

As shown in fig. 4e, in the present embodiment, the thickness of the second film layer 201b is greater than the thickness of the third film layer 201c in the depth direction, the thicker second film layer 201b can reduce the width dimension of the formed gap in the direction perpendicular to the depth direction, and the thinner third film layer 201c is difficult to directly fill the gap, so that the first air gap G1 and the second air gap G1 are easily formed.

With reference to fig. 4e, in the present embodiment, the second shielding pattern 202 is located between each of the first bit line structures BL1 and the substrate 100, and a width dimension of the second shielding pattern 202 in a direction perpendicular to the depth direction is equal to a width dimension of the first bit line structure BL 1. Unlike the first shielding pattern 201, the first film layer 202a, the second film layer 202b and the third film layer 202c in the second shielding pattern 202 are sequentially stacked on the substrate 100 from bottom to top, thereby isolating the substrate 1 from the first bit line structure BL 1.

In this embodiment, the first shielding pattern 201 and the second shielding pattern 202 are formed simultaneously, so that the first film layers 201a and 202a are made of the same material, the second film layers 202a and 202b are made of the same material, and the third film layers 201c and 202c are made of the same material. Further, the first film layers 201a and 202a and the third film layers 201c and 202c are made of silicon oxide, and the second film layers 202a and 202b are made of silicon nitride, so that the first shielding pattern 201 and the second shielding pattern 202 form an ONO structure, thereby enhancing the effect of protecting the word line structure WL and isolating external interference.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 2 and fig. 3a to 4 g. Fig. 2 is a schematic flow chart of a method for forming a memory according to an embodiment of the present invention, and fig. 3a to 4g are schematic structural diagrams of a semiconductor structure formed in a manufacturing process of the memory according to an embodiment of the present invention.

As shown in fig. 2, the method for forming the memory includes:

step S100: providing a substrate, wherein the substrate comprises a plurality of word line grooves extending along a first preset direction;

step S200: forming a plurality of word line structures in the word line trenches, the word line structures filling a portion of the depth of the word line trenches; and the number of the first and second groups,

step S300: and forming a plurality of shielding patterns on the substrate, wherein at least part of the shielding patterns are positioned on the word line structures and extend to the word line grooves filled with the residual depth.

Specifically, referring to fig. 3a, step S100 is performed to provide a substrate 100, in which a trench isolation structure STI is formed in the substrate 100, and a plurality of active regions AA extending along a third predetermined direction are defined by the trench isolation structure SIT.

Referring next to fig. 3b, word line trenches Tr are formed in the substrate 100 and extend along a first predetermined direction, wherein the word line trenches Tr are used for forming word line structures in a subsequent step, and thus the word line trenches Tr correspondingly extend along a second predetermined direction and pass through the corresponding active areas AA and the trench isolation structures STI. Further, the opening dimension D1 of the word line trench Tr in the active area AA is smaller than the opening dimension D2 of the word line trench Tr in the trench isolation structure STI; referring to fig. 3b, the bottom of the word line trench Tr in the active area AA is lower than the bottom of the word line trench Tr in the trench isolation structure STI, and the bottom of the word line trench Tr in the trench isolation structure STI is located at a first depth position H1 in the substrate 100, the bottom of the word line trench Tr in the active area AA is located at a second depth position H2 in the substrate 100, and the first depth position H1 is lower than the second depth position H2.

It should be noted that although the figure of the present embodiment does not show the mask layer on the top surface of the substrate 100, it should be appreciated that during the etching of the substrate 100 to form the word line trench Tr, the mask layer is usually formed on the top surface of the substrate 100 to avoid etching the regions of the substrate that are not corresponding to the trenches.

Referring next to fig. 3c, a first material layer 200a is formed on the substrate 100, the first material layer 200a covers the substrate 100 and extends to cover an inner wall of the word line trench Tr, and the first material layer 200a may serve as a gate dielectric layer for isolating the word line structure and the active area AA.

Referring next to fig. 3d, step S200 is performed to form a word line structure WL in the word line trench Tr, wherein the word line structure WL is a conductive film, such as polysilicon or tungsten. The word line structure WL fills the partial-depth word line trench Tr, and in this embodiment, the word line structure WL is located at a third depth position H3 in the substrate 100, and the third depth position H3 is higher than the first depth position H1 and the second depth position H2. Specifically, for example, the height of the word line structure WL in the word line trench Tr may be reduced by an etch-back process, so that the top surface of the word line structure WL is lower than the upper surface of the substrate 100. As a result, the portion of the word line trench Tr below the third depth position H3 is filled with the word line structure WL, and the portion above the third depth position H3 remains empty.

Next, for convenience of description, a portion of the word line trench Tr above the third depth position H3 is referred to as an upper trench, and a portion of the word line trench Tr below the third depth position H3 is referred to as a lower trench.

Referring next to fig. 3e, a second material layer 200b is formed on the first material layer 200a, and the second material layer 200b covers the first material layer 200a and extends to cover the inner wall of the upper trench, thereby resulting in a gap in the first material layer 200a between two sidewalls in the upper trench. Alternatively, it can be understood that the first material layer 200a between the two sidewalls of the upper trench is not attached, so that a gap is formed, and at this time, the opening of the upper trench is not closed.

With continued reference to fig. 3e, a third material layer 200c is formed on the second material layer 200b, and when the third material layer 200c is formed, due to the small size of the gap and the limitation of the deposition process, the third material layer 200c cannot fill the gap, so that the third material layer 200c covers the second material layer 200b above the substrate 100 and covers the gap, thereby closing the upper trench. The remaining gap between the upper surface of the second material layer 200b and the lower surface of the third material layer 200c forms a first air gap G1, and the first air gap G1 with a low dielectric constant can reduce the parasitic capacitance between adjacent conductive patterns, which will be described in detail later.

Further, when the third material layer 200c is formed, since there is no support at the gap, the formed third material layer 200c may be recessed into the gap, so that a portion of the third material layer 200c above the word line structure WL has a recessed portion. In this embodiment, the thickness of the second material layer 200b in the depth direction is greater than the thickness of the third material layer 200c in the depth direction, so that the width of the gap between the second material layers 200b covering the two sidewalls of the upper trench in the direction perpendicular to the depth direction is smaller, thereby ensuring that the formed third material layer 200c can cover the gap, but not limited thereto.

The lateral wall of slot and the part of cover substrate, second material layer 200b and third material layer 200c constitute and cover layer 200 in first material layer 200a, cover in the first material layer 200a the part of the lateral wall of slot is as the gate dielectric layer down, cover layer 200 and regard as the gate insulation layer in order to protect word line structure WL is not influenced by external steam or disturbance, compare in the process of forming the shielding layer in the background art, the utility model discloses can omit the step of getting rid of gate insulation layer, gate dielectric layer on the substrate and forming the shielding layer again on the substrate to the preparation technology of memory has been simplified, has improved the efficiency of preparation, and can not exert an influence to the performance of memory.

As an alternative embodiment, the first material Layer 200a, the second material Layer 200b and the third material Layer 200c may be formed by a Deposition process, and particularly may be formed by an Atomic Layer Deposition (ALD) process. Specifically, first, a deposition process (e.g., an atomic layer deposition process, etc.) is performed to deposit a dielectric material at a corresponding position; next, a thermal oxidation process (e.g., an in-situ steam oxidation method ISSG, etc.) is performed, thus improving the densification of the dielectric material.

It should be noted that, by performing a thermal oxidation process (for example, ISSG), in the trench isolation structure STI, not only the compactness of the deposited dielectric material can be improved, but also the compactness of the insulating material of the trench isolation structure STI itself can be further improved, and the internal stress of the trench isolation structure STI can be relieved, so that the isolation performance of the trench isolation structure STI can be improved, and the leakage current phenomenon can be improved. And in the active area AA, the compactness of the dielectric material in the active area AA can be improved through the thermal oxidation process, and the dielectric constant of the dielectric material is improved.

When the first material layer 200a, the second material layer 200b, and the third material layer 200c are prepared by deposition, the first material layer 200a and the third material layer 200c may be made of silicon oxide, and the second material layer 200b may be made of silicon nitride, so that the shielding layer 200 is an ONO (oxide-nitride-oxide) structure, and has better effects of isolating and protecting the word line structure WL.

Further, the method for forming the memory further comprises the following steps: forming a source drain region in the substrate 100, wherein a side edge boundary of the source drain region extends to a side wall of the word line trench close to the top opening, and a bottom boundary of the source drain region is lower than a top position of the word line structure WL, so that the source drain region and the word line structure WL have mutually opposite overlapping regions, and in the overlapping regions, the word line structure WL and the source drain region are mutually separated by using the first material layer 200 a.

Specifically, the source and drain regions include a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line structure WL. In this embodiment, the side edge boundary of the first source/drain region further extends to the sidewall of the trench isolation structure STI.

It should be noted that, in this embodiment, after the word line trench is formed and the word line structure WL is formed, the source and drain regions are prepared. However, in other embodiments, the source and drain regions may be formed first, and then the word line trench and the word line structure WL are sequentially prepared, which is not limited herein.

Referring to fig. 4a, step S300 is performed to form a plurality of isolation pillars 300 and a plurality of bit line structures BL on the substrate 100, wherein the isolation pillars 300 and the bit line structures BL extend along a second predetermined direction, a plurality of node contacts are defined on the substrate 100 by the isolation pillars 300 and the bit line structures BL, and the node contacts are aligned in a plurality of rows in the first predetermined direction and the second predetermined direction.

Further, the isolation pillar 300 is located on the word line structure WL so as to cover the recess in the third material layer 200c in the shielding layer, so that the recess and the lower surface of the isolation pillar 300 form a second air gap G2, and the second air gap G2 with a low dielectric constant can reduce the parasitic capacitance between adjacent conductive patterns, which will be described in detail later.

Specifically, when the bit line structure BL is formed, the bit line trench needs to be formed first, and since the bit line trench forms the bit line structure in a subsequent step, the bit line trench needs to extend along the second predetermined direction. A part of the bit line trench extends into the active region of the substrate 100 and is located between two word line structures WL in the active region, and another part is located above the shallow trench isolation structure STI. Specifically, a portion of the bit line trench above the shallow trench isolation STI is referred to as a first bit line trench, and a portion of the bit line trench extending into the active region of the substrate 100 and located between adjacent word line structures WL in the active region is referred to as a second bit line trench. It is understood that the second bit line trench is formed by etching the masking layer 200 and a partial depth of the active region in sequence from top to bottom.

A bit line structure BL is then formed in the bit line trench. The bit line structure BL comprises three layers of conductive material layers which are sequentially stacked. Based on this, the formed bit line structure BL includes the first bit line conductive layer 400a, the second bit line conductive layer 400b, and the third bit line conductive layer 400 c. Further, the bit line structure BL further includes a bit line shielding layer 400d, and the bit line shielding layer 400d may be a patterned film layer and is formed above the three conductive material layers. Alternatively, for example, the patterned bit line shielding layer 400d is used to sequentially perform a patterning process on the underlying conductive material layer. In this embodiment, the method for forming the bit line structure BL further includes: isolation spacers 400e are formed on the sidewalls of the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c, and the bit line shielding layer 400 d.

Next, for convenience of description, the bit line structure formed in the first bit line trench is referred to as a first bit line structure BL1, the bit line structure formed in the second bit line trench is referred to as a second bit line structure BL2, the first bit line structure BL1 is located on the substrate 100, the second bit line structure BL2 extends into the substrate 100 through the shielding layer 200,

referring to fig. 4a, in the present embodiment, the top surfaces of the isolation pillars 300 are flush, and the top surfaces of the isolation pillars 300 are higher than the top surface of the bit line structure BL, so that an isolation material layer 500 is formed on the bit line structure BL, so that the bit line structure BL is flush with the top surfaces of the isolation pillars 300. The isolation material layer 500, the bit line structure BL and the isolation pillars 300 therebelow form a plurality of isolation lines, and the isolation lines define a node contact array. In a specific embodiment, the isolation material layer 500 and the underlying bit line structure BL form a first isolation line extending along the extending direction of the bit line, for example, along a second predetermined direction, and the isolation pillar 300 forms a second isolation line extending along the first predetermined direction, for example, to intersect with the first isolation line, thereby defining the node contact array.

Referring to fig. 4b, step S300 is performed, and further, after the node contact array is defined, the method further includes further etching the shielding layer 200 at the bottom of the node contact 600 and the substrate 100 with a partial depth, so that at least a portion of the bottom of the node contact 600 further extends into the active region of the substrate 100, and the subsequently formed node contact structure and the active region have a better electrical connection effect.

As shown in fig. 4b, after etching the bottom of the node contact 600, the shielding layer at the bottom of the first bit line structure BL1 and the bottom of the isolation pillar 300 is retained, and the shielding layer at the rest of the substrate 100 is removed, so that the shielding layer forms a plurality of shielding patterns, where the shielding pattern at the bottom of the isolation pillar 300 is the first shielding pattern 201, and the shielding pattern at the bottom of the first bit line structure BL1 is the second shielding pattern 202, it can be understood that the first shielding pattern 201 is located between the isolation pillar 300 and the substrate 100, and the second shielding pattern 201 is located between the first bit line structure BL1 and the substrate 100. In addition, the first masking pattern 201 and the second masking pattern 202 include a portion of the remaining first material layer covering the sidewall of the upper trench, which constitutes first film layers 201a and 202a, a remaining second material layer which constitutes second film layers 201b and 202b, and a remaining third material layer which constitutes third film layers 201c and 202 c.

Further, as can be seen from fig. 4b, the top surfaces of the first shielding pattern 201 and the second shielding pattern 202 are higher than the surface of the substrate 100, and the whole is valley-shaped. In addition, in this embodiment, the width dimension of the isolation pillar 300 in the direction perpendicular to the depth direction is greater than the width dimension of the word line trench, so that the width dimension of the first shielding pattern 201 in the direction perpendicular to the depth direction is also greater than the width dimension of the word line trench, or it can be understood that the first shielding pattern 201 laterally extends from the word line trench to a portion of the substrate 100, thereby improving the effect of protecting the word line structure WL.

Referring specifically to fig. 4 c-4 e, an electrically conductive material layer (in the present embodiment, the electrically conductive material layer includes a first conductive material layer 700a and a second conductive material layer 700b) is formed, which fills at least a portion of the node contact windows and also covers the top surface of the isolation material layer 500. Wherein the electrically conductive material layer is used for further forming an electrically conductive layer in the node contact structure.

Optionally, before forming the electrically conductive material layer, the method further includes: and forming a contact layer in the node contact window. That is, in the present embodiment, when the electrically conductive material layer is formed, the electrically conductive material layer is formed on the contact layer, and the contact layer and the electrically conductive material layer are used to constitute the node contact structure.

Referring specifically to fig. 4c, the method of forming the contact layer includes: the conductive contact layer 700c is filled in at least a portion of the node contact window 600. In this embodiment, the conductive contact layer 700c is filled in the node contact 600 to electrically connect with the active region exposed in the node contact 600.

With continued reference to fig. 4c and 4d, after the contact layer is formed, a layer of electrically conductive material is formed. In this embodiment, the method for forming the electrically conductive material layer may specifically include the following steps.

A first step, specifically referring to fig. 4c, is to form a first conductive material layer 700a, wherein the first conductive material layer 700a covers the sidewalls of the node contact window 600 and the top surface of the conductive contact layer 700 c.

A second step, shown with particular reference to fig. 4d, is to form a second conductive material layer 700b, said second conductive material layer 700b filling said node contact windows 600 and also covering the top surface of said isolation material layer 500. In this embodiment, the second conductive material layer 700b is a planarization film layer.

Referring to fig. 4d and 4e, the electrically conductive material layer is patterned to form a node contact structure array including a plurality of node contact structures SC.

In this embodiment, the electrically conductive layer of the node contact structure SC is further formed by patterning the electrically conductive material layer. Specifically, the electrically conductive material layer is patterned, wherein the method for patterning the electrically conductive material layer specifically includes the following steps.

Step one, specifically referring to fig. 4d, a patterned mask layer is formed on the electrically conductive material layer, in this embodiment, the patterned mask layer is formed on the second electrically conductive material layer 700 b. The patterned mask layer 800 is, for example, a patterned photoresist layer.

Specifically, the patterned mask layer 800 covers the node contact opening 600 and extends laterally over the bit line structure to define a pattern of electrically conductive layers in the node contact structure.

Step two, referring to fig. 4e specifically, the patterned mask layer 800 is used as a mask to etch the electrically conductive material layer, that is, the patterned mask layer is used as a mask to sequentially etch the second electrically conductive material layer 700b and the first electrically conductive material layer 700 a. In this way, the electrically conductive material layers corresponding to different node contact windows 600 are separated from each other, so as to form electrically conductive layers separated from each other, thereby further forming node contact structures SC separated from each other.

With continued reference to fig. 4d, in a further aspect, after etching the electrically conductive material layer to expose the isolation material layer 500, the method further includes: the isolation material layer 500 is etched to a predetermined depth to form an isolation layer 510. By further etching the isolation material layer 500 between adjacent electrically conductive layers, the conductive material between adjacent electrically conductive layers can be effectively removed to ensure the isolation between adjacent electrically conductive layers.

With continued reference to fig. 4e, further, after forming the node contact structure SC, forming a spacer insulating layer 900 is also included. The spacer insulating layer 900 is formed in a space above the isolation layer and fills a gap between two adjacent node contact structures SC.

In this embodiment, the forming method of the spacer insulating layer 900 includes, for example: firstly, depositing an insulating material layer, wherein the insulating material layer fills gaps between adjacent node contact structures SC and covers the isolation layer; then, an etch-back process is performed to remove the portion of the insulating material layer above the node contact structure SC.

Referring to fig. 4e and 4f, the conductive contact layer 700c in the node contact structure SC has a first gap G1 and a second gap G2 separated from each other, and the first gap G1 and the second gap G2 have low dielectric constants, so that the parasitic capacitance between adjacent node contact structures SC can be reduced.

Example two

Fig. 5a is a schematic structural diagram of the memory in the present embodiment in the forming process, fig. 5b is a schematic partial structural diagram of the memory in the present embodiment, and fig. 5c is a partial enlarged view of fig. 5 b. As shown in fig. 5a to 5c, the difference from the first embodiment is that, in the present embodiment, the second film 201b of the first shielding pattern 201 fills the upper trench and extends to a position higher than the top of the word line trench, the third film 201c covers the second film 201b, and the first air gap G1 is located in the second film 201b in the upper trench and extends in the depth direction.

With reference to fig. 5b and fig. 5c, the second film 201b is covered on the first film 201a, covers the first film 201a and extends to fill the upper trench, and the upper surface of the second film 201b is flush with and higher than the substrate 100. When the third film 201c is formed on the second film 201b, the upper surface of the third film 201c is also flush, so that the lower surface of the isolation pillar 300 is attached to the upper surface of the third film 201 c.

In this embodiment, the first air gap G1 is formed in the second film 201b by controlling the process parameters for preparing the second film 201 b. For example, the second film 201b is formed by a deposition process with a poor trench filling capability, or the deposition process for preparing the second film 201b is accelerated. As shown in fig. 5b, in this embodiment, the thickness of the second film layer 201b is greater than that of the third film layer 201c, the thicker second film layer 201b can better fill the upper trench, and the thinner third film layer 201c does not cause the too thick shielding pattern to increase the volume of the memory.

Of course, as an alternative embodiment, a recess may be formed on the upper surface of the third film layer 201c by etching from the upper surface of the third film layer 201c, so that a second air gap may also be formed between the isolation pillar 300 and the first shielding pattern 201.

Referring to fig. 5a, further, a method for forming the memory in the present embodiment may be the same as the method for forming the memory in the first embodiment. The only difference is that after the word line structure WL is formed in the lower trench of the word line trench, the second material layer 200b is formed so as to cover the first material layer 200a and fill the upper trench. And, the first air gap G1 is formed in the second material layer 200b by controlling the deposition manner or the process conditions of the second material layer 200 b.

Further, the upper surface of the second material layer 200b is higher than the top surface of the substrate 100, and the upper surface of the second material layer 200b may be polished to be flat by a polishing process, and when the third film 201c is formed on the third film 201c, the upper surface of the third film 201c is also flush.

EXAMPLE III

Fig. 6a is a schematic structural diagram of the memory in the present embodiment in the forming process, fig. 6b is a schematic partial structural diagram of the memory in the present embodiment, and fig. 6c is a partially enlarged view of fig. 6 b. As shown in fig. 6a to 6c, the difference from the first embodiment is that, in the present embodiment, the first shielding pattern 201 includes only the first film layer 201a and the second film layer 201b, and the second shielding pattern 202 includes only the first film layer 202a and the second film layer 202 b.

Specifically, referring to fig. 6b and 6c, the first film 201a covers the sidewalls of the upper trench, and the first film 201b fills the inner wall of the upper trench to form a gap between the first films 201b on the two sidewalls of the upper trench.

The isolation pillars 300 are positioned on the first shielding pattern 201 to cover the gaps such that the lower surfaces of the isolation pillars 300 and the gaps constitute a second air gap G2. Alternatively, it can be understood that the surface of the first film layer 201a in the first shielding pattern 201 is recessed in a direction close to the substrate 100 to form a recess, and the isolation pillars 300 cover the opening of the recess to form the second air gap G2.

Further, referring to fig. 6c, in the present embodiment, the bottom of the isolation pillar 300 extends into the recess. That is, a portion of the lower surface of the isolation pillar 300 covers the first film layer 201a, and the remaining portion extends into the recess, so that the lowest position of the lower surface of the isolation pillar 300 is higher than the highest position of the first film layer 201 a. It should be understood, however, that the lower surface of the standoff post 300 does not extend to fill the recess such that the second air gap G2 is preserved.

Of course, when the size of the opening of the recess is small, the bottom of the isolation pillar 300 does not necessarily extend into the recess, but may just cover the opening of the recess, which is not explained one by one here.

Referring to fig. 6a, further, a method for forming the memory in the present embodiment may be the same as the method for forming the memory in the first embodiment. The only difference is that after forming the word line structure WL in the lower trench of the word line trench, when forming the second material layer 200b such that the second material layer 200b covers the first material layer 200a and covers the inner wall of the upper trench, and then forming no third material layer on the second material layer 200b, the first material layer 200a and the second material layer 200b may constitute the shielding layer 200.

Since the second material layer 200b covers only the inner wall of the upper trench, there is a gap between the second material layer 200b on both sidewalls of the upper trench, or it can be understood that the surface of the second material layer 200b is recessed to form a recess in the upper trench.

Referring to fig. 6a and 6b, in this embodiment, since the third material layer is not formed, in order to ensure the isolation performance, the thickness of the second material layer 200b may be increased, for example, and without limitation, to the sum of the thicknesses of the second material layer and the third material layer in the first embodiment.

Further, when the opening size of the recess is large, the material of the isolation pillar is accumulated in the recess when forming the isolation pillar 300, so that the lower surface of the isolation pillar 300 extends into the recess but does not fill the recess, and the dimension of the second air gap G2 formed at this time in the depth direction is small. Of course, when the opening size of the recess is small, the lower surface of the separation column 300 covers only the recess, and the size of the second air gap G2 formed at this time in the depth direction is large.

It should be understood that since only the first and second material layers 200a and 200b are formed, after the formation of the masking patterns, the second masking pattern 202 of the masking patterns also includes only the first and second film layers 202a and 202 b.

Compared with the first embodiment, the forming step of the third material layer is omitted, the process is further simplified, and the preparation efficiency is improved; meanwhile, a second air gap can be formed to reduce the parasitic capacitance between the node contact structures, and the performance of the memory is not influenced too much.

In summary, in the memory provided by the utility model, form a plurality of shielding patterns on the substrate, at least some shielding patterns are located the structural word line slot that just extends to the filling residual depth of word line, shielding pattern can be regarded as shielding layer and protection on the substrate simultaneously the grid insulating layer of word line structure, compare in current memory, the utility model discloses a step of removing grid insulating layer, grid dielectric layer on the substrate and reforming shielding layer on the substrate can be omitted when the memory is prepared, and preparation process is simpler, has improved the efficiency of preparation to can not exert an influence to the performance of memory; and the first air gap and the second air gap in the memory can reduce the parasitic capacitance between the conductive patterns and improve the performance of the memory.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims (11)

1. A memory, comprising:

a substrate including a plurality of word line trenches extending along a first predetermined direction therein;

a plurality of word line structures located in the word line trenches and filling a portion of the deep word line trenches; and the number of the first and second groups,

and a plurality of shielding patterns located on the substrate, wherein at least part of the shielding patterns are located on the word line structures and extend to the word line grooves filled with the residual depth.

2. The memory of claim 1, wherein the at least partial shielding pattern has a first air gap formed therein that extends in a depth direction.

3. The memory of claim 2, wherein the shielding pattern comprises a first layer, a second layer and a third layer, wherein the first layer covers at least sidewalls of the word line trench of the remaining depth, and the second layer and the third layer are sequentially stacked to fill the word line trench of the remaining depth and extend above a top of the word line trench.

4. The memory of claim 3, wherein the second layer fills an inner wall of the word line trench with a remaining depth, and the third layer covers an opening of the word line trench such that a gap between a lower surface of the third layer and an upper surface of the second layer forms the first air gap.

5. The memory of claim 3, wherein the second layer fills a remaining depth of the word line trench and extends above a top of the word line trench, the third layer overlies the second layer, and the first air gap is in the second layer in the remaining depth of the word line trench.

6. The memory of claim 4 or 5, wherein the thickness of the second film layer is greater than the thickness of the third film layer in a depth direction.

7. The memory of claim 3, wherein the first layer and the third layer are both comprised of silicon oxide, and the second layer is comprised of silicon nitride.

8. The memory of any one of claims 1-5, further comprising:

and the isolation columns are positioned on the substrate and extend along a second preset direction, and each pattern in the at least partial shielding patterns is positioned between the isolation columns and the word line structure.

9. The memory of claim 8, wherein a surface of each of the at least partially shielding patterns is recessed in a direction close to the substrate to have a second air gap extending in a depth direction between each pattern and the isolation pillars.

10. The memory of claim 8, further comprising:

and the bit line structures extend along the second preset direction, the parts of the bit line structures, which are positioned on the substrate, form first bit line structures, the parts of the bit line structures, which extend from the substrate into the substrate, form second bit line structures, and the rest shielding patterns are positioned between each first bit line structure and the substrate.

11. The memory of claim 1, wherein a width dimension of each of the at least partial masking patterns is greater than a width dimension of the word line trench in a direction perpendicular to a depth direction.

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