CN212010971U

CN212010971U - Semiconductor memory device with a plurality of memory cells

Info

Publication number: CN212010971U
Application number: CN202021070914.2U
Authority: CN
Inventors: 张钦福; 林昭维; 朱家仪; 冯立伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-06-11
Filing date: 2020-06-11
Publication date: 2020-11-24
Anticipated expiration: 2030-06-11

Abstract

The utility model discloses a semiconductor storage device, which comprises a substrate; a plurality of active regions; and a plurality of bit lines. Each active region is located on the substrate. The bit lines are arranged on the substrate in parallel along a first direction at intervals, the bit lines cross the active region, each bit line has a first end and a second end which are opposite, and the first ends and the second ends of the bit lines are arranged in a staggered mode and have different lengths respectively. The bit line structure of the semiconductor memory device can improve the manufacturing process space of the subsequent plug formation, thereby improving the contact resistance of the plug.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The utility model relates to a semiconductor field especially relates to a semiconductor storage device.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it has gradually replaced the DRAM cell with a planar gate structure under the current trend of mainstream development because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure.

Generally, a DRAM cell with a recessed gate structure includes a transistor device and a charge storage device for receiving voltage signals from bit lines and word lines. However, due to the limitations of the process technology, the conventional DRAM cell with the recessed gate structure still has many defects, and further improvements and improvements are needed to effectively improve the performance and reliability of the related memory device.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor memory device, which forms a plurality of bit lines by self-aligned double patterning (SADP) and bit line trimming mask. Therefore, the lengths of the bit lines are different, and the pitches of the two ends are correspondingly different, so that the bit line structure of the semiconductor memory device can improve the manufacturing process space (process window) of the subsequent plug formation, and improve the contact resistance (Rc) of the plug.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate, a plurality of active regions, and a plurality of bit lines. A plurality of active regions are defined on the substrate. The plurality of bit lines are arranged on the substrate in parallel and spaced along a first direction at intervals, the bit lines cross the active region, each bit line has a first end and a second end opposite to each other, and the first ends and the second ends of the bit lines are arranged in a staggered mode and have different lengths respectively.

Drawings

Fig. 1 to 10 are schematic diagrams illustrating a method for forming a semiconductor memory device according to a preferred embodiment of the present invention; wherein the content of the first and second substances,

fig. 1 is a schematic top view of a semiconductor memory device according to the present invention;

3 FIG. 32 3 is 3 a 3 schematic 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 31 3; 3

FIG. 3 is a cross-sectional view of a semiconductor memory device after forming a plug trench according to the present invention;

fig. 4 is a schematic top view of the semiconductor memory device of the present invention after forming the axial body and the sidewall;

3 FIG. 3 5 3 is 3 a 3 schematic 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 34 3; 3

Fig. 6 is a schematic cross-sectional view of the semiconductor memory device after a patterning process;

fig. 7 is a schematic top view of the semiconductor memory device after forming bit lines according to the present invention;

3 FIG. 3 8 3 is 3 a 3 schematic 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3' 3 of 3 FIG. 3 7 3; 3

Fig. 9 is a schematic top view of the semiconductor memory device after forming a bit line trimming mask according to the present invention; and

fig. 10 is a schematic top view of the semiconductor memory device after the bit line trimming process.

Wherein the reference numerals are as follows:

100. a substrate; 101. an active region; 102. a storage area; 106. shallow trench isolation; 108. A trench; 110. a word line; 112. a dielectric layer; 113. a gate dielectric layer; 114. a gate electrode; 116. a first insulating layer; 124. a second insulating layer; 126. a sacrificial layer; 128. a mask layer; 129. an opening; 130. a plug trench; 150. a layer of material; 160. a bit line pattern; 160a, bit line contact plugs; 161. a first bit line; 163. a second bit line; 165. a third bit line; 200. patterning the sacrificial layer; 210. a spacer; 230. a mask layer; 231. a first recess; 232. a second recess; 233. a third recess; 234. a fourth recess; 236. and a fifth recess.

Detailed Description

To further clarify the present invention, those skilled in the art will be able to understand the present invention by referring to the following detailed description of several preferred embodiments of the present invention, and by referring to the accompanying drawings, the constituent elements of the present invention and intended functions will be described in detail.

3 fig. 31 3 to 3 10 3 are 3 schematic 3 views 3 illustrating 3 a 3 semiconductor 3 memory 3 device 3 and 3 a 3 forming 3 process 3 thereof 3 according 3 to 3 a 3 preferred 3 embodiment 3 of 3 the 3 present 3 invention 3, 3 wherein 3 fig. 31 3, 34 3, 3 7 3, 3 9 3 and 3 10 3 are 3 schematic 3 top 3 views 3 illustrating 3 a 3 semiconductor 3 memory 3 device 3 in 3 a 3 manufacturing 3 process 3, 3 and 3 the 3 other 3 figures 3 are 3 schematic 3 cross 3- 3 sectional 3 views 3 illustrating 3 the 3 semiconductor 3 memory 3 device 3 in 3 the 3 manufacturing 3 process 3, 3 wherein 3 fig. 32 3, 3 5 3 and 3 8 3 are 3 schematic 3 cross 3- 3 sectional 3 views 3 along 3 a 3 cut 3 line 3 a 3- 3 a 3' 3 in 3 fig. 31 3, 34 3 and 3 7 3, 3 respectively 3. 3

In the present embodiment, the semiconductor memory device includes a recessed gate random access memory (DRAM), which includes at least one transistor device (not shown) and at least one capacitor structure (not shown) as a minimum unit in a DRAM array and receives voltage signals from word lines 110 (WL) and Bit Lines (BL), such as first bit lines 161, second bit lines 163, and third bit lines 165. First, as shown in fig. 1 and fig. 2, the semiconductor memory device includes a memory region 102(memory cell region)102 and a peripheral region (not shown) surrounding the memory region 102, wherein for simplicity of description, the drawings only illustrate the memory region 102 and elements disposed therein, and the peripheral region is omitted. Specifically, the semiconductor memory device includes a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, etc., a plurality of active areas 101 (AA) 101 are formed on the substrate 100, and each of the active areas 101 extends in parallel along a first direction D1. A plurality of buried gates 114 are formed in the substrate 100 and can be used as a Buried Word Line (BWL) 110. The gates 114 extend parallel to each other along a second direction D2, and cross under the active regions 101 (in the first direction D1), as shown in fig. 1.

In one embodiment, the semiconductor memory device may be formed by the following steps, but is not limited thereto. First, as shown in fig. 2, at least one Shallow Trench Isolation (STI) 106 is formed in the substrate 100 to define each active region 101 shown in fig. 1 in the substrate 100. Next, a plurality of trenches 108 are formed in the substrate 100, each trench 108 is parallel to each other and extends toward the second direction D2, and a dielectric layer 112 covering the entire surface of each trench 108, a gate dielectric layer 113 filling the lower half of each trench 108, a buried gate 114, and a first insulating layer 116 filling the upper half of each trench 108 are sequentially formed in each trench 108, wherein the top surface of the first insulating layer 116 is aligned with the surface of the substrate 100, as shown in fig. 2, so that the gates 114 in each trench 108 are parallel to each other and extend toward the second direction D2, thereby forming the word line 110 shown in fig. 1. Then, a second insulating layer 124 is formed on the surface of the substrate 100, and the second insulating layer 124 includes, for example, an oxide-nitride-oxide (ONO) structure to cover the substrate 100 and the word lines 110 therein.

Subsequently, as shown in fig. 2 and 3, at least one plug trench 130 is formed on the surface of the substrate 100. The plug trench 130 may be formed by the following steps, but is not limited thereto. First, a mask structure is formed on the substrate 100, wherein the mask structure may have at least one opening 129 for defining the plug trench 130, and a portion of the second insulating layer 124 is exposed. In one embodiment, the mask structure may include a sacrificial layer 126 and a mask layer 128 stacked in sequence from bottom to top, as shown in fig. 2, wherein the sacrificial layer 126 is, for example, an organic dielectric layer, but not limited thereto. Then, an etching process is performed to remove the second insulating layer 124 exposed from the opening 129 and the portion of the substrate 100 thereunder by using the mask structure, so as to form a plug trench 130 in the substrate 100, and then the mask structure is completely removed, as shown in fig. 3. The plug trench 130 is located between two adjacent word lines 110 and exposes a portion of the substrate 100. In one embodiment, an ion implantation process, such as an anti-punch-through (anti-punch-through) ion implantation process, may be performed during the formation of the plug trench 130 to further form a doped region (not shown) in the substrate 100 exposed by the plug trench 130, so as to achieve the effect of avoiding current leakage.

As shown in fig. 4 to 8, a plurality of bit line patterns 160 are formed on the substrate 100. In the present embodiment, the bit line pattern 160 may be formed by a self-aligned double patterning (SADP) process, but is not limited thereto. In detail, a material layer 150 is formed on the substrate 100, the plug trench 130 is filled and further covered on the substrate 100, as shown in fig. 5, and then the self-aligned double patterning process is performed. In one embodiment, the material layer 150 may be a conductive material or a composite material, such as a semiconductor layer (not shown), a barrier layer, and a barrier layer (not shown), but not limited thereto. Next, as shown in fig. 4 and 5, a plurality of patterned sacrificial layers 200(mandrels) are formed on the material layer 150 through a photolithography process, wherein each patterned sacrificial layer is parallel to each other and extends toward a third direction D3, and then deposition and etch-back processes are sequentially performed to form a sidewall spacer 210 on a sidewall of each patterned sacrificial layer 200. Subsequently, as shown in fig. 6, the patterned sacrificial layer 200 is completely removed, and an etching process is performed through the coverage of the sidewall spacer 210 to transfer the pattern of the sidewall spacer 210 to the underlying material layer 150, so that the material layer 150 filling the plug trench 130 can form a Bit Line Contact (BLC) 160a, and the material layer 150 on the substrate 100 can form the bit line pattern 160. In other words, in the present embodiment, the bit line contact plug 160a is integrally formed with the bit line pattern 160, but not limited thereto.

Thereafter, the spacers are completely removed. As shown in fig. 7 and 8, a plurality of bit line patterns 160 are formed on the gate 114, and each bit line pattern 160 extends in parallel along a third direction D3 and simultaneously crosses the active region in the first direction D1 and the word line 110 in the second direction D2, and each bit line contact plug 160a is formed below the bit line pattern 160 and between two adjacent word lines 110. That is, the third direction D3 is different from the first direction D1 and the second direction D2, and the first direction is different from the second direction, preferably perpendicular to the second direction D2 and not perpendicular to the first direction D1. Thus, the bit line pattern 160 and the word line 110 are isolated from each other by the insulating layer, and may be further electrically connected to a source/drain region (not shown) of the at least one transistor device in the semiconductor memory device through the bit line contact plug 160 a.

Then, as shown in fig. 9 to 10, a bit line trim (bit line trim out) process is performed to form a plurality of bit lines, which are a first bit line 161, a second bit line 163, and a third bit line 165. First, a mask layer 230 is formed on the substrate to completely cover the memory region 102 of the semiconductor memory device. It is noted that the mask layer 230 serves as a bit line trimming mask, the mask layer 230 has a plurality of recesses, i.e., a first recess 231, a third recess 233, a second recess 232, and a fourth recess 234, on two opposite sides in the third direction D3, and the first recess 231, the third recess 233, the second recess 232, and the fourth recess 234 on the two opposite sides are alternately arranged to alternately expose two opposite ends of the bit line pattern 160. In other words, a portion of the bit line pattern 160 outside the memory region 102 may be exposed from the first recess 231, the third recess 233, the second recess 232, and the fourth recess 234 of the mask layer 230. In the present embodiment, the respective recesses, the first recess 231, the third recess 233, the second recess 232, and the fourth recess 234, may preferably have the same or different sizes (e.g., refer to depths in the third direction D3) in the third direction D3. For example, the

recesses

231 and 233 on the same side may have different depths W1 and W3, so that the exposed portions of the bit line pattern 160 have different lengths; alternatively, the second recess 232 and the fourth recess 234 on the same side may have the same depth W1, such that the exposed portions of the bit line patterns 160 have the same length; alternatively, the second recess 232, the fourth recess 234 and the fifth recess 236 located on the same side may have the same depth W1 and different depths W2 at the same time, as shown in fig. 9, but not limited thereto. It should be readily understood by those skilled in the art that the size of each of the above-mentioned recesses can be further adjusted according to the actual device requirements, for example, all the recesses can have the same size, or all the recesses on the same side can have the same size, and all the recesses on different sides can have different sizes. In addition, although the first recess 231, the third recess 233, the second recess 232, and the fourth recess 234 have the same shape (e.g. all rectangular shapes) in the present embodiment, but not limited thereto, in another embodiment, the shape of each recess may be further adjusted according to actual device requirements, for example, each recess has a different shape, such as a circular, oval, trapezoidal, triangular recess (not shown), or the recesses on two opposite sides have different shapes.

Then, as shown in fig. 9 to 10, an etching process is performed through the mask layer 230 to remove portions of the bit line pattern 160 exposed by the first recess 231, the third recess 233, the second recess 232, and the fourth recess 234, thereby forming a plurality of bit lines, i.e., a first bit line 161, a second bit line 163, and a third bit line 165. Thereafter, the mask layer 230 is completely removed. As shown in fig. 10, the first bit line 161, the second bit line 163 and the third bit line 165 are disposed in parallel and spaced along the third direction D3, and cross each active region 101 and the word line 110 therebelow. It is to be noted that after the above-mentioned bit line trimming process, the first bit line 161, the second bit line 163 and the third bit line 165 may have the same length L1, or the first bit line 161, the second bit line 163 and the third bit line 165 may have different lengths L1, L2 and L3. The opposite ends of the first bit line 161, the second bit line 163, and the third bit line 165 in the third direction D3 are not aligned with each other, but are arranged offset from each other. In detail, one end (e.g., left end) of the second bit line 163 is not aligned with the adjacent third bit line 165 and one end (e.g., left end) of the first bit line 161, but staggered; the other end (e.g., right end) of the second bit line 163 is also staggered with respect to the adjacent third bit line 165 and the first bit line 161 (e.g., right end), as shown in fig. 10. The distances of the opposite ends of the first bit line 161, the second bit line 163, and the third bit line 165 may be selected to be the same, for example, the left ends of two adjacent bit lines may be shifted from each other to the same extent as the right ends thereof are shifted from each other; alternatively, the two opposite ends of the first bit line 161, the second bit line 163 and the third bit line 165 may be mutually staggered by different distances, for example, the left ends of the adjacent second bit line 163 and the third bit line 165 are mutually staggered by a degree significantly different from the left ends of the adjacent second bit line 163 and the first bit line 161, as shown in fig. 10.

Thus, as shown in fig. 9-10, the portions of the first bit line 161, the second bit line 163, and the third bit line 165 at the two opposite ends may have a larger pitch (pitch) P1, for example, but not limited to, about 2 times the pitch P2 of the other portions of the first bit line 161, the second bit line 163, and the third bit line 165. In this case, a portion of the first bit line 161 and the second bit line 163 may not partially overlap the underlying word line 110, particularly the word line 110 located outside the memory region 102 (i.e., located in the peripheral region), in other words, the overlapping area between a portion of the first bit line 161, the second bit line 163 and the underlying word line 110 may be smaller than the third bit line 165. Thus, the two opposite ends of the first bit line 161, the second bit line 163 and the third bit line 165 may have a larger process window (process window) to facilitate the subsequent processes, such as forming a plug process electrically connecting the first bit line 161, the second bit line 163 and the third bit line 165. Specifically, the two opposite ends of the first bit line 161, the second bit line 163 and the third bit line 165 are alternately arranged, and plugs electrically connected to the first bit line 161, the second bit line 163 and the third bit line 165 may be alternately arranged at the two opposite ends of the first bit line 161, the second bit line 163 and the third bit line 165, for example, the plugs electrically connected to the first bit line 161, the second bit line 163 and the third bit line 165 may be sequentially arranged at the left end of the third bit line 165, the right end of the second bit line 163 and the left end of the first bit line 161, so that each plug may have a sufficient arrangement space to improve the contact resistance, but the arrangement is not limited thereto.

Thus, the method of forming the semiconductor memory device according to the preferred embodiment of the present invention is completed. In the forming method of the present embodiment, a plurality of bit lines of the semiconductor memory device are formed by a self-aligned double patterning process and a bit line trimming mask (bit line trimming mask). In this case, the opposite ends of the bit lines are arranged to be shifted from each other, and the distances of the opposite ends of the bit lines may be selected to be the same or different from each other, so that the bit lines may have the same or different lengths. Therefore, the two opposite ends of each bit line can have a larger pitch, for example, about 2 times of the other portions, so as to have a larger fabrication process space. Therefore, the bit line structure of the semiconductor memory device, particularly the structure of the two opposite ends of the bit line, is advantageous for the subsequent manufacturing process, such as the formation of plugs electrically connecting the bit lines, so that the semiconductor memory device as a whole can have a preferable device performance.

The semiconductor memory device of the present application may be formed by the above method, and the position, connection relationship and/or material of each structure or component in the semiconductor memory device in the above method are all applicable to the semiconductor memory device, that is, the corresponding structure or component of the semiconductor memory device may have the same position, connection relationship and/or material.

In addition, in the above embodiments, although the bit line pattern is formed by the self-aligned double patterning process and then the bit line trimming mask is used to trim the bit line pattern to form the bit line, the formation method of the present invention is not limited to the above-mentioned manufacturing process sequence. In another embodiment, the above-mentioned bitline trimming process may be performed first, and the two opposite ends of a material layer are trimmed by a bitline trimming mask (not shown), and then a self-aligned double patterning process is performed to form a plurality of bitlines.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a plurality of active regions on the substrate; and

a plurality of bit lines spaced apart from each other in a first direction on the substrate in parallel, the bit lines crossing the active region, wherein each of the bit lines has a first end and a second end opposite to each other, and the first ends and the second ends of the bit lines are arranged in a staggered manner and have different lengths, respectively.

2. The semiconductor memory device according to claim 1, wherein a pitch between any adjacent two of the bit lines is smaller than a pitch between any adjacent two of the first terminals.

3. The semiconductor memory device according to claim 1, wherein a pitch between any adjacent two of the bit lines is smaller than a pitch between any adjacent two of the second terminals.

4. The semiconductor memory device according to claim 1, wherein the substrate includes a memory region and a peripheral region, and the bit line is located in the memory region.

5. The semiconductor storage device according to claim 1, further comprising:

the gate electrodes are arranged in the substrate and are arranged in parallel along a second direction, and the second direction is different from the first direction.

6. A semiconductor memory device, comprising:

a substrate;

a plurality of active regions on the substrate;

a plurality of word lines in the substrate, the word lines being arranged in parallel with each other along a second direction; and

a plurality of bit lines disposed in parallel with each other on the substrate at intervals along a first direction, the first direction being different from the second direction, the plurality of bit lines crossing the active region, wherein an overlapping area between a portion of the plurality of bit lines and the plurality of word lines is smaller than other bit lines of the plurality of bit lines.