CN216213456U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The utility model discloses a semiconductor memory device, which comprises a substrate, a plurality of bit lines and a plurality of insulating structures. The bit lines are disposed on the substrate and extend in a first direction, and the bit lines include a plurality of first bit lines and at least one second bit line disposed at one side of all the first bit lines. Insulating structures are disposed on the substrate, each insulating structure including a plurality of insulating end portions and a plurality of insulating fins extending in a second direction perpendicular to the first direction, wherein at least one of the insulating end portions is entirely within the second bit line. Therefore, the semiconductor memory device with better component reliability can be formed under the simplified manufacturing process, so that the efficiency of the semiconductor memory device is improved.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory device.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it has gradually replaced the DRAM cell with a planar gate structure due to the longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure.

Generally, a DRAM cell with a recessed gate structure includes a transistor element and a charge storage device to receive voltage signals from the bit line and the word line. However, due to the limitations of the process technology, the conventional DRAM cell with the recessed gate structure still has many drawbacks, and further improvements and improvements are needed to effectively improve the performance and reliability of the related memory device.

SUMMERY OF THE UTILITY MODEL

An objective of the present invention is to provide a semiconductor memory device and a method for forming the same, in which a plurality of insulating structures are formed by a self-aligned double patterning process, and are partially embedded in a common bit line and a dummy bit line. Therefore, the insulating structures can be used for effectively isolating each plug, and a semiconductor memory device with better assembly reliability is formed under the simplified manufacturing process so as to improve the efficiency of the semiconductor memory device.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate, a plurality of bit lines, and a plurality of insulating structures. The bit lines are disposed on the substrate and extend in a first direction in parallel with each other, and include a plurality of first bit lines and at least one second bit line disposed at one side of all the first bit lines. The isolation structures are disposed on the substrate, each isolation structure comprising a plurality of isolation end portions and a plurality of isolation fins extending in a second direction, the second direction being perpendicular to the first direction, wherein at least one of the isolation end portions is entirely within the second bit line.

To achieve the above objective, one embodiment of the present invention provides a method for forming a semiconductor memory device, which includes the following steps. First, a substrate is provided, and a plurality of bit lines extending in a first direction are formed on the substrate. The bit lines include a plurality of first bit lines and at least one second bit line formed at one side of all the first bit lines. Next, a plurality of insulating structures are formed on the substrate, each of the insulating structures including a plurality of insulating end portions and a plurality of insulating fins extending in a second direction. The second direction is perpendicular to the first direction, wherein at least one of the insulated end portions is entirely within the second bit line.

Drawings

FIGS. 1 to 3 are schematic views of a semiconductor memory device according to a first embodiment of the present invention; wherein

FIG. 1 is a schematic top view of a semiconductor memory device according to the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1; and

fig. 3 is a schematic cross-sectional view taken along line B-B' of fig. 1.

FIG. 4 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor memory device according to a second embodiment of the present invention.

Wherein the reference numerals are as follows:

100 substrate

101 active region

103 shallow trench isolation

108 trenches

120 word line

111 dielectric layer

113 Gate dielectric layer

115 gate electrode

117 insulating layer

130 insulating layer

130a opening

140 insulating layer

150. 250 insulating structure

151. 251 insulating fin

151a, 151b, 151c fragment

153. 253 insulated end

153a, 153b, 153c insulating end

160 bit line

160a bit line contact

162 first bit line

161 semiconductor layer

163 barrier layer

164 second bit line

165 metal layer

167 a cap layer

170 side wall layer

100. 300 semiconductor memory device

Direction D1

D2 second direction

D3 first direction

L1 first length

L2 second length

L3 third Length

S1 first depth

S2 second depth

S3 third depth

W1 and W2 line widths

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below to explain the present invention and its intended effects.

Referring to fig. 1 to 3, a semiconductor memory device 300 according to a first embodiment of the present invention is shown, wherein fig. 1 is a top view of the semiconductor memory device 300, and fig. 2 and 3 are cross-sectional views of the semiconductor memory device 300. In the present embodiment, the semiconductor memory device 300 is, for example, a recessed gate random access memory (DRAM), which includes at least one transistor element (not shown) and at least one capacitor element (not shown) as a minimum unit in a DRAM array and receives voltage signals from a Word Line (WL) 120 and a Bit Line (BL) 160. The semiconductor memory device 300 includes a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and a plurality of Active Areas (AA) 101 are defined in the substrate 100, and extend in parallel and spaced apart from each other along a direction D1, so as to form an array arrangement as a whole, as shown in fig. 1. A plurality of buried gate structures are formed in the substrate 100, and extend in parallel along the second direction D2 and intersect with the active regions 101 to serve as Buried Word Lines (BWLs) 120, as shown in fig. 2 and 3.

In one embodiment, the active region 101 and the word line 120 can be formed by the following steps, but are not limited thereto. First, at least one Shallow Trench Isolation (STI) 103 is formed in the substrate 100 to define each active region 101 shown in fig. 1 in the substrate 100. Next, a plurality of trenches 108 are formed in the substrate 100, each trench 108 is parallel to each other and extends toward the second direction D2, and a dielectric layer 111 covering the entire surface of each trench 108, a gate dielectric layer 113 and a buried gate 115 filling the lower half of each trench 108, and an insulating layer 117 filling the upper half of each trench 108 are sequentially formed in each trench 108, as shown in fig. 2 and 3. Preferably, the word line 120 is formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, for example, but not limited to, defining the trench 108 by the self-aligned double patterning or the self-aligned reverse patterning process. Thus, the top surface of the insulating layer 117 is cut to be flush with the surface of the substrate 100, and the insulating layer 130 is covered on the surface of the substrate 100, so that the gate structure in each trench 108 extends in the second direction D2 as the word line 120. In one embodiment, the insulating layer 130 includes, for example, a silicon oxide-nitride-silicon oxide (ONO) structure, but not limited thereto.

A plurality of openings 130a are also formed in the substrate 100, wherein the openings 130a are located between two adjacent word lines 120 and expose a portion of the substrate 100, as shown in fig. 2 and 3. In one embodiment, the opening 130a can be formed by the following steps, but is not limited thereto. First, a mask structure (not shown) is formed on the substrate 100, the mask structure may have at least one pattern (not shown) for defining the opening 130a to expose a portion of the insulating layer 130, an etching process is performed using the mask structure to remove the insulating layer 130 exposed from the mask structure and the substrate 100 therebelow, so as to form the opening 130a in the substrate 100, and then the mask structure is completely removed. In one embodiment, an ion implantation process, such as an anti-punch-through (anti-punch-through) ion implantation process, may be performed to form the opening 130a, so as to further form a doped region (not shown) in the substrate 100 exposed by the opening 130a, thereby preventing current leakage.

The semiconductor memory device 300 further includes a plurality of insulating structures 150 and a plurality of bit lines 160 disposed on the substrate 100. The isolation structure 150 is disposed above the word line 120 and includes a plurality of isolation fins 151 and a plurality of isolation end portions 153, wherein each isolation fin 151 extends parallel to each other along the second direction D2 and is aligned with each word line 120 below in a projection direction (not shown) perpendicular to the substrate 110, and each isolation end portion 153 has a U-shaped structure and connects two adjacent isolation fins 151, as shown in fig. 1. In an embodiment, the isolation structure 150 may also be formed by the self-aligned double patterning or the self-aligned reverse patterning process, and preferably, the isolation structure 150 and the trenches 108 of the word lines 120 are respectively defined by a same mask layer (not shown), such that the isolation fins 151 of the isolation structure 150 may completely overlap the underlying word lines 120, but not limited thereto.

On the other hand, the bit lines 160 extend parallel to each other along the first direction D3, so that the bit lines 160 can be simultaneously interleaved with the active regions 101 in the direction D1 and the insulating structures 150 in the second direction D2. The first direction D3 is different from the direction D1 and the second direction D2, and is preferably perpendicular to the second direction D2 and not perpendicular to the direction D1, but not limited thereto. Each bit line 160 detail includes a semiconductor layer 161, a barrier layer 163, a metal layer 165, and a cap layer 167, which are sequentially stacked from bottom to top, wherein the semiconductor layer 161 filled in each opening 130a forms each Bit Line Contact (BLC) 160 a. Bitline contact 160a is located below bitline 160 and between two adjacent wordlines 120. Thus, bit line contact 160a and bit line 160 can be integrally formed, and bit line 160 and word line 120 can be isolated from each other by insulating layer 130 and further electrically connected to the source/drain regions of the transistor elements of semiconductor memory device 300 through bit line contact 160 a. In addition, spacers 170, which comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., are disposed on the sidewalls of the bit lines 160. In one embodiment, the spacer 170 may have a composite structure, such as a first spacer (not shown), a second spacer (not shown), etc. sequentially stacked on the sidewalls of the bit line 160, or a single-layer structure, as shown in fig. 1.

In one embodiment, the bit line 160 can be formed by the following steps, but is not limited thereto. First, a semiconductor material layer (not shown, such as a polysilicon layer) is formed on the substrate 100, the opening 130a is filled and further covered on the insulating layer 130, and then a barrier material layer (not shown, such as a titanium layer and/or a titanium nitride layer), a metal material layer (not shown, such as a low-resistance metal like tungsten, aluminum, or copper), and a cover material layer (not shown, such as an insulating material like silicon nitride, silicon oxide, or silicon carbonitride) are sequentially formed on the semiconductor material layer, but not limited thereto. Then, a patterning process is performed to pattern the capping material layer, the metal material layer, the barrier material layer, and the semiconductor material layer, so as to form a bit line 160 on the substrate 100.

It should be noted that the bit lines 160 further include a plurality of first bit lines 162 and at least one second bit line 164, and the first bit lines 162 and the second bit lines 164 are respectively disposed in a memory cell region (not shown) and a peripheral region (not shown) of the semiconductor memory device 300, and can be used as general Bit Lines (BLs) and dummy bit lines (dummy BLs), respectively, wherein the second bit lines 164 can be located at one side of all the first bit lines 162, but not limited thereto. Referring to fig. 1, in the present embodiment, the semiconductor memory device 300 preferably includes two second bit lines 164 respectively disposed on two opposite sides (i.e., upper and lower sides) of all the first bit lines 162 in the second direction D2 without crossing any active region 101, but not limited thereto. It should be readily understood by those skilled in the art that the memory region and the peripheral region may have other configurations such that the first bit lines and the second bit lines have other configurations or the second bit lines have other numbers. In addition, in the present embodiment, the line width (e.g., the width in the second direction D2) W2 of each second bit line 164 is preferably greater than the line width W1 of each first bit line 162, but not limited thereto. In another embodiment, the second bit line and the first bit line may have the same line width selectively.

It is to be noted that the formation of the isolation structure 150 is preferably performed after the formation of the bit line 160, so that each of the isolation fins 151 of the isolation structure 150 may penetrate through the cap layer 167 of the first bit line 162 and be partially embedded in the first bit line 162 (i.e., partially overlapped with the first bit line 162), as shown in fig. 1. That is, the portion of each of the insulated fins 151 overlapping the first bit line 162 is located within the cap layer 167 thereof, and may have a first depth S1 within the cap layer 167, for example, approximately equal to the thickness of the cap layer 167, such that the portion of each of the insulated fins 151 overlapping the first bit line 162 may directly contact the top surface of the metal layer 165, as shown in fig. 2. On the other hand, the portion of each insulation fin 151 not overlapping the first bit line 162 is located in the insulation layer 140 and may have a relatively larger second depth S2, such that the portion of each insulation fin 151 not overlapping the first bit line 162 may directly contact the insulation layer 130 and the spacer 170 disposed on the sidewall of the bit line 160. In other words, the material of the insulating layer 140 and the material of the cap layer 167 should have a certain etching selectivity, such as silicon oxide and silicon nitride, respectively. Thus, the etch selectivity may be used to slow the etch rate of the cap layer 167 during the formation of the isolation structure 150, thereby avoiding over-etching the metal layer 165 of the first bit line 162. In this way, the first bit line 162 is prevented from being damaged to affect the function thereof. In addition, the portion of each of the insulating fins 151 that does not overlap the first bit line 162 further includes a plurality of first segments 151a, a plurality of second segments 151b, and a plurality of third segments 151c that are unequal in length L1, L2, and L3 in the second direction D2, and the first segments 151a having the greater length are preferably located outside the second segments 151b, and the third segments 151c, which are smaller in length, in the first direction D3. For example, the first length L1 is greater than the second length L2, and the second length L2 is greater than the third length L3, so that the second segment 151b (the second length L2) is located at two opposite sides (i.e., left and right sides) of all the third segments 151c (the third length L3), and the first segment 151a (the first length L1) is further located at the outer side of the second segment 151b (the second length L2) and directly contacts the end faces of the first bit line 162 and the second bit line 164, as shown in fig. 1 and 2. Thus, the end surface of the bit line 160 can be further protected by the insulating structure 150, and other active devices (not shown) disposed above the substrate 100 can be isolated.

In addition, as shown in fig. 1, each insulating end 153 of the insulating structure 150 may be selectively embedded in the second bit line 164. For example, at least one of the insulating end portions 153 is, for example, completely embedded in the cap layer 167 of the second bit line 164, such as the insulating end portion 153 a; at least another one of the insulating end portions 153 is, for example, partially embedded in the cap layer 167 of the second bit line 164 such that the U-shaped structure thereof can partially extend outside the second bit line 164, such as the insulating end portion 153 b; at least another one of the insulated end portions 153 is, for example, completely exposed outside the second bit line 164, such as the insulated end portion 153 c. Similarly, the insulating end 153a overlapping the second bit line 164 or a portion of the insulating end 153b overlapping the second bit line 164 may be located in the cap layer 167 of the second bit line 164 and have a first depth S1, such that the top surface of the metal layer 165 may be directly contacted; the insulating end 153c not overlapping the second bit line 164 or the insulating end 153b not overlapping the second bit line 164 is located in the insulating layer 140, and has a relatively larger second depth S2 and directly contacts the insulating layer 130, as shown in fig. 3.

Thus, the semiconductor memory device 300 according to the first preferred embodiment of the present invention is constructed. Semiconductor memory device 300 is further isolated from word line 120 and bit line 160 by the provision of insulating structure 150 disposed over word line 120. It should be noted that the insulating structure 150 is disposed above the substrate 100 and directly contacts a portion of the end of the bit line 160 and the spacers 170 at two sides of the bit line 160, thereby providing an effect of protecting the bit line 160; the insulating structure 150 partially overlaps the bit line 160 (the insulating fin 151 partially overlaps the first bit line 162, and the insulating end 153 may overlap the second bit line 164), and the portion overlapping the bit line 160 is embedded in the cap layer 167 of the bit line 160 and has the first depth S1 equal to the thickness of the cap layer 167, so as to effectively protect the bit line 160 and avoid damaging the metal layer 165 of the bit line 160. In addition, the formation of the insulating structure 150 and the word line 120 can be separately defined through the same mask layer, so that the insulating structure 150 can be overlapped with the underlying word line 120, thereby forming the semiconductor memory device 300 with better device reliability and improving the performance thereof on the premise of obviously simplifying the manufacturing process.

It should be readily apparent to those skilled in the art that the semiconductor memory device of the present invention may have other aspects or be formed by other manufacturing processes without limitation to the above embodiments so as to meet the actual product requirements. For example, although the portion of the insulating fin 151 overlapping the first bit line 162 in the capping layer 167 has the first depth S1 equal to the thickness of the capping layer 167 in the aforementioned embodiment, the present invention is not limited thereto, and in another embodiment, the portion of the insulating fin 151 overlapping the first bit line 162 may have a third depth S3 smaller than the thickness of the capping layer 167, so as to further prevent the underlying metal layer 165 from being damaged, as shown in fig. 4. That is, the insulating fin 151 overlapping the first bit line 162 and the insulating end portions (e.g., the insulating end portions 153a, 153b) overlapping the second bit line 164 may have a relatively smaller third depth S3 within the cap layer 167 of the first bit line 162 or the second bit line 164 without contacting the metal layer 165. In addition, other embodiments or variations of the semiconductor memory device and the method of forming the same will be further described below. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 5, a top view of a semiconductor memory device 500 according to a second preferred embodiment of the utility model is shown. The structure of the semiconductor memory device 500 in this embodiment is substantially the same as that of the semiconductor memory device 300 in the first preferred embodiment, and the description thereof is omitted. The main difference between the present embodiment and the foregoing embodiment is that an insulating structure 250 is additionally disposed in the peripheral region of the semiconductor memory device 300.

In detail, the insulating structures 250 are disposed on two opposite sides (i.e., left and right sides) of all the insulating structures 150 in the first direction D3, and also include a plurality of insulating fins 251 and a plurality of insulating end portions 253 extending in parallel along the second direction D2 and having a U-shaped configuration. Each insulating end 253 of the insulating structure 250 connects two adjacent insulating fins 151 and does not overlap any bit line 160, so that each insulating structure 250 may have a racetrack shape as a whole, as shown in fig. 5.

In one embodiment, the isolation structure 250 may be formed by the self-aligned double patterning or the self-aligned reverse patterning process, and preferably, may be formed together with the isolation structure 150, and the trench 108 and the word line 120 may be separately defined by a same mask layer (not shown), so that the isolation fin 251 of the isolation structure 250 may also completely overlap the underlying word line 120 (not shown in fig. 5), but is not limited thereto. In another embodiment, the isolation structure 250 may be formed separately, such that no word line 120 is disposed below the isolation structure 250 or the isolation structure does not overlap with the word line 120 disposed below.

Thus, the semiconductor memory device 500 according to the second preferred embodiment of the present invention is constructed. The semiconductor memory device 500 is further isolated from external elements by the additionally provided insulating structure 250. The insulating structure 250 may be integrated with the fabrication process of the insulating structure 150, and the fabrication process and the formation of the word line 120 may be separately defined through the same mask layer, so that the insulating structure 250 may also overlap the underlying word line 120. Thus, the semiconductor memory device 500 with better device reliability can be formed and the performance thereof can be improved on the premise of obviously simplifying the manufacturing process.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A semiconductor memory device, comprising:

a substrate;

a plurality of bit lines disposed on the substrate and extending in a first direction, the bit lines including a plurality of first bit lines and at least one second bit line, the second bit line being disposed at one side of all the first bit lines; and

a plurality of insulating structures disposed on the substrate and interleaved with the bit lines, the insulating structures comprising a plurality of insulating ends and a plurality of insulating fins extending in a second direction, the second direction being perpendicular to the first direction, wherein at least one of the insulating ends is entirely within the second bit line.

2. The semiconductor memory device of claim 1, wherein each of said insulative end portions has a U-shaped configuration and connects two adjacent ones of said insulative fins.

3. The semiconductor memory device according to claim 1, wherein at least another one of the insulating end portions is located entirely outside the second bit line.

4. The semiconductor memory device according to claim 2, wherein the U-shaped structure portion of at least another one of the insulating end portions extends outside the second bit line.

5. The semiconductor memory device of claim 1, wherein each of the insulating fins partially overlaps the first bit line.

6. The semiconductor memory device according to claim 5, wherein the portion of the insulating fin that does not overlap the first bit line comprises a plurality of first segments, a plurality of second segments, and a plurality of third segments, the first segments, the second segments, and the third segments having a first length, a second length, and a third length, respectively, in the second direction, wherein the first length is greater than the second length, and the second length is greater than the third length.

7. The semiconductor memory device according to claim 6, wherein the second segments are disposed on opposite sides of all of the third segments, and the first segments are disposed outside the second segments.

8. The semiconductor memory device according to claim 6, wherein the first segment directly contacts an end face of the bit line of the portion.

9. The semiconductor memory device according to claim 6, further comprising:

an insulating layer disposed on the substrate, the first, second, and third segments directly contacting the insulating layer.

10. The semiconductor memory device according to claim 6, wherein a portion of the insulating fin overlapping the first bit line has a first depth in a projected direction of a substrate, the portion of the insulating fin not overlapping the first bit line has a second depth in the projected direction, the second depth being greater than the first depth.

11. The semiconductor memory device of claim 10, wherein the bit line comprises a semiconductor layer, a barrier layer, a metal layer, and a cap layer stacked in sequence, the insulating fin overlapping the portion of the first bit line within the cap layer of the first bit line.

12. The semiconductor memory device according to claim 11, wherein the at least one of the insulated end portions is embedded in the cap layer of the second bit line.

13. The semiconductor memory device of claim 1, further comprising a plurality of spacers respectively disposed on sidewalls of the bit lines, the insulating fins directly contacting the spacers.

14. The semiconductor memory device according to claim 1, further comprising

And a plurality of word lines arranged in the substrate and extending in the second direction, wherein the word line pairs are positioned in the insulating structure.

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