CN213093202U

CN213093202U - Semiconductor memory device with a plurality of memory cells

Info

Publication number: CN213093202U
Application number: CN202022312766.7U
Authority: CN
Inventors: 童宇诚; 赖惠先; 詹益旺
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2021-04-30
Anticipated expiration: 2030-10-16

Abstract

The utility model discloses a semiconductor storage device contains a basement, a plurality of active area, a plurality of first wire and an at least first plug. The active regions extend in parallel with each other along a first direction, and first conductive lines cross the active regions, wherein each of the first conductive lines has opposite first and second ends. The first plug is arranged on the first end of the first lead and is electrically connected with the first lead, wherein the first plug integrally wraps the first end of the first lead and directly contacts the top surface, the side wall and the end surface of the first end. Therefore, the contact area between the plug and the first lead wire can be increased, the contact resistance of the plug is reduced, and the reliability of the electrical connection between the plug and the first lead wire is further improved.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The utility model belongs to the technical field of the semiconductor storage and specifically relates to a semiconductor storage device is related to.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it has gradually replaced the DRAM cell with a planar gate structure under the current trend of mainstream development because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure.

Generally, a DRAM cell with a recessed gate structure includes a transistor element and a charge storage device to receive voltage signals from the bit line and the word line. However, due to the limitations of the process technology, the conventional DRAM cell with the recessed gate structure still has many drawbacks, and further improvements and improvements are needed to effectively improve the performance and reliability of the related memory device.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor memory device, in which plugs are disposed at two opposite ends of a bit line or a word line and entirely cover the ends of the bit line or the word line. Therefore, the plug can directly contact the top surface, the side wall and the end surface of the end part, the contact area between the plug and the bit line or the word line can be increased, the contact resistance of the plug is reduced, and the reliability of the electrical connection between the plug and the bit line or the word line is improved.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate, a plurality of active regions, a plurality of first conductive lines, and at least one first plug. The active regions extend in parallel with each other along a first direction, and the first conductive lines cross the active regions, wherein each of the first conductive lines has opposite first and second ends. The first plug is arranged on the first end of the first lead and electrically connected with the first lead, wherein the first plug integrally wraps the first end of the first lead and directly contacts the top surface, the side wall and the end surface of the first end.

The semiconductor memory device of the present invention is provided with plugs at two opposite ends of a conductive line (bit line or word line, etc.) and integrally covers the ends of the conductive line. Thus, the plug can directly contact with at least the top surface, the side wall and the end surface of the end part of the lead, the contact area between the plug and the lead is increased, and the contact resistance of the plug is reduced. Furthermore, the end of the conductive wire can be optionally provided with an additional protrusion to further increase the contact area between the plug and the conductive wire, wherein the protrusion can have various shapes (linear, L-shaped, arc-shaped or hook-shaped) or sizes. Therefore, the semiconductor memory device of the present invention contributes to improving the reliability of the electrical connection between the plug and the wire.

Optionally, the thickness of the sidewall of the first plug covering the first end is less than the thickness of the end face of the first plug covering the first end.

Optionally, the portions of the first plug overlying the side walls and the end faces at the first end have different depths in a direction perpendicular to the substrate.

Optionally, different sidewalls of the first plug have different distances to different surfaces of the first end, and a greater distance of the first plug from the first end is deeper in a direction perpendicular to the substrate.

Optionally, a bottom surface of the first plug is lower than a bottom surface of the first conductive line.

Optionally, the semiconductor memory device further includes: a plurality of second conductive lines extending in parallel with each other along a first direction and crossing the active region, wherein each of the second conductive lines is alternately arranged in sequence with each of the first conductive lines in a second direction perpendicular to the first direction, and each of the second conductive lines has opposite first and second ends; and at least one second plug arranged on the second end of the second lead and electrically connected with the second lead, wherein the second plug integrally covers the second end of the second lead.

Optionally, the first end of the first wire and the first end of the second wire are offset from each other in the second direction.

Optionally, the first plugs include a plurality of first plugs, and the first plugs are alternately disposed on the first ends of the first conductive lines and aligned with each other.

Optionally, the first end of each of the first conductive wires includes a first protrusion, and the first protrusions extend toward a third direction.

Optionally, the second end of each of the first conductive lines includes a second protrusion, and the second protrusions extend toward an opposite direction relative to the third direction.

Alternatively, each of the first protruding portions and each of the second protruding portions may have a linear shape or an L-shape.

Optionally, the first plug further wraps the first protrusion on the first end of the first wire.

Optionally, the first plug completely covers the end face of the first protrusion.

Optionally, the first conductive line is disposed within the substrate.

Optionally, the substrate further includes a shallow trench isolation surrounding the active region, wherein the first end of the first conductive line is disposed in the shallow trench isolation.

Optionally, the first conductive line is disposed on the substrate.

Optionally, the substrate further includes a shallow trench isolation surrounding the active region, wherein the first end of the first conductive line is disposed on the shallow trench isolation.

Optionally, the method further comprises: a plurality of third conductive lines extending in a first direction in parallel with each other, wherein the third conductive lines are disposed at one side of the first conductive lines, and each of the third conductive lines has opposite first and second ends; and

at least one third plug disposed on the third conductive line proximate to the first end of the third conductive line and electrically connected to the third conductive line, wherein the third plug does not cover the first end of the third conductive line.

Optionally, the third plug covers two opposite sidewalls and a top surface of the third conductive line.

Optionally, the method further comprises: and the insulating layer covers the active region and the first conducting wire, the first plug is arranged in the insulating layer, and the top surface of the first plug is flush with the top surface of the insulating layer.

Drawings

Fig. 1 to 8 are schematic views illustrating a semiconductor memory device according to a first preferred embodiment of the present invention; wherein

Fig. 1 is a schematic top view of a semiconductor memory device according to the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic cross-sectional view taken along line B-B' of FIG. 1;

FIG. 4 is another schematic cross-sectional view taken along line B-B' of FIG. 1;

FIG. 5 is a schematic cross-sectional view taken along line C-C' of FIG. 1;

FIG. 6 is a schematic cross-sectional view taken along line D-D' of FIG. 1;

FIG. 7 is another schematic cross-sectional view taken along line D-D' of FIG. 1;

FIG. 8 is a further cross-sectional view taken along line D-D' of FIG. 1;

fig. 9 is a schematic top view of a semiconductor memory device according to a second preferred embodiment of the present invention;

fig. 10 is a schematic top view of a semiconductor memory device according to a third preferred embodiment of the present invention.

Wherein the reference numerals are as follows:

100. a first semiconductor memory device; 200. a second semiconductor memory device; 300. a third semiconductor memory device; 101. a first region; 102. a second region; 110. a substrate; 112. shallow trench isolation; 113. an active region; 130. a first word line; 130a, a first bottom surface; 131. a dielectric layer; 133. a gate dielectric layer; 135. a gate electrode; 137. a third insulating layer; 140. a second insulating layer; 142. a first insulating layer; 150. a first bit line; 150a, a second bottom surface; 151. a semiconductor layer; 153. a first barrier layer; 155. a first metal layer; 157. a shielding layer; 160. bit line contact plugs; 170. a first plug; 190. a second plug; 171. a first barrier layer; 191. a second barrier layer; 173. a second metal layer; 193. a third metal layer; 170a, a third bottom surface; 190a, a fifth bottom surface; 170b, a fourth bottom surface; 190b, a sixth bottom surface; 230. a second word line; 231. a second protrusion; 233. a first protrusion; 231a, a third projection; 233a, a fourth projection; 250. a second bit line; 251. a fifth projection; 253. a sixth projection; 251a, a seventh projection; 253a, an eighth protrusion; 270. a third plug; 290. a fourth plug; 330. a third word line; 331. a ninth projection; 333. a tenth protrusion; 331a, an eleventh projection; 333a, a twelfth projection; 350. a third bit line; 351. a thirteenth projection; 353. a fourteenth projecting portion; 351a, a fifteenth projection; 353a, a sixteenth projection; 370. a fifth plug; 390. a sixth plug; d1, first direction; d2, second direction; d3, third direction; e1, first dashed box; e2, second dashed box; e3, third dashed box; e4, fourth dashed box.

Detailed Description

To further clarify the present invention, those skilled in the art will be able to understand the present invention by referring to the following detailed description of several preferred embodiments of the present invention, and by referring to the accompanying drawings, the constituent elements of the present invention and intended functions will be described in detail.

Referring to fig. 1 to 8, a first semiconductor memory device 100, which is a semiconductor memory device according to a first preferred embodiment of the present invention, is shown, wherein fig. 1 is a top view of the first semiconductor memory device 100, and fig. 2 to 8 are cross-sectional views of the first semiconductor memory device 100. The first semiconductor memory device 100 is, for example, a Dynamic Random Access Memory (DRAM), and includes at least one transistor element (not shown) and at least one capacitor structure (not shown) as a minimum unit in a DRAM array and receives voltage signals from a first conductive line, such as the first word line 130, and a second conductive line, such as the first bit line 150.

First, referring to fig. 1 and 2, a first semiconductor memory device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and at least one Shallow Trench Isolation (STI) 112 is disposed in the substrate 110 to define a plurality of active areas 113 in the substrate 110. The active regions 113 extend along a first direction D1, for example, parallel to and spaced apart from each other, and are alternately arranged along the first direction D1, so that the active regions 113 may be arranged in a specific array, such as the array shown in fig. 1, but not limited thereto. In one embodiment, each active region 113 is formed, for example, by a patterning process of the substrate 110, for example, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a plurality of patterns (not shown) for defining the active regions 113 and exposes a portion of the substrate 110, an etching process is performed using the mask layer to remove the portion of the substrate 110 and form at least one trench (not shown), and then a dielectric layer (not shown) such as silicon oxide, silicon nitride or silicon oxynitride is formed in the at least one trench, so that the shallow trench isolation 112 having a top surface aligned with the surface of the substrate 110 can be formed, and the active regions 113 are defined. Thus, the shallow trench isolations 112 may be disposed around the active region 113, and the specific fabrication process of the active region 113 is not limited to the above fabrication process. In another embodiment, the active region may be formed by a self-aligned double patterning (SADP) process, a self-aligned reverse patterning (SARP) process, or the like.

Referring to fig. 1 and 2, a plurality of buried gates 135 are formed in the substrate 110 to serve as buried first word lines 130 (BWL). The first word lines 130 extend parallel to each other along the second direction D2 and cross under the active regions 113 (in the first direction D1), as shown in fig. 1. In one embodiment, the first word line 130 is formed by, for example, but not limited to, the following process. First, a plurality of trenches (not shown) are formed in the substrate 110, the trenches are parallel to each other and extend toward the second direction D2, and then a dielectric layer 131 covering the entire surface of each trench, a gate dielectric layer 133 and a gate 135 filling the bottom half of each trench, and a third insulating layer 137 filling the top half of each trench are sequentially formed, wherein the top surface of the third insulating layer 137 is cut to be flush with the surface of the substrate 110, as shown in fig. 2. Thus, the gates 135 in each of the trenches extend in parallel to each other in the second direction D2 to form the first word line 130 shown in fig. 1.

A second insulating layer 140 is formed on the substrate 110, and the second insulating layer 140 includes, for example, an oxide-nitride-oxide (ONO) structure to cover the surface of the substrate 110 and the first word lines 130 embedded in the substrate 110. Referring to fig. 1 and 5, a plurality of first bit lines 150 are further formed on the substrate 110, wherein the first bit lines 150 extend parallel to each other along the third direction D3 and simultaneously cross the active region 113 in the first direction D1 and the first word line 130 in the second direction D2. That is, the third direction D3 is different from the first direction D1 and the second direction D2, and is preferably perpendicular to the second direction D2 and not perpendicular to the first direction D1. Also, a plurality of bit line contacts 160 (BLC) are formed below a portion of the first bit lines 150, respectively, between two adjacent first word lines 130. Thus, the first bit line 150 and the first word line 130 are isolated from each other by the second insulating layer 140, and further electrically connected to a source/drain region (not shown) of the transistor device of the first semiconductor memory device 100 through the bit line contact plug 160.

In one embodiment, the first bit line 150 and the bit line contact plug 160 are formed by, for example, but not limited to, the following processes. First, another mask layer (not shown) is formed on the substrate 110, the another mask layer can be used to define the position (not shown) where the bit line contact plug 160 is formed, an etching process is performed using the another mask layer to remove the second insulating layer 140 at the position and the substrate 110 below the second insulating layer, so as to form a plurality of openings (not shown) on the surface of the substrate 110 between two adjacent word lines, and then the another mask layer is completely removed. When the openings are formed, an ion implantation process, such as an anti-junction-breakdown (anti-punch-through) ion implantation process, may be performed to further form a doped region (not shown) in the substrate 110 exposed by the openings, so as to achieve the effect of avoiding current leakage. Then, a semiconductor layer (not shown, such as a polysilicon layer) is formed on the substrate 110, the openings are filled and further covered on the substrate 110, and a barrier layer (not shown, such as a titanium layer and/or a titanium nitride layer), a metal layer (not shown, such as a low-resistance metal including tungsten, aluminum, or copper), and a shielding layer (not shown, such as silicon nitride or silicon carbonitride) are sequentially formed on the semiconductor layer. Then, a patterning process is performed on the semiconductor layer, the barrier layer, the metal layer and the shielding layer stacked on each other, such that the semiconductor layer filled in the openings forms a bit line contact plug 160, and the bit line contact plug 160 or the semiconductor layer 151, the first barrier layer 153, the first metal layer 155 and the shielding layer 157 stacked on the substrate 110 form a first bit line 150, as shown in fig. 5. Through the above-mentioned fabrication process, the bit line contact plug 160 is integrally formed with the semiconductor layer 151 of the first bit line 150, such that the bit line contact plug 160 and the semiconductor layer 151 of the first bit line 150 may comprise the same material (e.g., polysilicon), but not limited thereto. In another embodiment, the bit line contact plugs and the bit lines may also be selected to comprise different materials. In another embodiment, to simplify the manufacturing process of the first semiconductor memory device 100, the word lines or the bit lines may be formed by the self-aligned double patterning process or the self-aligned reverse patterning process.

It should be noted that the first semiconductor memory device 100 further includes a first region 101 and a second region 102, wherein the first region 101 is, for example, a region with a relatively high device integration level, such as a memory cell region (memory cell region), and the second region 102 is a region with a relatively low device integration level, such as a peripheral region (peripheral region), but not limited thereto. In the present embodiment, the second region 102 is disposed outside the first region 101 and surrounds the first region 101, the active region 113, the first word line 130 and the first bit line 150 are mainly disposed in the first region 101, and the first word line 130 and the first bit line 150 further extend to the second region 102 and are electrically connected to an external circuit (not shown) through the first plugs 170 and the second plugs 190 disposed in the second region 102, as shown in fig. 1. However, it should be easily understood by those skilled in the art that the relative positions of the first region and the second region are not limited to those shown in fig. 1; meanwhile, in fig. 1, only a portion of the first region 101 is shown in order to clearly show the connection relationship between the first plug 170 and the first word line 130 or between the second plug 190 and the first bit line 150, so that the specific number of the active regions 113, the first word line 130 and the first bit line 150 is not limited to that shown in fig. 1.

Specifically, the first plug 170 and the second plug 190 are preferably disposed at two opposite ends of the first word line 130 or the first bit line 150, and entirely cover the ends. The ends of the first word lines 130 refer to, for example, two opposite ends of each first word line 130 in the second direction D2, which are about 1% to 5% of the total length, that is, each first word line 130 is located at a first end in the first dashed box E1 in fig. 1, and at a second end in the second dashed box E2 in fig. 1, and the first ends or the second ends are located in the shallow trench isolations 112, as shown in fig. 1 and 2. Referring to fig. 1 again, the first plugs 170 electrically connecting the first word lines 130 are alternately disposed on the first end or the second end of the adjacent first word lines 130, that is, the first plugs 170 are sequentially disposed from the right side to the left side of fig. 1 at the first end of the first word line 130, at the second end of the second word line 130, at the first end of the third word line 130, and so on; also, the respective first plugs 170 may be aligned with each other in a third direction D3 perpendicular to the second direction D2, but is not limited thereto. In this embodiment, the first plug 170 may be directly disposed on the first end or the second end of the first word line 130, and entirely covers the first end or the second end. That is, each first plug 170 may directly contact at least four surfaces of the first end or the second end, including a top surface of the first end or the second end, two opposite side wall surfaces of the first end or the second end in the second direction D2, and an end surface of the first end or the second end in the perpendicular second direction D2 (i.e., the third direction D3), as shown in fig. 1, but not limited thereto. In another embodiment, at least a portion of the first plug 170 (shown in the left side of fig. 1) may be selectively disposed at a position other than the first end or the second end of the first word line 130, without covering the first end or the second end. For example, at least a portion of the first word lines 130 (as shown in the left side of fig. 1) may have a relatively long length, such that the first plugs 170 disposed on the at least a portion of the first word lines 130 cannot cover two opposite ends (the first end or the second end) of the first word lines 130, especially cannot cover an end surface of the first end or the second end in the third direction D3, provided that the first plugs 170 are disposed opposite to each other in the third direction D3. In this case, the first plug 170 of the portion can directly contact only three surfaces of the first word line 130, including the top surface of the first word line 130 and two opposite sidewall surfaces of the first word line 130 in the second direction D2, as shown in the left side of fig. 1. In the foregoing embodiment, the at least one portion of the first word line 130 (as shown in the left side of fig. 1) is preferably disposed at the edge of the first region 101 or in the second region 102, but not limited thereto.

Similarly, the ends of the first bitlines 150 refer to, for example, the two opposite ends of each first bitline 150 in the third direction D3 being about 1% to 5% of the total length, i.e., each first bitline 150 is located at a first end within the third dashed box E3 of fig. 1 and at a second end within the fourth dashed box E4 of fig. 1, the first end or the second end being located on the sti 112, as shown in fig. 1 and 5. Referring to fig. 1 again, the plurality of second plugs 190 electrically connected to each first bit line 150 are alternately disposed on the first end or the second end of the adjacent first bit line 150, that is, the second plugs 190 are sequentially disposed on the second end of the first bit line 150, the first end of the second first bit line 150, the second end of the third first bit line 150, and so on from the bottom to the top in fig. 1; also, the respective second plugs 190 may be aligned with each other in a second direction D2 perpendicular to the third direction D3. In this embodiment, the second plug 190 may be directly disposed on the first end or the second end of the first bit line 150, and entirely covers the first end or the second end. That is, each of the second plugs 190 may directly contact at least four surfaces of the first end or the second end, including a top surface of the first end or the second end, two opposite side wall surfaces of the first end or the second end in the third direction D3, and an end surface of the first end or the second end in the perpendicular third direction D3 (i.e., the second direction D2), as shown in fig. 1, but is not limited thereto. In another embodiment, at least a portion of the second plug 190 (as shown in the upper portion of fig. 1) may also be selectively disposed at a position other than the first end or the second end of the first bit line 150, without covering the first end or the second end. For example, at least a portion of the first bitlines 150 (as shown in the top of fig. 1) may have a relatively long length, such that the second plugs 190 disposed on the at least a portion of the first bitlines 150 cannot cover two opposite ends (the first end or the second end) of the first bitlines 150, especially cannot cover an end surface of the first end or the second end in the second direction D2, if the second plugs 190 are disposed opposite to each other in the second direction D2. In this case, the second plug 190 of the portion can directly contact only three surfaces of the first bit line 150, including the top surface of the first bit line 150 and two opposite sidewall surfaces of the first bit line 150 in the third direction D3, as shown in the upper part of fig. 1. In the foregoing embodiment, the at least one portion of the first bit line 150 (as shown in the upper part of fig. 1) is preferably disposed at the edge of the first region 101 or in the second region 102, but not limited thereto.

On the other hand, the portions of the first plugs 170 and the second plugs 190 respectively covering the surfaces (including the top surfaces, the sidewall surfaces and/or the end surfaces) of the first word lines 130 (the first ends or the second ends) or the first bit lines 150 (the first ends or the second ends) may have the same or different thicknesses, and accordingly, the portions of the first plugs 170 or the second plugs 190 may have the same or different depths in the direction perpendicular to the substrate 110. In one embodiment, the first plug 170 or the second plug 190 is formed by, for example, but not limited to, the following processes; the process for forming the first plug 170 may be performed together with or separately from the process for forming the second plug 190. First, a first insulating layer 142 is formed, wherein the first insulating layer 142 comprises, for example, silicon oxide, silicon oxynitride, or silicon nitride, and entirely covers the substrate 110 to serve as an interlayer dielectric (ILD). Then, a further mask layer (not shown) is formed on the first insulating layer 142, the further mask layer may be used to define a formation portion (not shown) of the first plug 170 or the second plug 190, an etching process is performed using the further mask layer to remove the first insulating layer 142 at the formation portion and the second insulating layer 140 thereunder, or only the first insulating layer 142 at the formation portion is removed, a plurality of plug holes (not shown) are formed to expose the first end or the second end of the first word line 130, or to expose the first end or the second end of the first bit line 150, and then the further mask layer is completely removed. Then, a barrier layer (not shown) and a metal layer (not shown) are sequentially deposited (for example, including titanium, titanium nitride, tantalum or tantalum oxide) and filled into each of the plugs, and an etch-back process is performed to form the first plug 170 or the second plug 190. As such, the top surface of the first plug 170 or the second plug 190 may be flush with the top surface of the first insulating layer 142; each first plug 170 may include a first barrier layer 171 covering the surface of each plug hole and a second metal layer 173 filling each plug hole, as shown in fig. 2 and 3; each second plug 190 may include a second barrier layer 191 covering the surface of each plug hole and a third metal layer 193 filling each plug hole, as shown in fig. 5 and 6.

It should be noted that, during the etching process of the plug hole, the introduced etchant or etching gas may be blocked by the lower first word line 130 (the first end or the second end) or the first bit line 150 (the first end or the second end), and therefore, when the sidewall of the plug hole is too close to the sidewall of the first word line 130 (the first end or the second end) or the first bit line 150 (the first end or the second end), the etchant or the etching gas may not be introduced smoothly, and the etching rate of the etching process is affected. Therefore, the sidewall of the first plug 170 (shown on the right side of fig. 2) may gradually slope toward the sidewall of the first word line 130 (the first end or the second end) until directly contacting the sidewall of the first word line 130 (the first end or the second end), such that the portions of the first plug 170 (shown on the right side of fig. 2) covering the two opposite sidewalls of the first word line 130 (the first end or the second end) may have different depths d1, d2 within the substrate 110, respectively, as shown in fig. 2. Also, the maximum distance L1 from the sidewall having the smaller depth d1 to the sidewall surface of the first word line 130 (the first end or the second end) of the first plug 170 (as shown on the right side of fig. 2) may be smaller than the maximum distance L2 from the sidewall having the larger depth d2 to the sidewall surface of the first word line 130 (the first end or the second end) of the first plug 170 (as shown on the right side of fig. 2), i.e., the portions of the first plug 170 (as shown on the right side of fig. 2) respectively covering the two opposite sidewall surfaces of the first word line 130 (the first end or the second end) may have different thicknesses L1, L2, as shown on the right side of fig. 2. In another embodiment, the portions of the first plugs 170 (shown on the left side of fig. 2) covering the two opposite sidewalls of the first word lines 130 (the first end or the second end) may also have the same depth d2 in the substrate 110 and the same thickness L2, as shown on the left side of fig. 2. Preferably, the portion of the first plug 170 covering the end surface of the first word line 130 (the first end or the second end) may have a relatively maximum thickness L3 (thickness L3 > thickness L1 (shown in fig. 2) or thickness L2 (shown in fig. 2)) to ensure that the first plug 170 may completely cover the end surface of the first end or the second end, as shown in fig. 3. In addition, although the maximum depth d2 of each portion of the surface of the first word line 130 (the first end or the second end) covered by the first plug 170 in the substrate 110 in the above embodiment is described as an implementation mode that the depth of the first word line 130 (the first end or the second end) in the substrate 110 is not exceeded, the third bottom surface 170a of each portion of the surface of the first word line 130 (the first end or the second end) covered by the first plug 170 may be coplanar with the first bottom surface 130a of the first word line 130 (the first end or the second end), as shown in fig. 2 and 3, but not limited thereto. It should be readily understood by those skilled in the art that, in other embodiments, the depth of the first plug 170 formed in the substrate 110 may be adjusted according to actual process requirements, so as to selectively make at least one bottom surface of each of the portions of the surface of the first word line 130 (the first end or the second end) covered by the first plug 170 lower than the first bottom surface 130a of the first word line 130, for example, fig. 4 illustrates a situation where the fourth bottom surface 170b of the end surface portion of the first word line 130 (the first end or the second end) covered by the first plug 170 is lower than the first bottom surface 130a of the first word line 130, and thus, the portion may have a relatively larger depth d3 in the substrate 110. In a preferred embodiment, the greater the distance from the sidewall of the first plug 170 to the surface of the first word line 130, the deeper the depth of the portion in the direction perpendicular to the substrate 110, such as the portion of the first plug 170 covering the end surface of the first word line 130, but not limited thereto.

Similarly, the sidewall of the second plug 190 (shown on the left side of fig. 5) may gradually incline toward the first bit line 150 (the first end or the second end) until directly contacting the sidewall surface of the first bit line 150 (the first end or the second end), so that the portions of the second plug 190 (shown on the left side of fig. 5) covering the two opposite sidewall surfaces of the first bit line 150 (the first end or the second end) may have different depths d4, d5 within the first insulating layer 142, respectively, as shown in fig. 5. Also, the maximum distance L4 between the sidewall of the first bit line 150 (the first end or the second end) and the sidewall of the second plug 190 (the left side of fig. 5) having the smaller depth d4 is smaller than the maximum distance L5 between the sidewall of the first bit line 150 (the first end or the second end) having the larger depth d5, that is, the portions of the second plug 190 (the left side of fig. 5) covering the opposite sidewalls of the first bit line 150 (the first end or the second end) have different thicknesses L4, L5, as shown in the left side of fig. 5. In another embodiment, the portions of the second plugs 190 (shown on the right side of fig. 5) covering the two opposite sidewalls of the first bit line 150 (the first end or the second end) may also have the same depth d5 in the first insulating layer 142 and the same thickness L5, as shown on the right side of fig. 5. Preferably, the portion of the second plug 190 covering the end surface of the first bit line 150 (the first end or the second end) may have a relatively maximum thickness L6 (thickness L6 > thickness L3 (as shown in fig. 3 and 4) or thickness L4 (as shown in fig. 3 and 4)) to ensure that the second plug 190 may completely cover the end surface of the first end or the second end, as shown in fig. 6. In addition, although the maximum depth d5 of each portion of the surface of the first bit line 150 (the first end or the second end) covered by the second plug 190 in the first insulating layer 142 in the above embodiments is described as an implementation mode, the depth of the first bit line 150 (the first end or the second end) in the first insulating layer 142 is not more than the depth of the second bit line 150 (the first end or the second end) so that the fifth bottom surface 190a of each portion of the surface of the first bit line 150 (the first end or the second end) covered by the second plug 190 may be coplanar with the second bottom surface 150a of the first bit line 150 (the first end or the second end), i.e., on the second insulating layer 140, as shown in fig. 5 and 6, but not limited thereto. It should be readily understood by those skilled in the art that, in other embodiments, the depth of the second plug 190 formed in the first insulating layer 142 may also be adjusted according to actual process requirements, so that at least one bottom surface of each of the portions of the surface of the first bit line 150 (the first end or the second end) covered by the second plug 190 may be lower than the second bottom surface 150a of the first bit line 150, for example, fig. 7 illustrates a state in which the sixth bottom surface 190b of the end surface portion of the first bit line 150 (the first end or the second end) covered by the second plug 190 is lower than the second bottom surface 150a of the first bit line 150, so that the portion may further penetrate through the second insulating layer 140 to have a relatively larger depth d 6. Briefly, the distance between each sidewall of the second plug 190 and each surface of the end portion (the first end or the second end) of the first bit line 150 may be the same or different, so that the thickness of the second plug 190 covering each surface of the first bit line 150 may be the same or different, in a preferred embodiment, the greater the distance between the sidewall of the second plug 190 and the surface of the first bit line 150, the deeper the depth of the portion in the direction perpendicular to the substrate 110, such as the portion of the second plug 190 covering the end surface of the first bit line 150, but not limited thereto.

In addition, in a situation where the second plug 190 can further penetrate the second insulating layer 140, after the plug hole is etched down to remove the second insulating layer 140, a lateral etching process can be optionally performed to partially remove the shallow trench isolation 112 under the first bit line 150 (the first end or the second end), so that the formed second plug 190 can further cover a second bottom surface 150a of a portion of the first bit line 150, as shown in fig. 8, whereby the second plug 190 can directly contact five surfaces of the first bit line 150 (the first end or the second end), including the top surface and the bottom surface, two opposite sidewall surfaces, and the end surface of the first end or the second end, thereby increasing the contact area between the second plug 190 and the first bit line 150.

Thus, as shown in fig. 1 to 8, in the first semiconductor memory device 100 according to the first preferred embodiment of the present invention, the first plug 170 electrically connected to the first word line 130 and/or the second plug 190 electrically connected to the first bit line 150 are disposed at two opposite ends of the first word line 130 or the first bit line 150, and entirely cover the ends. Thus, the first plug 170 and/or the second plug 190 may directly contact at least four surfaces of the first word line 130 (the first end or the second end) or the first bit line 150 (the first end or the second end), including a top surface, two opposite sidewall surfaces, and an end surface of the first end or the second end, so as to increase a contact area between the first plug 170 and the first word line 130 and/or the second plug 190 and the first bit line 150, such that the first plug 170 electrically connected to the first word line 130 and/or the second plug 190 electrically connected to the first bit line 150 may have a relatively low contact resistance (Rc). In addition, the portions of the first plug 170 overlying the surfaces (including the top surface, the side wall surface and/or the end surface, and even the bottom surface) of the first bit line 150 and/or the second plug 190 may have the same or different thicknesses, respectively, and accordingly, the portions of the first plug 170 and/or the second plug 190 may have the same or different depths in the direction perpendicular to the substrate 110, and the thicker portions have the depths thereof being relatively deeper. Preferably, the portion of the first plug 170 covering the end surface of the first word line 130 and/or the portion of the second plug 190 covering the end surface of the first bit line 150 may have a relatively maximum thickness L3/L6 and a depth d2/d5 (or a depth d3/d6) relative to the portion of the first plug 170 and/or the portion of the second plug 190 covering the other portions of the first word line 130 and the first bit line 150, so as to ensure that the first plug 170 and/or the second plug 190 can completely cover the end surface of the end portion (the first end or the second end) of the first word line 130 and/or the first bit line 150.

The present invention is applicable to semiconductor memory devices that can be easily manufactured by other processes, and is not limited to the above-mentioned ones. For example, although the configuration of the first plug 170 electrically connected to the first word line 130 and/or the second plug 190 electrically connected to the first bit line 150 is illustrated in the foregoing embodiments, the present invention is not limited thereto, and in another embodiment, the configuration of the first plug 170 and/or the second plug 190 may also be used to electrically connect to other conductive lines of the semiconductor memory device, or the first plug 170 and/or the second plug 190 may have a different configuration. Therefore, further description will be made below with respect to other embodiments or variations of the semiconductor memory device and the method of forming the same. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 9, a schematic diagram of a second semiconductor memory device 200 according to a second preferred embodiment of the present invention is shown. The second semiconductor memory device 200 of the present embodiment is substantially the same as the first semiconductor memory device 100 of the first preferred embodiment, and includes the substrate 110, the shallow trench isolation 112, the active region 113, and the like, and the description of the same parts will not be repeated. The main difference between the present embodiment and the previous embodiments is that the opposite ends of the second word line 230 or the second bit line 250 of the present embodiment are additionally provided with protrusions, the protrusions extend in a direction perpendicular to the second word line 230 or the second bit line 250, and the third plug 270 electrically connected to the second word line 230 and/or the fourth plug 290 electrically connected to the second bit line 250 are still disposed at the opposite ends of the second word line 230 or the second bit line 250, and optionally integrally cover the ends and the protrusions, or partially cover the ends and the protrusions.

In detail, the first ends and the second ends of two adjacent second word lines 230 are respectively provided with a second protrusion 231 and a first protrusion 233, and the second protrusion 231 and the first protrusion 233 both extend in a direction perpendicular to the second word lines 230 (i.e., in a direction perpendicular to the second direction D2), so that each second word line 230 can be L-shaped or inverted L-shaped as a whole in the second direction D2, but not limited thereto. The first protruding portion 233 disposed at the second end of the second word line 230 extends in the third direction D3, and the second protruding portion 231 disposed at the first end of the second word line 230 extends in the opposite direction of the third direction D3, as shown in fig. 9. In one embodiment, the second protrusion 231 and the first protrusion 233 may have the same length, so that two adjacent second word lines 230 may be rotationally symmetric with respect to a geometric axis (not shown), but not limited thereto. In another embodiment, the protrusions disposed on the first end or the second end may have different lengths. Therefore, the third plugs 270 disposed at two opposite ends of the second word line 230 for electrically connecting the second word line 230 can directly contact more surfaces of the first end or the second end on the premise of completely covering the first end or the second end and the second protrusion 231 or the first protrusion 233 disposed on the first end or the second end, thereby further increasing the contact area between the third plugs 270 and the second word line 230, and further effectively reducing the resistance of the third plugs 270. In a preferred embodiment, the greater the distance from each sidewall of the third plug 270 to each surface of the second protrusion 231 or the first protrusion 233, the deeper the depth of the portion in the direction perpendicular to the substrate 110, and the portion of the third plug 270 covering the end surface of the second protrusion 231 or the first protrusion 233 in the second direction D2 is, but not limited thereto.

Similarly, the first end and the second end of each of two adjacent second bit lines 250 are respectively provided with a fifth protrusion 251 and a sixth protrusion 253, and the fifth protrusion 251 and the sixth protrusion 253 both extend in a direction perpendicular to the second bit lines 250 (i.e., a direction perpendicular to the third direction D3), so that each of the second bit lines 250 may be L-shaped or inverted L-shaped as a whole in the third direction D3, but the invention is not limited thereto. The sixth protrusion 253 disposed at the second end of the second bit line 250 extends in the second direction D2, and the fifth protrusion 251 disposed at the first end of the second bit line 250 extends in the opposite direction of the second direction D2, as shown in fig. 9. In an embodiment, the fifth protrusion 251 and the sixth protrusion 253 may have the same length, so that two adjacent second bit lines 250 may be rotationally symmetric with respect to a geometric axis (not shown), but not limited thereto. In another embodiment, the protrusions disposed on the first end or the second end may have different lengths. Therefore, the fourth plugs 290 disposed at two opposite ends of the second bit line 250 for electrically connecting the second bit line 250 can directly contact more surfaces of the first end or the second end on the premise of completely covering the first end or the second end and the fifth protrusion 251 or the sixth protrusion 253 disposed on the first end or the second end, so as to further increase the contact area between the fourth plugs 290 and the second bit line 250, and further effectively reduce the resistance of the fourth plugs 290. In a preferred embodiment, the greater the distance from each sidewall of the fourth plug 290 to each surface of the fifth protrusion 251 or the sixth protrusion 253, the deeper the depth of the portion in the direction perpendicular to the substrate 110, and the portion of the fourth plug 290 covering the end surface of the fifth protrusion 251 or the sixth protrusion 253 in the third direction D3 is, but not limited thereto.

On the other hand, in one embodiment, two adjacent second word lines 230 may be selectively aligned with each other in the third direction D3 (as shown on the left side of fig. 9) or alternatively arranged with each other in a staggered manner (as shown on the right side of fig. 9). That is, the first ends or the second ends of two adjacent second word lines 230 may be shifted by a distance g1 in the second direction D2, so that the second protrusion 231 and the third protrusion 231a disposed on the first ends, or the first protrusion 233 and the fourth protrusion 233a disposed on the second ends, may be shifted by a distance g1, respectively, as shown in the right side of fig. 9. Alternatively, the adjacent second bit lines 250 may be aligned with each other in the second direction D2 (as shown in the upper part of fig. 9) or may be arranged in a staggered manner (as shown in the lower part of fig. 9). That is, the first ends or the second ends of two adjacent second bit lines 250 may be staggered by a distance g1 in the third direction D3, so that the fifth protrusion 251 and the seventh protrusion 251a disposed on the first ends, or the sixth protrusion 253 and the eighth protrusion 253a disposed on the second ends, may also be correspondingly staggered by a distance g1, as shown in the lower part of fig. 9. Thus, when the third plug 270 electrically connected to the second word line 230 or the fourth plug 290 electrically connected to the second bit line 250 is disposed, the adjacent third plug 270 or the adjacent fourth plug 290 has a relatively large manufacturing space, thereby preventing a short circuit. In another embodiment, the third plug 270 electrically connected to the second word line 230 or the fourth plug 290 electrically connected to the second bit line 250 may also cover the first end or the second end, but only partially covers the second protrusion 231/the fifth protrusion 251 or the first protrusion 233/the sixth protrusion 253 provided on the first end or the second end, such that at least one surface of the second protrusion 231/fifth protrusion 251 or first protrusion 233/sixth protrusion 253 (e.g., the end surface of the second protrusion 231/fifth protrusion 251 or first protrusion 233/sixth protrusion 253) is not covered by the third plug 270/fourth plug 290, thus, there may be a relatively larger manufacturing space between the adjacent third plugs 270 (as shown on the left side of fig. 9) or the adjacent fourth plugs 290 (as shown on the top side of fig. 9).

Therefore, the semiconductor memory device according to the second preferred embodiment of the present invention is the second semiconductor memory device 200, which further increases the contact area of the third plug 270 electrically connected to the second word line 230 and/or the fourth plug 290 electrically connected to the second bit line 250 through the protrusion portions additionally formed at the opposite ends of the second word line 230 and/or the second bit line 250, and can more effectively reduce the resistance of the third plug 270 and/or the fourth plug 290. It should be easily understood by those skilled in the art that the shapes of the protruding portions in the foregoing embodiments are all illustrated as linear shapes, but are not limited thereto. On the premise of increasing the contact area between the plug and the conductive wire, the protruding portion can be further changed or configured in different ways according to the actual device requirements. For example, in other embodiments, the protrusion may have other shapes, such as an L-shape, or have different sizes or lengths.

Referring to fig. 10, a third semiconductor memory device 300 according to a third preferred embodiment of the present invention is shown. The third semiconductor memory device 300 of the present embodiment is substantially the same as the second semiconductor memory device 200 of the second preferred embodiment, and the description thereof is omitted. The main difference between the present embodiment and the previous embodiments is only the shape of the protrusion, and the fifth plug 370 electrically connected to the third word line 330 and/or the sixth plug 390 electrically connected to the third bit line 350 are still disposed at two opposite ends of the third word line 330 or the third bit line 350, and can selectively cover the ends and the protrusion entirely or partially.

Specifically, the ninth protrusion 331 and the tenth protrusion 333 disposed at the first end or the second end of the third word line 330 are, for example, L-shaped or inverted L-shaped. Preferably, each of the tenth protrusions 333 provided at the first end and each of the ninth protrusions 331 provided at the second end may have the same size and shape. Thus, the adjacent third word lines 330 may be rotationally symmetric with respect to a geometric axis (not shown), but not limited thereto. However, in another embodiment, the protrusions disposed at the first end or the second end of the third word line 330 may have different sizes or shapes. Therefore, the fifth plugs 370 disposed at two opposite ends of the third word line 330 for electrically connecting the third word line 330 can directly contact more surfaces of the first end or the second end on the premise of completely covering the first end or the second end and the ninth protrusion 331 or the tenth protrusion 333 disposed on the first end or the second end, thereby further increasing the contact area between the fifth plugs 370 and the third word line 330, and further effectively reducing the resistance of the fifth plugs 370. Similarly, the thirteenth protrusion 351 and the fourteenth protrusion 353 disposed at the first end or the second end of the third bit line 350 may also have an L shape or an inverted L shape, and each of the fourteenth protrusion 353 disposed at the first end and the thirteenth protrusion 351 disposed at the second end preferably have the same size and shape. Thus, the adjacent third bit lines 350 may be rotationally symmetric with respect to a geometric axis (not shown), but not limited thereto. However, in another embodiment, the protrusion disposed at the first end or the second end of the third bit line 350 may have different sizes or shapes. Therefore, the sixth plugs 390 disposed at two opposite ends of the third bit line 350 for electrically connecting the third bit line 350 can directly contact more surfaces of the first end or the second end on the premise of completely covering the first end or the second end and the thirteenth protrusion 351 or the fourteenth protrusion 353 disposed on the first end or the second end, thereby further increasing the contact area between the sixth plugs 390 and the third bit line 350, and further effectively reducing the resistance of the sixth plugs 390. It should be noted that, the distance between each sidewall of the fifth plug 370 or the sixth plug 390 and each protrusion surface may be the same or different, so that the thickness of the plug 37 or the sixth plug 390 covering each protrusion surface may be the same or different, in a preferred embodiment, the greater the distance between the sidewall of the fifth plug 370 or the sixth plug 390 and the protrusion surface, the deeper the depth of the portion in the direction perpendicular to the substrate 110, and the portion is preferably the portion of the fifth plug 370 or the sixth plug 390 covering the end surface of the protrusion, but not limited thereto.

On the other hand, in an embodiment, two adjacent third word lines 330 may also be selectively aligned with each other in the third direction D3 (as shown on the left side of fig. 10), or may also be arranged offset from each other (as shown on the right side of fig. 10). That is, the first ends or the second ends of two adjacent third word lines 330 may be shifted by a distance g1 in the second direction D2, so that the ninth protrusion 331 and the eleventh protrusion 331a disposed on the first ends, or the tenth protrusion 333 and the twelfth protrusion 333a disposed on the second ends may be shifted by a distance g1, respectively, as shown in the right side of fig. 10. Alternatively, the adjacent third bit lines 350 may be alternatively aligned with each other in the second direction D2 (as shown in the upper part of fig. 10), or may be alternatively aligned with each other in a staggered manner (as shown in the lower part of fig. 10). That is, the first ends or the second ends of two adjacent third bit lines 350 may be shifted by a distance g1 in the third direction D3, so that the thirteenth protrusion 351 and the fifteenth protrusion 351a disposed on the first ends, or the fourteenth protrusion 353 and the sixteenth protrusion 353a disposed on the second ends, may also be shifted by a distance g1, respectively, as shown in fig. 10 below. Thus, when the fifth plug 370 electrically connected to the third word line 330 is disposed or the sixth plug 390 electrically connected to the third bit line 350 is disposed, the adjacent fifth plug 370 or the adjacent sixth plug 390 may have a relatively large manufacturing space to avoid short circuit. In addition, in another embodiment, the fifth plug 370 electrically connected to the third word line 330 or the sixth plug 390 electrically connected to the third bit line 350 may also cover the first end or the second end, but only partially covers the ninth protrusion 331/the thirteenth protrusion 351 or the tenth protrusion 333/the fourteenth protrusion 353 disposed on the first end or the second end, such that at least one surface of the ninth projection 331/thirteenth projection 351 or the tenth projection 333/fourteenth projection 353 (e.g. the above-mentioned end surface of the ninth projection 331/thirteenth projection 351 or the tenth projection 333/fourteenth projection 353) is not covered by the fifth 370/sixth 390 plug, thus, there may be a relatively larger manufacturing space between adjacent fifth plugs 370 (as shown on the left side of fig. 10) or adjacent sixth plugs 390 (as shown on the top side of fig. 10).

Thus, the third semiconductor memory device 300 according to the third preferred embodiment of the present invention can further increase the contact area of the fifth plug 370 electrically connected to the third word line 330 and/or the sixth plug 390 electrically connected to the third bit line 350 through the shape change of the protrusion disposed at the end of the third word line 330 and/or the third bit line 350, and can further effectively reduce the resistance of the fifth plug 370 and/or the sixth plug 390. Furthermore, those skilled in the art will readily appreciate that the specific shape variations of the projections are not limited to those described above. For example, in forming the third word line 330 and/or the third bit line 350, the etching conditions may be adjusted such that the formed protruding portion is rounded to form an arc shape (not shown) or a hook shape (not shown), which is also beneficial to increase the contact area between the protruding portion and the plug.

In general, in a semiconductor memory device of the present invention, plugs are provided at opposite ends of a conductive line (bit line, word line, or the like) so as to entirely cover the ends of the conductive line. Thus, the plug can directly contact at least the top surface, the side wall and the end surface of the end part of the lead, the contact area between the plug and the lead is increased, and the contact resistance of the plug is reduced. Furthermore, the end of the conductive wire may be optionally provided with an additional protrusion to further increase the contact area between the plug and the conductive wire, wherein the protrusion may have various shapes (linear, L-shaped, arc-shaped or hook-shaped) or sizes. Therefore, the semiconductor memory device of the present invention contributes to improving the reliability of the electrical connection between the plug and the wire.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a plurality of active regions defined on the substrate;

a plurality of first conductive lines extending in parallel with each other along a first direction, the first conductive lines crossing the active region, wherein each of the first conductive lines has a first end and a second end opposite to each other; and

and the first plug is arranged on the first end of the first lead and is electrically connected with the first lead, wherein the first plug integrally wraps the first end of the first lead and directly contacts the top surface, the side wall and the end surface of the first end.

2. The semiconductor memory device according to claim 1, wherein a thickness of the sidewall of the first plug covering the first end is smaller than a thickness of the end face of the first plug covering the first end.

3. The semiconductor memory device according to claim 1, wherein the portion of the first plug covering the side wall and the end face at the first end has different depths in a direction perpendicular to the substrate.

4. The semiconductor memory device according to claim 1, wherein distances from different sidewalls of the first plug to different surfaces of the first end are different, and a depth in a direction perpendicular to the substrate is deeper in a portion where the distance from the first plug to the first end is larger.

5. The semiconductor memory device according to claim 1, wherein a bottom surface of the first plug is lower than a bottom surface of the first conductive line.

6. The semiconductor memory device according to claim 1, further comprising:

a plurality of second conductive lines extending in parallel with each other along a first direction and crossing the active region, wherein each of the second conductive lines is alternately arranged in sequence with each of the first conductive lines in a second direction perpendicular to the first direction, and each of the second conductive lines has opposite first and second ends; and

and the second plug is arranged on the second end of the second lead and electrically connected with the second lead, wherein the second plug integrally covers the second end of the second lead.

7. The semiconductor memory device according to claim 6, wherein the first end of the first conductive line and the first end of the second conductive line are offset from each other in the second direction.

8. The semiconductor memory device according to claim 1, wherein the first plugs comprise a plurality of first plugs, the first plugs being alternately disposed on the first ends of the first conductive lines and aligned with each other.

9. The semiconductor memory device according to claim 1, wherein the first end of each of the first conductive lines includes a first protrusion, and the first protrusions extend in a third direction.

10. The semiconductor memory device according to claim 9, wherein the second end of each of the first conductive lines includes a second protrusion extending in an opposite direction with respect to the third direction.

11. The semiconductor memory device according to claim 10, wherein each of the first protruding portions and each of the second protruding portions are linear or L-shaped.

12. The semiconductor memory device according to claim 9, wherein the first plug further wraps the first protrusion on the first end of the first conductive line.

13. The semiconductor memory device according to claim 12, wherein the first plug entirely covers an end face of the first protrusion.

14. The semiconductor memory device according to claim 1, wherein the first conductive line is provided in the substrate.

15. The semiconductor memory device of claim 14 wherein said substrate further comprises a shallow trench isolation surrounding said active region, wherein said first end of said first conductive line is disposed within said shallow trench isolation.

16. The semiconductor memory device according to claim 1, wherein the first conductive line is provided over the substrate.

17. The semiconductor memory device of claim 16, wherein the substrate further comprises a shallow trench isolation surrounding the active region, wherein the first end of the first conductive line is disposed on the shallow trench isolation.

18. The semiconductor memory device according to claim 1, further comprising:

a plurality of third conductive lines extending in a first direction in parallel with each other, wherein the third conductive lines are disposed at one side of the first conductive lines, and each of the third conductive lines has opposite first and second ends; and

19. The semiconductor memory device according to claim 18, wherein the third plug covers both of the opposite sidewalls and a top surface of the third conductive line.

20. The semiconductor memory device according to claim 1, further comprising:

the first insulating layer covers the active region and the first conducting wire, the first plug is arranged in the first insulating layer, and the top surface of the first plug is flush with the top surface of the first insulating layer.