CN113437071B

CN113437071B - Semiconductor memory device and manufacturing process thereof

Info

Publication number: CN113437071B
Application number: CN202110704388.3A
Authority: CN
Inventors: 颜逸飞; 赖惠先
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2023-06-09
Anticipated expiration: 2041-06-24
Also published as: CN116801633A; CN113437071A

Abstract

The present disclosure discloses a semiconductor memory device and a process for fabricating the same, including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate and further includes a first active region and a second active region. The first active region includes a plurality of active region units parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region surrounding all the active region units. Shallow trench isolation is provided in the substrate surrounding the active structure. The word lines are disposed within the substrate and are interleaved with the active area cells. The word lines include first word lines arranged at a first pitch and second word lines arranged at a second pitch, wherein the second pitch is greater than the first pitch. Therefore, the processing space of the bit line contact arranged on the outer side can be improved, and the word line and the bit line can be prevented from being directly conducted.

Description

Semiconductor memory device and manufacturing process thereof

Technical Field

The present disclosure relates to a semiconductor memory device and a manufacturing process thereof, and more particularly, to a semiconductor memory device including an active structure and a shallow trench isolation and a manufacturing process thereof.

Background

With the miniaturization of semiconductor devices and the complexity of integrated circuits, the size of devices is continuously reduced and the structure is continuously changed, so maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In the semiconductor manufacturing process, a plurality of active regions are defined on a substrate as a basis, and then required components are formed on the active regions. Generally, the active regions are formed with a plurality of patterns on the substrate by using photolithography and etching processes, but under the requirement of shrinking the size, the width of the active regions is gradually reduced, and the space between the active regions is also gradually reduced, so that the manufacturing process of the active regions faces many limitations and challenges, which cannot meet the product requirements.

Disclosure of Invention

One of the objectives of the present disclosure is to provide a semiconductor memory device having a relatively large pitch between an outer word line and an adjacent word line, and a relatively small pitch between an inner word line and an adjacent word line, so as to improve a process space of a bit line contact plug disposed on an outer side, and prevent the word line and the bit line from being directly connected. With this arrangement, the semiconductor memory device of the present disclosure can achieve a more optimized device performance.

In order to achieve the above object, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate, and the active structure further includes a first active region and a second active region. The first active region includes a plurality of active region units parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region surrounding all of the active region units. The shallow trench isolation is disposed in the substrate surrounding the active structure. The word lines are disposed within the substrate, extend in a second direction and are interleaved with the active area cells, wherein the second direction intersects and is not perpendicular to the first direction. The word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged at a first interval along a third direction perpendicular to the second direction, and the second word lines are sequentially arranged at a second interval along the third direction, wherein the second interval is larger than the first interval.

In order to achieve the above object, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate, and the active structure further includes a first active region and a second active region. The first active region includes a plurality of active region units parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region, surrounding all of the active region units. The shallow trench isolation is disposed in the substrate surrounding the active structure. The word lines are disposed within the substrate, extend in a second direction and are interleaved with the active area cells, wherein the second direction intersects and is not perpendicular to the first direction. The word lines comprise a plurality of first word lines and at least one second word line, one end of part of the active area units is directly contacted with the second word line, and the other end is directly contacted with the second active area.

In order to achieve the above object, one embodiment of the present disclosure provides a process for manufacturing a semiconductor memory device, which includes the following steps. First, a substrate is provided, and an active structure is formed in the substrate, wherein the active structure further comprises a first active region and a second active region. The first active region includes a plurality of active region units parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region, surrounding all of the active region units. A shallow trench isolation is then formed in the substrate surrounding the active structure. Then, a plurality of word lines are formed within the substrate, the word lines extending in a second direction and being interleaved with the active area cells, the second direction intersecting and not perpendicular to the first direction. The word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged at a first interval along a third direction perpendicular to the second direction, and the second word lines are sequentially arranged at a second interval along the third direction, wherein the second interval is larger than the first interval.

Drawings

FIGS. 1 to 7 are schematic views illustrating a process for fabricating a semiconductor memory device according to a preferred embodiment of the present disclosure; wherein the method comprises the steps of

FIG. 1 is a schematic top view of a semiconductor memory device of the present disclosure after forming active structures and word lines;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic top view of a semiconductor memory device of the present disclosure after forming contact openings;

FIG. 4 is a schematic cross-sectional view of FIG. 3 along line A-A';

FIG. 5 is a schematic top view of a semiconductor memory device of the present disclosure after forming bit lines and contacts;

FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 5; and

fig. 7 is a schematic cross-sectional view of fig. 5 along the line B-B'.

Wherein reference numerals are as follows:

300. semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell

110. Substrate and method for manufacturing the same

112. Shallow trench

120. Shallow trench isolation

130. Active structure

131. A first active region

131a, 131b, 131c, 131d active area unit

133. Second active region

133a first side edge

133b second side

140. Buried gate structure

140a first word line

140b second word line

141. Ditch groove

142. Dielectric layer

143. Gate dielectric layer

144. Gate electrode

145. Cover layer

150. Insulating layer

155. Contact opening

155a first contact opening

155b second contact openings

160. Bit line

161. Semiconductor layer

162. Barrier layer

163. Conductive layer

164. Cover layer

170. Contact point

170a first contact

170b second contact

180. 190 third contact

D1 First direction

D2 Second direction

D3 Third direction of

Length of L1, L2, L3, L4

Pore size and width of O1 and O2

P1, P2, P3 pitch

T1 width

W width

Detailed Description

The following description sets forth several preferred embodiments of the present disclosure in order to provide a further understanding of the present disclosure to those of ordinary skill in the art to which the present disclosure pertains, and in conjunction with the accompanying drawings, details of the construction and the efficacy of the present disclosure are set forth. Those of skill in the art will be able to replace, reorganize, and mix features in several different embodiments to accomplish other embodiments without departing from the spirit of the present disclosure with reference to the following exemplary embodiments.

Referring to fig. 1 to 7, a process of manufacturing a semiconductor memory device 300 according to a preferred embodiment of the disclosure is shown, wherein fig. 1, 3 and 5 are schematic top views of the semiconductor memory device 300 at different formation stages, and fig. 2, 4, 6 and 7 are schematic cross-sectional views of the semiconductor memory device 300 at different formation stages. The semiconductor memory device 300 includes a substrate 110, such as a silicon base, a silicon-containing base (e.g., siC, siGe) or a silicon-on-insulator (SOI) base, at least one shallow trench isolation (shallow trench isolation, STI) 120 is disposed in the substrate 110 to define an active structure (active structure) 130 in the substrate 110, i.e., the shallow trench isolation 120 is disposed around the active structure 130. Wherein the active structure 130 further includes a first active region 131 disposed in one region (e.g., a memory region having a relatively high device integration), and a second active region 133 disposed in another region (e.g., a peripheral region having a relatively low device integration). Preferably, the other region (e.g., the peripheral region) is disposed outside the region (e.g., the storage region), such that the second active region 133 can be disposed around the outside of the first active region 131, as shown in fig. 1, but not limited thereto.

Referring to fig. 1 and 2, the first active region 131 includes a plurality of

active region units

131a, 131b, 131c, 131D extending parallel to each other and spaced apart from each other along a first direction D1, and being disposed alternately with each other, wherein the first direction D1 is, for example, intersecting and not perpendicular to a y-direction (e.g., the second direction D2) or an x-direction (e.g., the third direction D3). In an embodiment, each of the active area units 131a has the same length L1 and the same pitch P1 in the first direction D1, and is sequentially arranged in a plurality of rows along the first direction D1, so that a specific arrangement can be shown as a whole, such as the array arrangement (array arrangement) shown in fig. 1, but is not limited thereto. The

active area units

131b, 131c, 131D have lengths different from the length L1 in the first direction D1, for example, the lengths L2, L3, L4 shown in fig. 1, where the length L4 may be smaller than the lengths L1, L2, L3, and the length L3 may be greater than the length L2, and the length L2 may be greater than the length L1 (L3 > L2 > L1 > L4), but not limited thereto. In the first direction D1, the

active area units

131a, 131b, 131c, 131D are sequentially arranged in a plurality of rows along the first direction D1 at the same pitch P1, and the

active area units

131b, 131c, 131D are sequentially arranged outside all the active area units 131a at the same pitch P1, for example, left, lower, right, and upper sides (not shown) of all the active area units 131a, but may be arranged in a specific arrangement as a whole, such as the array arrangement (array arrangement) shown in fig. 1, but is not limited thereto.

In an embodiment, the first active region 131 may be formed by, but not limited to, a patterning process described below. For example, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a plurality of patterns for defining a plurality of

active area units

131a, 131b, 131c, 131d of the first active area 131 and exposing a portion of the substrate 110, an etching process is performed by using the mask layer, the portion of the substrate 110 is removed to form at least one shallow trench 112, and then an insulating material (not shown) such as silicon oxide, silicon nitride or silicon oxynitride is filled in the shallow trench 112, so as to form a shallow trench isolation 120 with a top cut Ji Chende on the surface, and define the first active area 131, as shown in fig. 1 and 2. In one embodiment, the first active region 131 may be formed by a self-aligned double patterning (self-aligned double patterning, SADP) process or a self-aligned reverse patterning (self-aligned reverse patterning, SARP) process, but is not limited thereto.

Referring to fig. 1 again, the second active region 133 is disposed around the outside of the first active region 131. In this embodiment, the details of the second active region 133 include at least two first sides 133a extending along the second direction D2 and at least one second side 133b extending along the third direction D3, where each of the first sides 133a is opposite to each other and adjacent to each other and sequentially arranged with respect to the second sides 133b, so that the second active region 133 may entirely take a rectangular frame shape (not shown) and directly contact a portion of the

active region units

131b, 131c, 131D. That is, when the second active region 133 is disposed, a portion of the

active region units

131b, 131c, 131d may be further connected to the first side 133a and/or the second side 133b of the second active region 133, and another portion of the active region units 131a may not be connected to the first side 133a and/or the second side 133b of the second active region 133 but be disposed separately therefrom, as shown in fig. 1. In addition, the first and

second sides

133a and 133b may have the same width T1, and the width T1 thereof may preferably be greater than the width W of each of the

active region units

131a, 131b, 131c, 131d, but is not limited thereto. With this arrangement, the second active region 133 can be more uniformly subjected to the stress from the

active region units

131b, 131c, 131d and the shallow trench isolation 120, so as to obtain a more stable structure. However, in other embodiments (not shown), the second active region 133 may be selected not to contact any of the

active region units

131a, 131b, 131c, 131d at all according to the actual product requirement, or the width T1 of the first side 133a and the second side 133b may be selected to be equal to or smaller than the width W of the active region unit 131 a. It should be understood by those skilled in the art that the specific number of the first side or the second side may be adjusted according to the actual requirement, or may further include other sides, so that the second active region may entirely take on other shapes, not limited to the rectangular frame shape described above.

Note that in this embodiment, the second active region 133 may be formed by the patterning process of the substrate 110, and may be optionally performed together with the patterning process of the first active region 131. That is, in this embodiment, the patterns of the first active region 131 and the second active region 133 may be defined simultaneously or separately by using the same or different mask layers, and then the substrate 110 is etched and filled with the insulating material. Here, the first active region 131 and the second active region 133 may include the same material (i.e., the material of the substrate 110), and the first side 133a, the second side 133b, and the

active region units

131b, 131c, and 131d connected to the second active region 133 may be integrally formed, as shown in fig. 1. In this case, the

active region units

131b, 131c, 131d of the first active region 131 connected to the first side 133a and the second side 133b of the second active region 133 can be regarded as an extension portion extending inward of the first side 133a and the second side 133b of the second active region 133, so that the second active region 133 can have a relatively stable and reinforced structure to protect the first active region 131, particularly the active region unit 131a, disposed inside thereof from structural collapse or damage of the active region unit 131 a. However, it should be understood by those skilled in the art that the formation of the second active region is not limited to the foregoing fabrication process, and may be performed by other fabrication processes, for example, may be performed separately from the fabrication process of the first active region. For example, in another embodiment, the second active region may be formed by patterning the substrate before the first active region, and then the first active region is formed by an epitaxial growth process (epitaxial growth process, not shown), where the top surfaces of the second active region and the first active region may not be coplanar (not shown); alternatively, in another embodiment, the fabrication process of the second active region may be performed after the fabrication process of the first active region, the first active region is formed by using the patterning fabrication process of the substrate, and then the second active region (e.g. comprising polysilicon, a dielectric material, etc. different from the substrate) is formed by using a deposition process, where the second active region and the first active region may comprise different materials.

Next, as shown in fig. 1 and 2, a plurality of gate structures, preferably buried gate structures 140, are formed in the substrate 110. In this embodiment, a plurality of trenches 141 extending in the second direction D2 in parallel and spaced apart from each other are formed in the substrate 110. Then, a dielectric layer 142 covering the entire surface of each trench 141, a gate dielectric layer 143 covering the lower half surface of each trench 141, a gate 144 filling the lower half of each trench 141, and a cap layer 145 filling the upper half of each trench 141 are sequentially formed. Thus, the top surface of the cap layer 145 may be cut Ji Chende at the top surface of the substrate 110, as shown in fig. 2, so that the buried gate structure 140 in the substrate 110 may serve as a buried Word Line (WL) of the semiconductor memory device 300, wherein each word line is parallel to the first side of the second active region and is staggered with the

active region cells

131a, 131b, 131c, 131d to receive or transmit a voltage signal of each memory cell (not shown). It should be noted that each word line (i.e., the buried gate structure 140) is sequentially arranged along the third direction D3, and includes a plurality of first word lines 140a and a plurality of second word lines 140b, wherein the first word lines 140a are sequentially arranged along the third direction D3 at a first pitch P2, and the second word lines 140b are sequentially arranged along the third direction D3 at a second pitch P3 on two opposite outer sides of all the first word lines 140a, and the second pitch P3 is larger than the first pitch P2, as shown in fig. 1 and 2. In addition, it should be noted that the first word line 140a passes through the middle portion of the

active area cells

131a and 131d, and the second word line 140b passes through the middle portion of the active area cell 131c and directly contacts the end portion of the active area cell 131 b. In other words, a portion of the active region unit 131b contacts the second word line 140b at one end and contacts the first side 133a of the second active region 133 at the other end, as shown in fig. 1.

Next, as shown in fig. 3 (the insulating layer 150 is omitted) and fig. 4, an insulating layer 150 is formed on the top surface of the substrate 110, so as to entirely cover the substrate 110 and contact the buried gate structure 140 and the shallow trench isolation 120 in the substrate 110, wherein the insulating layer 150 includes, but is not limited to, a silicon oxide-nitride-oxide (ONO) structure. Then, an etching process is performed to remove a portion of the insulating layer 150 and a portion of the substrate 110 thereunder, thereby forming a plurality of contact openings 155 in the substrate 110. Each contact opening 155 is formed between two adjacent word lines (i.e., buried gate structures 140) and exposes a portion of the substrate 110. In detail, the contact opening 155 further includes at least one first contact opening 155a and at least one second contact opening 155b, wherein each first contact opening 155a is disposed on the active area unit 131a and between two adjacent first word lines 140a, and each second contact opening 155b is also disposed on the active area unit 131a but is located between the adjacent first word lines 140a and second word lines 140b, in other words, neither the first contact opening 155a nor the second contact opening 155b is disposed on the

active area units

131b, 131c, 131d that can be further connected to the second active area unit 133, as shown in fig. 3. Further, the first contact opening 155a has an aperture O1 in the first direction D1, and the second contact opening 155b has an aperture O2 in the first direction D1. It should be noted that, because the arrangement pitch P3 of the second word line 140b is larger, the aperture O2 of the second contact opening 155b may also be larger than the aperture O1 of the first contact opening 155a, as shown in fig. 3. In other words, the arrangement pitch P3 of the second word lines 140b may enable the second contact openings 155b to have a relatively large manufacturing space (process window).

Subsequently, at least one Bit Line (BL) 160 is formed on the substrate 110, as shown in fig. 5 to 7, a plurality of bit lines 160 are formed in this embodiment, and each bit line 160 extends parallel to each other and spaced apart from each other along the third direction D3 and is staggered with the word line (i.e. the buried gate structure 140) and the

active area units

131a, 131b, 131c, 131D. Each bit line 160 includes a semiconductor layer 161 (e.g., including polysilicon), a barrier layer 162 (e.g., including titanium and/or titanium nitride), a conductive layer 163 (e.g., including low-resistance metal such as tungsten, aluminum, or copper), and a cap layer 164 (e.g., including silicon oxide, silicon nitride, or silicon oxynitride) sequentially stacked on the insulating layer 150, but is not limited thereto. Wherein a portion of the bit line 160 overlaps the contact opening 155 such that a portion of the semiconductor layer 162 fills the contact opening 155 and forms a contact 170, thereby forming a Bit Line Contact (BLC). In this arrangement, the bit line contact plug (i.e., contact 170) may be integrally formed with the bit line 160 (as shown in fig. 7) and directly contact a portion of the active area cell 131a, and may be electrically connected to a transistor element (not shown) within the substrate 110 to receive or transmit the voltage signal of each of the memory cells. It should be noted that, in view of the clear presentation of the bit line 160, the contact 170 is not directly depicted in fig. 5, but the specific location thereof may be referred to the contact opening 155 shown in fig. 3. In detail, the contact 170 further includes at least one first contact 170a and at least one second contact 170b, wherein the first contact 170a is disposed on the active area unit 131a between two adjacent first word lines 140a, and the second contact 170b is also disposed on the active area unit 131a between two adjacent first word lines 140a and second word lines 140 b. That is, none of the contacts 170 (including the first contact 170a and the second contact 170 b) is disposed on and in contact with the

active region units

131b, 131c, 131d that can be further connected to the second active region 133. Thus, the first contact 170a may have a relatively smaller width O1 in the first direction D1, and the second contact 170b may have a relatively larger width O2 due to the larger arrangement pitch P3 of the second word line 140b, as shown in fig. 6 and 7.

Then, as further shown in fig. 5, a plurality of

third contacts

180, 190 are formed on the bit line 160 and the word line (i.e., the buried gate structure 140), respectively. The third contacts 180 are alternately disposed at two ends of the bit line 160 (not shown, for example, refer to the left and right ends of the bit line 160 shown in fig. 5) and electrically connected thereto. For example, the third contact 180 is disposed at the right end of the odd-order bit lines 160 and at the left end of the even-order bit lines 160, as shown in fig. 5, but not limited thereto. Alternatively, the third contact 190 may have a similar arrangement to the third contact 180, for example, the third contact 190 may be disposed at a lower end of the odd-order word lines (i.e., the buried gate structure 140) and at an upper end (not shown) of the even-order word lines (i.e., the buried gate structure 140), but is not limited thereto. With this arrangement, the

third contacts

180, 190 can be made to maintain sufficient process space and electrically connect through the ends of the bit line 160 and the word line (i.e., buried gate structure 140), respectively.

Thus, the semiconductor memory device 300 of the preferred embodiment of the present disclosure is completed. The semiconductor memory device 300 has a second active region 133 circumferentially disposed outside the first active region 131, such that a portion of the

active region units

131b, 131c, 131d can be further connected to the first side 133a and/or the second side 133b of the second active region 133, thereby dispersing the stress influence from the shallow trench isolation 120 to obtain a more stable structure. In addition, the semiconductor memory device 300 has word lines (i.e., buried gate structures 140) arranged at different pitches, with a relatively large pitch P3 between the outer word line 140b and the adjacent word line 140a, and a relatively small pitch P2 between the inner word line 140a and the adjacent word line 140 a. Accordingly, the contacts 170a disposed between the adjacent word lines 140a have a relatively small width O1, and the contacts 170b disposed between the

adjacent word lines

140a, 140b have a relatively large width O2, so that the process space of the bit line contact plug (i.e., the contacts 170 a) disposed on the outer side can be improved, and the word line and the bit line can be prevented from being directly conducted. With this arrangement, the semiconductor memory device of the present disclosure can achieve a more optimized device performance.

However, it should be readily understood by those skilled in the art that the semiconductor memory device and the manufacturing process thereof of the present disclosure may have other aspects or may be achieved by other means, and are not limited to the foregoing. For example, in one embodiment, the etching conditions may be adjusted to round the corners of the second active region during the patterning process, or a plurality of openings may be formed on the second active region to further distribute stress, but not limited to this.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, comprising:

a substrate;

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region units parallel to each other and extending along a first direction; and

the second active area is arranged outside the first active area and surrounds all the active area units;

shallow trench isolation arranged in the substrate and surrounding the active structure;

the word lines are arranged in the substrate, extend in a second direction and are staggered with the active area units, the second direction is intersected and is not perpendicular to the first direction, the word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged at a first interval along a third direction perpendicular to the second direction, the second word lines are arranged at a second interval along the third direction, wherein the second interval is larger than the first interval, and the second interval is the interval between the first word lines and the second word lines;

at least one first contact arranged on the active area unit and between two adjacent first word lines; and

and at least one second contact arranged on the active area unit and between the adjacent first word line and the second word line, wherein the width of the second contact in the first direction is larger than that of the first contact in the first direction.

2. The semiconductor memory device according to claim 1, wherein a portion of the active region unit is connected to the second active region, and the second contact does not contact the portion of the active region unit.

3. The semiconductor memory device according to claim 2, wherein the second word line directly contacts an end of the active region unit of the portion.

4. The semiconductor memory device according to claim 1, further comprising:

and the bit lines are arranged on the substrate and staggered with the word lines, extend in the third direction and are respectively connected with the first contact and the second contact.

5. The semiconductor memory device according to claim 4, wherein the bit line is integrally formed with the first contact and the second contact, respectively.

6. The semiconductor memory device according to claim 1, wherein the second active region includes a first side extending along the second direction and a second side extending along the third direction, and wherein the first side is parallel to the word line.

7. The semiconductor memory device according to claim 1, wherein one end of a part of the active region unit contacts the second word line and the other end contacts the second active region.

8. A process for manufacturing a semiconductor memory device, comprising:

providing a substrate;

forming an active structure in the substrate, the active structure comprising:

forming shallow trench isolation in the substrate surrounding the active structure;

forming a plurality of word lines in the substrate, wherein the word lines extend in a second direction and are staggered with the active area units, the second direction is intersected and is not perpendicular to the first direction, the word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged at a first pitch along a third direction perpendicular to the second direction, and the second word lines are arranged at a second pitch along the third direction, wherein the second pitch is larger than the first pitch, and the second pitch is the pitch between the first word lines and the second word lines; and

forming a plurality of contacts on the substrate, the contacts comprising:

9. The process of claim 8, wherein a portion of the active region units are connected to the second active region, and wherein the contacts do not contact the portion of the active region units.

10. The process of claim 9, wherein the second word line directly contacts an end of the active region unit of the portion.

11. The process for manufacturing a semiconductor memory device according to claim 8, further comprising:

forming a plurality of contact openings on the substrate, respectively located on the active region units; and

the contacts are formed in the contact openings, respectively.

12. The process for manufacturing a semiconductor memory device according to claim 11, further comprising:

a plurality of bit lines are formed on the substrate, the bit lines are staggered with the word lines, and the bit lines extend in the third direction and are respectively connected with the contacts.

13. The process of claim 8, wherein one end of a portion of the active region unit contacts the second word line and the other end contacts the second active region.