CN111916453B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN111916453B CN111916453B CN201910384266.3A CN201910384266A CN111916453B CN 111916453 B CN111916453 B CN 111916453B CN 201910384266 A CN201910384266 A CN 201910384266A CN 111916453 B CN111916453 B CN 111916453B
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- sidewall
- distance
- bit line
- forming
- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 77
- 238000000059 patterning Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a dielectric layer, a plurality of bit lines, a spacer and a contact window. The substrate has a plurality of active regions disposed parallel to each other. The dielectric layer is arranged on the substrate. The plurality of bit lines are disposed on the dielectric layer in parallel with each other. Each bit line partially overlaps the active region. Each bit line has first portions and second portions alternating with each other in an extending direction thereof, and a width of the first portions is smaller than a width of the second portions. The spacer is disposed on a sidewall of each bit line. The contact window is disposed between adjacent bit lines and adjacent to the first portion of at least one of the adjacent bit lines and passes through the dielectric layer to contact the active region.
Description
Technical Field
The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure capable of improving a resistance of a contact between adjacent bit lines and a method for fabricating the same.
Background
In the current process of forming the bit lines in the DRAM (dynamic random access memory), a contact window is formed between adjacent bit lines, which is electrically connected to the active region through the underlying dielectric layer, and the contact window is also electrically connected to the capacitor formed later.
As device dimensions continue to shrink, so does the spacing between adjacent devices. Therefore, when forming the contact between the adjacent bit lines, the size of the contact must be reduced, and the contact area with the active region is also reduced, which results in a decrease in the amount of current flowing through the contact during operation of the device, thereby affecting the device performance.
Disclosure of Invention
The invention provides a semiconductor structure, wherein a contact window between adjacent bit lines and an active region have a larger contact area.
The invention provides a manufacturing method of a semiconductor structure, which is used for manufacturing the semiconductor structure.
The semiconductor structure of the invention comprises a substrate, a dielectric layer, a plurality of bit lines, a spacer and a contact window. The substrate has a plurality of active regions disposed parallel to each other. The dielectric layer is arranged on the substrate. The plurality of bit lines are disposed on the dielectric layer in parallel with each other. Each bit line partially overlaps the active region. Each bit line has first portions and second portions alternating with each other in an extending direction thereof, and a width of the first portions is smaller than a width of the second portions. The spacer is disposed on a sidewall of each bit line. The contact window is disposed between adjacent bit lines and adjacent to the first portion of at least one of the adjacent bit lines and passes through the dielectric layer to contact the active region.
In an embodiment of the semiconductor structure of the present invention, from an upper view, a first distance is provided between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is, for example, not more than 5nm.
In an embodiment of the semiconductor structure of the present invention, from an upper view, a sidewall of a second side of the first portion opposite to the first side and a sidewall of the second side of the second portion have a second distance therebetween in a direction perpendicular to an extending direction of the bit line, and the second distance is, for example, not more than 5nm.
In an embodiment of the semiconductor structure of the present invention, from an upper view, a first distance is provided between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is, for example, not more than 35% of a width of the second portion.
In an embodiment of the semiconductor structure of the present invention, from an upper view, a sidewall of a second side of the first portion opposite to the first side and a sidewall of the second side of the second portion have a second distance therebetween in a direction perpendicular to an extending direction of the bit line, and the second distance is, for example, not more than 35% of a width of the second portion.
In an embodiment of the semiconductor structure of the present invention, the first distance is equal to the second distance, for example.
In one embodiment of the semiconductor structure of the present invention, the first portions of adjacent bit lines are staggered with respect to each other.
The manufacturing method of the semiconductor structure comprises the following steps. First, a dielectric layer is formed on a substrate, wherein the substrate has a plurality of active regions disposed parallel to each other. And forming a plurality of bit lines parallel to each other on the dielectric layer, wherein each bit line is partially overlapped with the active region, each bit line is provided with a first part and a second part which are mutually alternated in the extending direction, and the width of the first part is smaller than that of the second part. Then, a spacer is formed on the sidewall of each bit line. Then, a contact window is formed between adjacent bit lines, wherein the contact window is adjacent to the first portion of at least one of the adjacent bit lines and passes through the dielectric layer to contact the active region.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, from an upper view, a first distance is provided between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is, for example, not more than 5nm.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, from an upper view, a sidewall of a second side of the first portion opposite to the first side and a sidewall of the second side of the second portion have a second distance therebetween in a direction perpendicular to an extending direction of the bit line, and the second distance is, for example, not more than 5nm.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, from an upper view, a first distance is between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is, for example, not more than 35% of a width of the second portion.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, from an upper view, a sidewall of a second side of the first portion opposite to the first side and a sidewall of the second side of the second portion have a second distance therebetween in a direction perpendicular to an extending direction of the bit line, and the second distance is, for example, not more than 35% of a width of the second portion.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the first distance is equal to the second distance, for example.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming a bit line includes the following steps. First, a bit line material layer is formed on the dielectric layer. Then, a plurality of mask patterns are formed on the bit line material layer in parallel with each other. A patterned photoresist layer is then formed over the bit line material layer, wherein the patterned photoresist layer exposes a portion of each of the mask patterns. Then, an isotropic etching process is performed to remove a portion of the exposed mask pattern to reduce the width of the exposed mask pattern. The patterned photoresist layer is then removed. And then, taking the mask patterns as masks, performing an anisotropic etching process, and removing part of the bit line material layer. Thereafter, the photoresist pattern is removed.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the spacer includes the following steps. First, after forming the plurality of bit lines, a spacer material layer is conformally formed on the dielectric layer. And then, performing an anisotropic etching process to remove part of the spacer material layer.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming a contact includes the following steps. First, after forming the spacers, a dielectric material layer is formed on the dielectric layer to cover the bit lines. Then, a portion of the dielectric material layer is removed to expose top surfaces of the plurality of bit lines. Then, the dielectric material layer adjacent to the first portion and the dielectric layer below are removed to form an opening exposing a portion of the active region. And then, forming a conductive layer in the opening.
Drawings
Fig. 1A to 1F are schematic top views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.
Fig. 2A to 2F are schematic cross-sectional views shown along the line I-I' in fig. 1A to 1F.
[ symbolic description ]
100: substrate
102: active region
104: isolation structure
106. 120: dielectric layer
108: bit line material layer
110: hard mask material layer
112: mask pattern
112a, 116a: first part
112b, 116b: second part
114: patterning a photoresist layer
116: bit line
118: spacer wall
122: an opening
124: contact window
126: region(s)
D1, D2: distance of
W: width of (L)
Detailed Description
Fig. 1A to 1F are schematic top views of a manufacturing process of a semiconductor structure according to an embodiment of the invention. Fig. 2A to 2F are schematic cross-sectional views shown along the line I-I' in fig. 1A to 1F.
First, referring to fig. 1A and fig. 2A, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. The substrate 100 has an isolation structure 104 therein for defining a plurality of active regions 102. The arrangement of the active regions 102 is not limited to the arrangement shown in fig. 1A. The isolation structure 104 is, for example, a shallow trench isolation structure (shallow trench isolation, STI). In addition, various elements (e.g., gate structures, source regions, drain regions, etc.) are formed on the substrate 100 and in the substrate 100 to constitute a memory cell. However, the various elements described above are omitted from the figures for clarity of the drawing. Then, a dielectric layer 106 is formed on the substrate 100. The dielectric layer 106 is, for example, an oxide layer, and is formed by, for example, chemical vapor deposition. The dielectric layer 106 covers various elements on the substrate 100. In addition, an interconnect structure is formed in the dielectric layer 106. Also, the interconnect structures described above are omitted from the figures for clarity of the drawing.
Next, referring to fig. 1B and fig. 2B, a bit line material layer 108 is formed on the dielectric layer 106. The bit line material layer 108 is, for example, a polysilicon layer, but the invention is not limited thereto. In other embodiments, the bit line material layer 108 may be a composite layer of a polysilicon layer, a tungsten silicide layer and a silicon nitride layer, as required. In addition, a hard mask material layer 110 may be formed on the bit line material layer 108. The hard mask material layer 110 may be an oxide layer, a nitride layer or a stacked layer composed of an oxide layer and a nitride layer, but the present invention is not limited thereto. In other embodiments, the hard mask material layer 110 may be a single layer or a composite layer of other materials, as desired. Thereafter, a double patterning (double patterning) process may be performed to form a plurality of mask patterns 112 on the hard mask material layer 110. In other embodiments, a common single patterning process may be used instead of a double patterning process, as the case may be. The mask pattern 112 is, for example, an oxide layer.
Then, referring to fig. 1C and fig. 2C, a patterned photoresist layer 114 is formed on the hard mask material layer 110. The patterned photoresist layer 114 exposes portions of each mask pattern 112 corresponding to regions of smaller width in the bit lines to be formed later. In the present embodiment, the exposed areas of the patterned photoresist layer 114 are alternately arranged with each other, but the present invention is not limited thereto. In other embodiments, the exposed area of the patterned photoresist layer 114 may be adjusted depending on the actual layout requirements.
Next, referring to fig. 1D and fig. 2D, an isotropic etching process is performed to remove a portion of the exposed mask pattern 112, so as to reduce the width of the exposed mask pattern 112. The isotropic etching process is, for example, a wet etching process using buffered hydrofluoric acid (buffered hydrofluoric acid, BHF). In this way, the mask pattern 112 has a first portion 112a with a smaller width and a second portion 112b with a larger width, and the first portion 112a corresponds to a region with a smaller width in the bit line to be formed later. The mask pattern 112 serves as a mask when patterning the bit line material layer 108 into a plurality of bit lines. Since the mask pattern 112 has the first portion 112a with smaller width and the second portion 112b with larger width, the bit line formed later may also have the portion with smaller width and the portion with larger width. This will be further described below.
Then, referring to fig. 1E and fig. 2E, the patterned photoresist layer 114 is removed. Then, an anisotropic etching process is performed using the mask pattern 112 as an etching mask, and a portion of the hard mask material layer 110 is removed to form a hard mask pattern (not shown). Then, an anisotropic etching process is performed using the hard mask pattern as an etching mask, and a portion of the bit line material layer 108 is removed to form a bit line 116 having a first portion 116a with a smaller width and a second portion 116b with a larger width.
In the present embodiment, the width of the first portion 112a is adjusted by controlling the removal amount of the mask pattern 112 in the steps described in fig. 1D and 2D, so as to obtain the desired width of the first portion 116a of the bit line 116. As shown in fig. 1E, from the top view, in a direction perpendicular to the extending direction of the bit line 116, a distance D1 is provided between a sidewall of one side of the first portion 116a and a sidewall of the second portion 116b on the same side, and a distance D2 is provided between a sidewall of the first portion 116a and a sidewall of the second portion 116b on the opposite side. In one embodiment, distance D1 is no more than 5nm and distance D2 is no more than 5nm. In another embodiment, distance D1 does not exceed 35% of the width W of second portion 116b, and distance D2 does not exceed 35% of the width W of second portion 116 b. In addition, in the present embodiment, the distance D1 is equal to the distance D2, but the present invention is not limited thereto. In other embodiments, the distance D1 and the distance D2 may be different from each other depending on the actual layout requirements.
Next, referring to fig. 1F and fig. 2F, spacers 118 are formed on sidewalls of the bit lines 116. The spacers 118 are, for example, nitride layers. The spacer 118 is formed, for example, by conformally forming a spacer material layer on the dielectric layer 106 and then performing an anisotropic etching process to remove a portion of the spacer material layer. Then, a dielectric material layer is formed on the dielectric layer 106 to cover the bit lines 116 and the spacers 118. Thereafter, a Chemical Mechanical Polishing (CMP) process is performed, for example, to remove a portion of the dielectric material layer to expose the top surfaces of the bit lines 116 and form a dielectric layer 120 between the bit lines 116. Next, the dielectric layer 120 adjacent to the first portion 116a and the underlying dielectric layer 106 are removed to form an opening 122 exposing a portion of the active region 102. Then, the opening 122 is filled with a conductive layer to form a contact window 124 in the dielectric layer 120 and the dielectric layer 106, which contacts the active region 102. The contact 124 is used to electrically connect a device (e.g., a capacitor) formed later to the active region 102.
In the present embodiment, the bit lines 116 have a first portion 116a with a smaller width and a second portion 116b with a larger width, and the contact 124 between the bit lines 116 is disposed adjacent to the first portion 116 a. In this way, the contact 124 may have a larger size and lower resistance than a typical bit line having a uniform width, and a larger contact area between the contact 124 and the active region 102 may increase the amount of current flowing through the contact 124 and the active region 102 during operation of the device, thereby improving the electrical performance of the device. As shown by region 126 in fig. 1F, the contact 124 increases in size and contact area with the active region 102 compared to a bit line having a generally uniform width.
Further, in the present embodiment, the distances D1, D2 between the sidewalls of the first portion 116a and the sidewalls of the second portion 116b are not more than 5nm, or the distances D1, D2 are not more than 35% of the width W of the second portion 116 b. In this way, when the width of the bit line 116 is reduced to increase the size of the contact 124, the resistance of the bit line 116 itself can be maintained at a desired level, and the electrical performance of the device is not affected by an excessive increase in resistance due to an excessive reduction in the width of the bit line 116.
Claims (8)
1. A semiconductor structure, comprising:
a substrate having a plurality of active regions disposed parallel to each other;
a dielectric layer disposed on the substrate;
a plurality of bit lines disposed on the dielectric layer in parallel with each other, each bit line partially overlapping the active region, wherein each bit line has first portions and second portions alternating with each other in an extending direction thereof, and a width of the first portion is smaller than a width of the second portion;
a spacer disposed on a sidewall of each bit line; and
a contact window disposed between adjacent bit lines and adjacent to the first portion of at least one of the adjacent bit lines and through the dielectric layer to contact the active region,
wherein from a top view perspective, there is a first distance between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is not more than 35% of a width of the second portion, and there is a second distance between a sidewall of a second side of the first portion opposite the first side and a sidewall of the second side of the second portion, and the second distance is not more than 35% of a width of the second portion.
2. The semiconductor structure of claim 1, wherein, from a top view perspective, a first distance is provided between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion, and the first distance is no more than 5nm, and a second distance is provided between a sidewall of a second side of the first portion opposite the first side and a sidewall of the second side of the second portion, and the second distance is no more than 5nm, in a direction perpendicular to an extending direction of the bit line.
3. The semiconductor structure of claim 1, wherein the first portions of adjacent bit lines are staggered with respect to each other.
4. A method of fabricating a semiconductor structure, comprising:
forming a dielectric layer on a substrate, wherein the substrate is provided with a plurality of active areas which are arranged in parallel;
forming a plurality of bit lines parallel to each other on the dielectric layer, wherein each bit line is partially overlapped with the active region, each bit line is provided with a first part and a second part which are mutually alternated in the extending direction, and the width of the first part is smaller than that of the second part;
forming a spacer on a sidewall of each bit line; and
forming contact windows between adjacent bit lines, wherein the contact windows are adjacent to the first portion of at least one of the adjacent bit lines and pass through the dielectric layer to contact the active region,
wherein from a top view perspective, there is a first distance between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion in a direction perpendicular to an extending direction of the bit line, and the first distance is not more than 35% of a width of the second portion, and there is a second distance between a sidewall of a second side of the first portion opposite the first side and a sidewall of the second side of the second portion, and the second distance is not more than 35% of a width of the second portion.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein, from a top view perspective, a first distance is provided between a sidewall of a first side of the first portion and a sidewall of the first side of the second portion, and the first distance is not more than 5nm, and a second distance is provided between a sidewall of a second side of the first portion opposite to the first side and a sidewall of the second side of the second portion, and the second distance is not more than 5nm, in a direction perpendicular to an extending direction of the bit line.
6. The method of manufacturing a semiconductor structure of claim 4, wherein the bit line forming method comprises:
forming a bit line material layer on the dielectric layer;
forming a plurality of mask patterns parallel to each other on the bit line material layer;
forming a patterned photoresist layer over the bit line material layer, wherein the patterned photoresist layer exposes a portion of each of the mask patterns;
performing an isotropic etching process to remove a portion of the exposed mask pattern to reduce the width of the exposed mask pattern;
removing the patterned photoresist layer;
taking the mask patterns as masks, performing an anisotropic etching process, and removing part of the bit line material layer; and
and removing the plurality of mask patterns.
7. The method of claim 4, wherein the forming the spacers comprises:
conformally forming a spacer material layer on the dielectric layer after forming the plurality of bit lines; and
and performing an anisotropic etching process to remove a portion of the spacer material layer.
8. The method of manufacturing a semiconductor structure according to claim 4, wherein the method of forming the contact window comprises:
forming a dielectric material layer on the dielectric layer after forming the spacers to cover the bit lines;
removing a portion of the dielectric material layer to expose top surfaces of the plurality of bit lines;
removing the dielectric material layer adjacent to the first portion and the dielectric layer below to form an opening exposing a portion of the active region; and
and forming a conductive layer in the opening.
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| CN201910384266.3A CN111916453B (en) | 2019-05-09 | 2019-05-09 | Semiconductor structure and manufacturing method thereof |
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| CN201910384266.3A CN111916453B (en) | 2019-05-09 | 2019-05-09 | Semiconductor structure and manufacturing method thereof |
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| CN111916453B true CN111916453B (en) | 2023-11-14 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112713A (en) * | 2013-04-22 | 2014-10-22 | 华邦电子股份有限公司 | Memory structure and manufacturing method thereof, and semiconductor element |
| CN108878366A (en) * | 2017-05-15 | 2018-11-23 | 长鑫存储技术有限公司 | Memory and forming method thereof, semiconductor devices |
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| KR100555564B1 (en) * | 2004-03-31 | 2006-03-03 | 삼성전자주식회사 | Semiconductor device including square type storage node and manufacturing method therefor |
| KR100577542B1 (en) * | 2005-03-11 | 2006-05-10 | 삼성전자주식회사 | Method of fabricating semiconductor devices having buried contact plugs |
| KR102001417B1 (en) * | 2012-10-23 | 2019-07-19 | 삼성전자주식회사 | Semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112713A (en) * | 2013-04-22 | 2014-10-22 | 华邦电子股份有限公司 | Memory structure and manufacturing method thereof, and semiconductor element |
| CN108878366A (en) * | 2017-05-15 | 2018-11-23 | 长鑫存储技术有限公司 | Memory and forming method thereof, semiconductor devices |
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