TWI722418B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer, a plurality of bit lines, a spacer and a contact. The substrate has a plurality of active areas parallel with each other. The dielectric layer is disposed on the substrate. The plurality of bit lines are disposed on the substrate and parallel with each other. Each of the bit lines partially overlaps the active areas. Each of the bit lines has first portions and second portions alternated with each other in the extending direction of the bit line. The widths of the first portions are less than the widths of the second portions. The spacer is disposed on the sidewalls of the bit lines. The contact is disposed between the adjacent bit lines and adjacent to the first portion of the at least one of the adjacent bit lines, and passes through the dielectric layer to contact the active area.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure and a manufacturing method thereof that can improve the resistance of a contact window between adjacent bit lines.

In the current process of dynamic random access memory (DRAM), after the bit lines are formed, a dielectric layer is formed between adjacent bit lines to pass through the underlying dielectric layer to be electrically connected to the active region. The contact window is electrically connected, and the contact window will also be electrically connected with the capacitor formed later.

As the size of components continues to shrink, the spacing between adjacent components also shrinks. Therefore, when forming a contact window between adjacent bit lines, the size of the contact window must be reduced, and the contact area between the contact window and the active area is also reduced, resulting in a decrease in the amount of current flowing through the contact window when operating the element. And affect component performance.

The present invention provides a semiconductor structure in which a contact window between adjacent bit lines and an active region have a larger contact area.

The present invention provides a method for manufacturing a semiconductor structure, which is used for manufacturing the above-mentioned semiconductor structure.

The semiconductor structure of the present invention includes a substrate, a dielectric layer, a plurality of bit lines, spacers and contact windows. The substrate has a plurality of active regions arranged parallel to each other. The dielectric layer is disposed on the substrate. The plurality of bit lines are arranged on the dielectric layer in parallel with each other. Each of the bit lines partially overlaps the active area. Each bit line has a first part and a second part alternating with each other in the extending direction, and the width of the first part is smaller than the width of the second part. The spacer is arranged on the side wall of each bit line. The contact window is disposed between adjacent bit lines and is adjacent to the first portion of at least one of the adjacent bit lines, and passes through the dielectric layer to communicate with the active Zone contact.

In an embodiment of the semiconductor structure of the present invention, from a top perspective, in a direction perpendicular to the extension direction of the bit line, the sidewalls of the first side of the first part are opposite to the sidewalls of the second part. There is a first distance between the side walls of the first side, and the first distance does not exceed 5 nm, for example.

In an embodiment of the semiconductor structure of the present invention, from a top perspective, in a direction perpendicular to the extension direction of the bit line, a second side of the first portion opposite to the first side There is a second distance between the side wall of the second part and the side wall of the second side of the second part, and the second distance does not exceed 5 nm, for example.

In an embodiment of the semiconductor structure of the present invention, from a top perspective, in a direction perpendicular to the extension direction of the bit line, the sidewalls of the first side of the first part are opposite to the sidewalls of the second part. There is a first distance between the side walls of the first side, and the first distance does not exceed 35% of the width of the second part, for example.

In an embodiment of the semiconductor structure of the present invention, from a top perspective, in a direction perpendicular to the extension direction of the bit line, a second side of the first portion opposite to the first side There is a second distance between the side wall of and the side wall of the second side of the second part, and the second distance does not exceed 35% of the width of the second part, for example.

In an embodiment of the semiconductor structure of the present invention, the first distance and the second distance are, for example, equal.

In an embodiment of the semiconductor structure of the present invention, the first portions of adjacent bit lines are staggered.

The manufacturing method of the semiconductor structure of the present invention includes the following steps. First, a dielectric layer is formed on a substrate, wherein the substrate has a plurality of active regions arranged parallel to each other. Next, a plurality of bit lines parallel to each other are formed on the dielectric layer, each of the bit lines partially overlaps the active region, and each of the bit lines has alternating directions in the extending direction. The first part and the second part of, and the width of the first part is smaller than the width of the second part. Then, a spacer is formed on the side wall of each bit line. Afterwards, a contact window is formed between adjacent bit lines, wherein the contact window is adjacent to the first portion of at least one of the adjacent bit lines and passes through the dielectric layer And contact with the active area.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, from a top view, in a direction perpendicular to the extension direction of the bit line, the sidewall of the first side of the first portion is connected to the There is a first distance between the side walls of the first side of the second part, and the first distance does not exceed 5 nm, for example.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, from a top view, in a direction perpendicular to the extension direction of the bit line, the first part of the first part is opposite to the first side There is a second distance between the side wall on the second side and the side wall on the second side of the second part, and the second distance does not exceed 5 nm, for example.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, from a top view, in a direction perpendicular to the extension direction of the bit line, the sidewall of the first side of the first portion is connected to the There is a first distance between the side walls of the first side of the second part, and the first distance does not exceed 35% of the width of the second part, for example.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, from a top view, in a direction perpendicular to the extension direction of the bit line, the first part of the first part is opposite to the first side There is a second distance between the side wall of the second side and the side wall of the second side of the second part, and the second distance does not exceed 35% of the width of the second part, for example.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, the first distance and the second distance are, for example, equal.

In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the bit line includes the following steps. First, a bit line material layer is formed on the dielectric layer. Then, a plurality of mask patterns parallel to each other are formed on the bit line material layer. Then, a patterned photoresist layer is formed on the bit line material layer, wherein the patterned photoresist layer exposes a part of each of the mask patterns. Then, an isotropic etching process is performed to remove a part of the exposed mask pattern to reduce the width of the exposed mask pattern. Then, the patterned photoresist layer is removed. Then, using the multiple mask patterns as a mask, an anisotropic etching process is performed to remove part of the bit line material layer. After that, the photoresist pattern is removed.

In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the spacer includes the following steps. First, after forming the plurality of bit lines, a spacer material layer is conformally formed on the dielectric layer. Afterwards, an anisotropic etching process is performed to remove part of the spacer material layer.

In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the contact window includes the following steps. First, after forming the spacers, a dielectric material layer is formed on the dielectric layer to cover the plurality of bit lines. Then, a part of the dielectric material layer is removed to expose the top surface of the plurality of bit lines. Then, the dielectric material layer adjacent to the first portion and the dielectric layer below are removed to form an opening exposing part of the active region. Afterwards, a conductive layer is formed in the opening.

1A to 1F are schematic top views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views along the line I-I' in FIGS. 1A to 1F.

First, please refer to FIG. 1A and FIG. 2A at the same time to provide a substrate 100. The substrate 100 is, for example, a silicon substrate. The substrate 100 has an isolation structure 104 for defining a plurality of active regions 102. The arrangement of the active area 102 is not limited to the arrangement shown in FIG. 1A. The isolation structure 104 is, for example, a shallow trench isolation (STI) structure. In addition, various elements (such as a gate structure, a source region, a drain region, etc.) useful for forming a memory cell are formed on and in the substrate 100. However, in order to make the drawings clear, the above-mentioned various elements are omitted in the figure. Then, a dielectric layer 106 is formed on the substrate 100. The dielectric layer 106 is, for example, an oxide layer, and its formation method is, for example, a chemical vapor deposition method. The dielectric layer 106 covers various elements on the substrate 100. In addition, an interconnection structure is formed in the dielectric layer 106. Similarly, in order to make the drawings clear, the above-mentioned interconnection structure is omitted in the figure.

Next, referring to FIG. 1B and FIG. 2B at the same time, a bit line material layer 108 is formed on the dielectric layer 106. The bit line material layer 108 is, for example, a polysilicon layer, but the invention is not limited thereto. In other embodiments, the bit line material layer 108 may also be a composite layer composed of a polysilicon layer, a tungsten silicide layer, and a silicon nitride layer according to actual needs. In addition, a hard mask material layer 110 can also be formed on the bit line material layer 108. The hard mask material layer 110 may be an oxide layer, a nitride layer, or a stacked layer composed of an oxide layer and a nitride layer, but the invention is not limited thereto. In other embodiments, depending on actual needs, the hard mask material layer 110 may also be a single layer or a composite layer of other materials. After that, a double patterning process may be performed to form a plurality of mask patterns 112 on the hard mask material layer 110. In other embodiments, depending on the actual situation, a general single patterning process can also be used instead of a double patterning process. The mask pattern 112 is, for example, an oxide layer.

Then, referring to FIG. 1C and FIG. 2C at the same time, a patterned photoresist layer 114 is formed on the hard mask material layer 110. The patterned photoresist layer 114 exposes a portion of each mask pattern 112 corresponding to a region with a smaller width in the bit line to be formed later. In this embodiment, the exposed areas of the patterned photoresist layer 114 are alternately arranged with each other, but the invention is not limited to this. In other embodiments, the exposed area of the patterned photoresist layer 114 can be adjusted according to actual layout requirements.

Next, referring to FIGS. 1D and 2D at the same time, an isotropic etching process is performed to remove a part of the exposed mask pattern 112 to reduce the width of the exposed mask pattern 112. The aforementioned isotropic etching process is, for example, a wet etching process using buffered hydrofluoric acid (BHF). In this way, the mask pattern 112 can have a first portion 112a with a smaller width and a second portion 112b with a larger width, and the first portion 112a corresponds to a region with a smaller width in the bit line to be formed later. The mask pattern 112 serves as a mask when the bit line material layer 108 is patterned into multiple bit lines. Since the mask pattern 112 has a first portion 112a with a smaller width and a second portion 112b with a larger width, the bit line to be subsequently formed may also have a portion with a smaller width and a portion with a larger width. This will be further explained below.

Then, referring to FIG. 1E and FIG. 2E at the same time, the patterned photoresist layer 114 is removed. Next, using the mask pattern 112 as an etching mask, an anisotropic etching process is performed to remove part of the hard mask material layer 110 to form a hard mask pattern (not shown). Then, using the hard mask pattern as the etching mask, an anisotropic etching process is performed to remove part of the bit line material layer 108 to form a first part 116a with a smaller width and a second part 116b with a larger width. Bit line 116.

In this embodiment, by controlling the removal amount of the mask pattern 112 in the steps described in FIG. 1D and FIG. 2D to adjust the width of the formed first portion 112a, the required bit line 116 can be obtained. The width of the first part 116a. As shown in FIG. 1E, from the top view, in the direction perpendicular to the extension direction of the bit line 116, there is a distance between the side wall on one side of the first portion 116a and the side wall on the same side of the second portion 116b. D1, and on the opposite side, there is a distance D2 between the side wall of the first part 116a and the side wall of the second part 116b. In an embodiment, the distance D1 does not exceed 5 nm, and the distance D2 does not exceed 5 nm. In another embodiment, the distance D1 does not exceed 35% of the width W of the second portion 116b, and the distance D2 does not exceed 35% of the width W of the second portion 116b. In addition, in this embodiment, the distance D1 is equal to the distance D2, but the present invention is not limited to this. In other embodiments, the distance D1 and the distance D2 may be different from each other according to actual layout requirements.

Next, referring to FIG. 1F and FIG. 2F at the same time, a spacer 118 is formed on the sidewall of the bit line 116. The spacer 118 is, for example, a nitride layer. The method for forming the spacer 118 is, for example, to conformally form a spacer material layer on the dielectric layer 106, and then perform an anisotropic etching process to remove part of the spacer material layer. Then, a dielectric layer material layer is formed on the dielectric layer 106 to cover the bit line 116 and the spacer 118. Afterwards, for example, a chemical mechanical polishing process (CMP) is performed to remove part of the dielectric material layer to expose the top surface of the bit line 116, and a dielectric layer 120 is formed between the bit lines 116. Next, the dielectric layer 120 adjacent to the first portion 116a and the underlying dielectric layer 106 are removed to form an opening 122 exposing a portion of the active region 102. After that, a conductive layer is filled in the opening 122 to form a contact window 124 in the dielectric layer 120 and the dielectric layer 106 that is in contact with the active region 102. The contact window 124 is used to electrically connect a subsequently formed element (such as a capacitor) with the active region 102.

In this embodiment, the bit line 116 has a first portion 116 a with a smaller width and a second portion 116 b with a larger width, and the contact window 124 between the bit lines 116 is disposed adjacent to the first portion 116 a. As a result, compared to the bit lines with uniform width, the contact window 124 can have a larger size and lower resistance, and the contact window 124 can have a larger contact area with the active region 102. The amount of current flowing through the contact window 124 and the active area 102 when the device is operated is increased, thereby improving the electrical performance of the device. As shown in the area 126 in FIG. 1F, compared to the bit line having a uniform width, the contact window 124 increases the size and the contact area with the active region 102.

In addition, in this embodiment, the distance D1, D2 between the sidewall of the first portion 116a and the sidewall of the second portion 116b does not exceed 5 nm, or the distance D1, D2 does not exceed 35% of the width W of the second portion 116b. In this way, in the case of increasing the size of the contact window 124 by reducing the width of the bit line 116, the resistance of the bit line 116 itself can also be maintained to a desired level, without reducing the bit line 116. Excessive shrinkage of the width of the device leads to an excessive increase in resistance, thus affecting the electrical performance of the device.

100: base 102: active area 104: Isolation structure 106, 120: Dielectric layer 108: bit line material layer 110: Hard mask material layer 112: mask pattern 112a, 116a: part one 112b, 116b: part two 114: Patterned photoresist layer 116: bit line 118: Clearance Wall 122: open 124: contact window 126: area D1, D2: distance W: width

1A to 1F are schematic top views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views along the line I-I' in FIGS. 1A to 1F.

116: bit line

116a: Part One

116b: Part Two

118: Clearance Wall

120: Dielectric layer

124: contact window

126: area

Claims (8)

A semiconductor structure includes: a substrate having a plurality of active regions arranged parallel to each other; a dielectric layer arranged on the substrate; a plurality of bit lines arranged parallel to each other on the dielectric layer, each The bit line partially overlaps the active region, wherein each bit line has a first portion and a second portion alternately in its extending direction, and the width of the first portion is smaller than that of the second portion Width; spacers are provided on the sidewalls of each of the bit lines; and contact windows are provided between adjacent bit lines and are connected to at least one of the adjacent bit lines The first part is adjacent and passes through the dielectric layer to contact the active region. From the top view, in the direction perpendicular to the extension direction of the bit line, the first part of the first part There is a first distance between the side wall on one side and the side wall on the first side of the second part, and the first distance does not exceed 35% of the width of the second part, and the distance of the first part There is a second distance between the side wall of the second side opposite to the first side and the side wall of the second side of the second part, and the second distance does not exceed the width of the second part 35%. The semiconductor structure according to the first item of the scope of patent application, wherein from a top view, in a direction perpendicular to the extending direction of the bit line, the sidewall of the first side of the first part is connected to the first side There is a first distance between the sidewalls of the first side of the two parts, and the first distance does not exceed 5 nm, and the and There is a second distance between the side wall of the second side opposite to the first side and the side wall of the second side of the second part, and the second distance does not exceed 5 nm. The semiconductor structure according to the first item of the scope of patent application, wherein the first portions of adjacent bit lines are staggered with each other. A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a substrate, wherein the substrate has a plurality of active regions arranged parallel to each other; forming a plurality of bit lines parallel to each other on the dielectric layer, each The bit line partially overlaps the active region, wherein each bit line has a first portion and a second portion that alternate with each other in its extending direction, and the width of the first portion is smaller than that of the second portion The width of each bit line is formed on the sidewall; and a contact window is formed between adjacent bit lines, wherein the contact window and at least one of the adjacent bit lines The first part of the one is adjacent and passes through the dielectric layer to contact the active region, wherein from a top view angle, in a direction perpendicular to the extension direction of the bit line, the There is a first distance between the side wall of the first side of the first part and the side wall of the first side of the second part, and the first distance does not exceed 35% of the width of the second part, and so There is a second distance between the side wall on the second side of the first part opposite to the first side and the side wall on the second side of the second part, and the second distance does not exceed the second distance. 35% of the width of the part. The method for manufacturing a semiconductor structure as described in claim 4, wherein from the top view, in a direction perpendicular to the extension direction of the bit line, the side wall of the first side of the first part is aligned with There is a first distance between the side walls on the first side of the second part, and the first distance does not exceed 5 nm, and the side walls on the second side of the first part opposite to the first side and There is a second distance between the sidewalls of the second side of the second part, and the second distance does not exceed 5 nm. According to the method for manufacturing a semiconductor structure according to claim 4, the method for forming the bit line includes: forming a bit line material layer on the dielectric layer; and on the bit line material layer Forming a plurality of mask patterns parallel to each other; forming a patterned photoresist layer on the bit line material layer, wherein the patterned photoresist layer exposes a part of each mask pattern; performing isotropic etching The process includes removing a part of the exposed mask pattern to reduce the width of the exposed mask pattern; removing the patterned photoresist layer; using the multiple mask patterns as masks to perform non-exposure An isotropic etching process removes part of the bit line material layer; and removes the photoresist pattern. According to the method for manufacturing a semiconductor structure as described in item 4 of the scope of patent application, the method for forming the spacer includes: After forming the plurality of bit lines, a spacer material layer is conformally formed on the dielectric layer; and an anisotropic etching process is performed to remove part of the spacer material layer. According to the manufacturing method of the semiconductor structure described in claim 4, the method of forming the contact window includes: after forming the spacer, forming a dielectric material layer on the dielectric layer to cover the The plurality of bit lines; remove a portion of the dielectric material layer to expose the top surface of the plurality of bit lines; remove the dielectric material layer adjacent to the first portion and the underlying A dielectric layer to form an opening exposing part of the active area; and a conductive layer is formed in the opening.

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