TWI576993B - Method of fabricating memory device - Google Patents

Method of fabricating memory device Download PDF

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Publication number
TWI576993B
TWI576993B TW104141456A TW104141456A TWI576993B TW I576993 B TWI576993 B TW I576993B TW 104141456 A TW104141456 A TW 104141456A TW 104141456 A TW104141456 A TW 104141456A TW I576993 B TWI576993 B TW I576993B
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Taiwan
Prior art keywords
dielectric layer
layer
opening
region
substrate
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TW104141456A
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Chinese (zh)
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TW201721839A (en
Inventor
簡毅豪
田中義典
張維哲
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華邦電子股份有限公司
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Publication of TW201721839A publication Critical patent/TW201721839A/en

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Description

Memory element manufacturing method
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a memory device.
In order to improve the accumulative degree of dynamic random access memory to speed up the operation speed of components and meet the needs of consumers for miniaturized electronic devices, buried word line dynamic random access memory (buried word) has been developed in recent years. Line DRAM) to meet the above needs. However, as the memory accumulation increases, the word line spacing and the isolation structure of the memory array will continue to shrink, resulting in various adverse effects. For example, cell-to-cell leakage, interference between word lines (also known as Row Hammer), t WR failure, retention failure, bit line Bit Line coupling failure, etc.
Therefore, in order to deal with interference between word lines, an isolation structure deeper than the buried word line is used to improve the above problem. However, in this case, the original isolation structure process must be changed, and the lithography process of simultaneously forming the word line and the isolation structure is changed to at least two lithography processes, one is to make a deep isolation structure, and the other is to make a deep isolation structure, One is to make a buried word line between the isolated structures.
However, in the prior art, the step of forming a spacer structure and a capacitor contact window by using a multi-pass lithography process, respectively, easily causes an alignment issue. The alignment problem can become more severe as the size of the component shrinks, for example, it tends to result in a reduced contact area between the active region (eg, the source/drain region) and the capacitor contact window. As the contact area between the active area and the capacitor contact window becomes smaller, the resistance between the active area and the capacitor contact window is increased, thereby causing the read/write time to fail. Therefore, how to develop a method for manufacturing a memory element, which can improve the contact area between the active area and the capacitive contact window caused by the offset in the lithography process, will become an important issue.
The present invention provides a method of fabricating a memory device having a self-aligned isolation structure to improve the problem of reduced contact area between the active region and the capacitive contact window caused by offset in the lithography process.
The present invention provides a method of fabricating a memory element that reduces process steps to reduce process cost.
The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A substrate having a first zone and a second zone is provided. A plurality of word line groups are formed in the substrate of the first region. Each character line group has two buried word lines. A first dielectric layer is formed on the substrate of the first region. A conductor layer is formed on the substrate of the second region, wherein a top surface of the conductor layer is lower than a top surface of the first dielectric layer. Forming a second dielectric layer on the substrate. A first etching process is performed to remove a portion of the second dielectric layer and a portion of the conductor layer to form a first opening in the conductor layer and the second dielectric layer of the second region. The first opening exposes a surface of the substrate of the second region. A second etching process is performed to remove a portion of the substrate of the second region to form a trench in the substrate of the second region, wherein the first opening is on the trench. A third dielectric layer is formed in the trench and the first opening. A portion of the first dielectric layer and the third dielectric layer are removed to form a second opening on the remaining first dielectric layer, and a third opening is formed on the remaining third dielectric layer. Forming a fourth dielectric layer in the second opening and the third opening.
Based on the above, the present invention can form an isolation structure by forming a self-aligned trench to improve the problem that the contact area between the active region and the capacitive contact window is reduced due to the offset in the lithography process. Additionally, the present invention can vary the thickness of the second dielectric layer to adjust the width of the subsequently formed isolation structure. In addition, the present invention can also simplify the process steps to reduce process costs.
The above described features and advantages of the invention will be apparent from the following description.
The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a memory element in accordance with a first embodiment of the present invention.
Referring to FIG. 1 , the present embodiment provides a memory device including: a substrate 100 , a plurality of isolation structures 101 , a plurality of active regions 102 , a plurality of bit lines 104 , a plurality of word line groups 106 , and a plurality of capacitor contact windows 108 . And a plurality of bit line contact windows 110. For the sake of clarity of the drawing, FIG. 1 only shows the above-mentioned members, and other structures can be seen in the subsequent cross-sectional views of FIGS. 2A to 2H.
In the first embodiment, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 are arranged to each other along the first direction D1. An isolation structure 101 is formed in the substrate 100 of the second region R2, which extends along the second direction D2. The isolation structure 101 may chop a plurality of strip-type active areas arranged along the second direction D2 to define a plurality of active areas 102. In other words, there is an isolation structure 101 between two adjacent active regions 102. In this embodiment, the strip-shaped active area is linear. However, the invention is not limited thereto. In other embodiments, the strip active region may be, for example, non-linear, for example, it may be, for example, a zigzag shape.
The bit line 104 is located on the substrate 100 and traverses the first region R1 and the second region R2. The bit lines 104 extend along the first direction D1 and are arranged along the second direction D2. The word line group 106 is located in the substrate 100 of the first region R1. The word line groups 106 extend along the second direction D2 and are arranged to each other along the first direction D1. Each word line set 106 has two buried word lines 106a, 106b. The first direction D1 is different from the second direction D2. In an embodiment, the first direction D1 and the second direction D2 are substantially perpendicular to each other.
In this embodiment, each active region 102 has a long side L1 and a short side L2, and the long side L1 traverses the corresponding word line group 106 (ie, two buried word lines 106a, 106b), and Each of the active regions 102 has a bit line contact window 110 at an overlap with the corresponding bit line 104. Therefore, each bit line 104 can be electrically connected to a corresponding doped region (not shown) by using a bit line contact window 110 when traversing the corresponding word line group 106, wherein the doped region Located between two buried word lines 106a, 106b. In addition, the bit line contact window 110 is shown as a rectangle in FIG. 1, but the contact window actually formed is slightly rounded, and its size can be designed according to process requirements.
Capacitor contact windows 108 are located on substrate 100 between bit lines 104. In detail, the capacitor contact windows 108 are arranged in a plurality of rows (Row) and a plurality of rows, the columns are arranged along the second direction D2, and the rows are arranged along the first direction D1. On the other hand, the capacitor contact window 108 is disposed on the substrate 100 on both sides of the word line group 106, that is, each two rows of the capacitor contact window 108 and has two buried word lines 106a, 106b. The set of word lines 106 alternate with each other along the first direction D1.
2A to 2H are schematic cross-sectional views showing a manufacturing flow of the memory element of the second embodiment taken along line I-I' of Fig. 1.
Referring to FIG. 1 and FIG. 2A simultaneously, the present invention provides a method of manufacturing a memory element, the steps of which are as follows. First, a substrate 100 is provided. In this embodiment, the substrate 100 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The substrate 100 has a plurality of first regions R1 and a plurality of second regions R2. The first zone R1 and the second zone R2 alternate with each other.
Next, a plurality of word line groups 106 are formed in the substrate 100 of the first region R1. In detail, each word line group 106 includes two buried word lines 106a, 106b. Each buried word line 106a includes a gate 112a and a gate dielectric layer 114a. The gate dielectric layer 114a surrounds the gate 112a to electrically isolate the gate 112a from the substrate 100. In one embodiment, the material of the gate 112a includes a conductive material, which may be, for example, a metal material, a barrier metal material, or a combination thereof, which may be formed by chemical vapor deposition or physical vapor deposition. The material of the gate dielectric layer 114a may be, for example, hafnium oxide, which may be formed by a chemical vapor deposition method, a thermal oxidation method, or an in situ steam generation (ISSG). Similarly, another buried word line 106b also includes a gate 112b and a gate dielectric layer 114b. The gate dielectric layer 114b surrounds the gate 112b to electrically isolate the gate 112b from the substrate 100.
Thereafter, a tantalum nitride layer 116a is formed on the buried word line 106a, and a tantalum nitride layer 116b is formed on the buried word line 106b. A tantalum oxide layer 118 is formed on the substrate 100 between the tantalum nitride layers 116a, 116b. A tantalum nitride layer 120 is formed on the tantalum nitride layers 116a, 116b and the tantalum oxide layer 118. In an embodiment, the method for forming the tantalum nitride layers 116a, 116b, the hafnium oxide layer 118, and the tantalum nitride layer 120 may be a chemical vapor deposition method.
Then, a first dielectric layer 122 is formed on the substrate 100 of the first region R1. The first dielectric layer 122 includes dielectric material layers 121a, 121b. In an embodiment, the material of the dielectric material layer 121a may be, for example, a spin-on dielectric (SOD). The material of the dielectric material layer 121b may be, for example, tetraethoxysilane (TEOS). However, the invention is not limited thereto, and the material of the first dielectric layer 122 may be a dielectric material or a combination of a plurality of dielectric materials.
Referring to FIG. 1 and FIG. 2B simultaneously, the conductor layer 124 is formed on the substrate 100 of the second region R2, wherein the top surface of the conductor layer 124 is lower than the top surface of the first dielectric layer 122. Specifically, the step of forming the conductor layer 124 includes first forming a conductor material layer (not shown) on the substrate 100. The conductive material layer covers not only the surface of the substrate 100 of the second region R2 but also the top and sidewalls of the first dielectric layer 122. Next, an etch back process is performed to remove a portion of the conductive material layer to expose the top surface of the first dielectric layer 122 and a portion of the sidewalls. In an embodiment, the material of the conductor layer 124 may be, for example, doped polysilicon, which may be formed by chemical vapor deposition.
Next, please refer to FIG. 1 and FIG. 2C simultaneously to form a second dielectric layer 126 on the substrate 100. Since the top surface of the conductor layer 124 is lower than the top surface of the first dielectric layer 122, the second dielectric layer 126 can be, for example, a continuous relief structure. The second dielectric layer 126 on the first dielectric layer 122 is a convex portion; and the second dielectric layer 126 on the conductive layer 124 is a concave portion. In an embodiment, the material of the second dielectric layer 126 may be, for example, tantalum nitride, which may be formed by atomic layer deposition (ALD).
It should be noted that in the present embodiment, the width W of the subsequently formed isolation structure 101 can be adjusted by changing the thickness T of the second dielectric layer 126 (as shown in FIG. 2F). For example, when the thickness T of the second dielectric layer 126 is thicker, the width of the recess opening 125 on the conductor layer 124 is smaller. Then, the widths of the first opening 10 and the trench 15 formed after the subsequent first etching process and the second etching process are subsequently reduced. Therefore, the width W of the isolation structure 101 located in the trench 15 is also reduced. vice versa.
Then, referring to FIG. 1 and FIG. 2D simultaneously, a first etching process is performed to remove a portion of the second dielectric layer 126 and a portion of the conductor layer 124 to form the conductor layer 124a and the second opening of the first opening 10 in the second region R2. In the dielectric layer 126a. The first opening 10 exposes the surface of the substrate 100 of the second region R2. In addition, when performing the first etching process, a portion of the second dielectric layer 126 of the first region R1 is removed to expose the top surface of the first dielectric layer 122. On the other hand, the first opening 10 divides one conductor layer 124 into two conductor layers 124a. In an embodiment, the first etching process can be, for example, a single step, two steps, or multiple steps.
Referring to FIG. 1 and FIG. 2E simultaneously, a second etching process is performed to remove the substrate 100 of the portion of the second region R2 to form the trench 15 in the substrate 100 of the second region R2. The first opening 10 is located on the trench 15. In this embodiment, the etching process of the second etching process can be adjusted by adjusting the process parameters of the second etching process (which may be, for example, an etching gas composition or ratio, etc.), so that the second etching process is relatively high for the substrate 100 material (which may be, for example, germanium). Therefore, when the first dielectric layer 122 and the second dielectric layer 126a are used as the mask layer, most of the substrate 100 can be removed to form the self-aligned trenches 15 during the second etching process. In one embodiment, a small portion of the first dielectric layer 122 and the second dielectric layer 126a are removed by the second etch process, but it does not affect the formation of the self-aligned trenches 15. Here, the first dielectric layer 122 and the second dielectric layer 126a removed by the second etching process are represented by the first dielectric layer 122a and the second dielectric layer 126b. In one embodiment, the bottom surface of the trench 15 is lower than the bottom surface of the buried word lines 106a, 106b.
Referring to FIG. 1 and FIG. 2F simultaneously, a third dielectric layer 128 is formed in the trench 15 and the first opening 10. Specifically, the step of forming the third dielectric layer 128 includes first forming a third dielectric material layer (not shown) on the substrate 100. The third dielectric material layer not only fills the trench 15 and the first opening 10, but also covers the top surface of the first dielectric layer 122a and the top surface of the second dielectric layer 126b. Performing a chemical mechanical polishing (CMP) process to remove a portion of the third dielectric material layer to expose the top surface of the first dielectric layer 122a or the top surface of the second dielectric layer 126b, such that the first dielectric The top surface of layer 122a and the top surface of second dielectric layer 126b are coplanar. In an embodiment, the material of the third dielectric layer 128 may be, for example, yttrium oxide or a spin-on dielectric material (SOD). However, the present invention is not limited thereto, as long as it is a dielectric material having a good filling ability. In an embodiment, the third dielectric layer 128 filled into the trench 15 can be, for example, the isolation structure 101. The bottom surface of the isolation structure 101 is lower than the bottom surface of the buried word lines 106a, 106b to improve interference between the word lines.
Referring to FIG. 1 and FIG. 2G simultaneously, a portion of the first dielectric layer 122a and the third dielectric layer 128 are removed to form a second opening 20 on the remaining first dielectric layer 122b, and a third opening 30 is formed. The remaining third dielectric layer 128a. The bottom surface of the second opening 20 and the bottom surface of the third opening 30 are coplanar. In an embodiment, the method of removing a portion of the first dielectric layer 122a and the third dielectric layer 128 may be, for example, a wet etching method.
Referring to FIG. 1 , FIG. 2G and FIG. 2H , a fourth dielectric layer 130 is formed in the second opening 20 and the third opening 30 . Since the fourth dielectric layer 130 is disposed on the first dielectric layer 122b and the third dielectric layer 128a, it can be used as an etch stop layer. Therefore, when a capacitor (not shown) is formed later, there is no problem that the first dielectric layer 122b and the isolation structure 101 are worn out due to over-etching. Specifically, a fourth dielectric material layer (not shown) is formed on the substrate 100 in a conformal manner. A fourth dielectric material layer is filled in the second opening 20 and the third opening 30 and covers the top surface of the second dielectric layer 126b. A planarization process is performed to remove a portion of the fourth dielectric material layer and the second dielectric layer 126b such that the top surface of the fourth dielectric layer 130 and the top surface of the conductor layer 124a are coplanar. In an embodiment, the material of the fourth dielectric layer 130 may be, for example, tantalum nitride, and the forming method thereof may be, for example, atomic layer deposition (ALD). In an embodiment, the planarization process can be, for example, a CMP process or an etch back process. In an embodiment, the conductor layer 124a can be, for example, a capacitor contact window 108. Thereafter, a plurality of capacitors (not shown) may be formed on the conductor layer 124a (or the capacitor contact window 108), respectively.
In summary, the present invention can form an isolation structure by forming self-aligned trenches to improve the problem of the contact area between the active region and the capacitive contact window caused by the offset in the lithography process. Additionally, the present invention can vary the thickness of the second dielectric layer to adjust the width of the subsequently formed isolation structure. In addition, the present invention can also simplify the process steps to reduce process costs.
Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧ first opening
15‧‧‧ Ditch
20‧‧‧second opening
30‧‧‧ third opening
100‧‧‧Base
101‧‧‧Isolation structure
102‧‧‧active area
104‧‧‧ bit line
106‧‧‧ character line group
106a, 106b‧‧‧ Buried word line
108‧‧‧Capacitor contact window
110‧‧‧ bit line contact window
112a, 112b‧‧‧ gate
114a, 114b‧‧‧ gate dielectric layer
116a, 116b‧‧‧ layer of tantalum nitride
118‧‧‧Oxide layer
120‧‧‧layer of tantalum nitride
121a, 121b‧‧‧ dielectric material layer
122, 122a, 122b‧‧‧ first dielectric layer
124, 124a‧‧‧ conductor layer
125‧‧‧ recess opening
126, 126a, 126b‧‧‧ second dielectric layer
128, 128a‧‧‧ third dielectric layer
130‧‧‧fourth dielectric layer
D1‧‧‧ first direction
D2‧‧‧ second direction
L1‧‧‧ long side
L2‧‧‧ Short side
R1‧‧‧ first district
R2‧‧‧Second District
T‧‧‧ thickness
W‧‧‧Width
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a memory element in accordance with a first embodiment of the present invention. 2A to 2H are schematic cross-sectional views showing a manufacturing flow of the memory element of the second embodiment taken along line I-I' of Fig. 1.
20‧‧‧second opening
30‧‧‧ third opening
100‧‧‧Base
101‧‧‧Isolation structure
106a, 106b‧‧‧ Buried word line
108‧‧‧Capacitor contact window
118‧‧‧Oxide layer
120‧‧‧layer of tantalum nitride
122b‧‧‧First dielectric layer
124a‧‧‧ conductor layer
128a‧‧‧ third dielectric layer
130‧‧‧fourth dielectric layer
R1‧‧‧ first district
R2‧‧‧Second District

Claims (9)

  1. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a plurality of word line groups in the substrate of the first region, each word line group having Two buried word lines; forming a first dielectric layer on the substrate of the first region; forming a conductor layer on the substrate of the second region, wherein a top surface of the conductor layer is lower than the a top surface of the first dielectric layer; a second dielectric layer is formed on the substrate; a first etching process is performed to remove a portion of the second dielectric layer and a portion of the conductive layer of the second region, Forming a first opening in the conductor layer of the second region and the second dielectric layer, wherein the first opening exposes a surface of the substrate of the second region, wherein when performing the first etching process, The method includes removing a portion of the second dielectric layer of the first region to expose a top surface of the first dielectric layer, and performing a second etching process to remove a portion of the substrate of the second region to form a trench In the substrate of the second region, wherein the first opening is located on the trench; forming a third dielectric layer The first dielectric layer and the third dielectric layer are removed to form a second opening on the remaining first dielectric layer, and a third opening is formed in the trench Remaining on the third dielectric layer; and forming a fourth dielectric layer in the second opening and the third opening.
  2. The method of manufacturing the memory device of claim 1, wherein the material of the first dielectric layer comprises tetraethoxy decane (TEOS), spin-on dielectric material (SOD), or a combination thereof.
  3. The method of manufacturing a memory device according to claim 1, wherein the material of the conductor layer comprises doped polysilicon.
  4. The method of manufacturing the memory device of claim 1, wherein the material of the second dielectric layer comprises tantalum nitride, and the method of forming the second dielectric layer comprises atomic layer deposition (ALD).
  5. The method of manufacturing a memory device according to claim 1, wherein the material of the third dielectric layer comprises ruthenium oxide.
  6. The method of fabricating a memory device according to claim 1, wherein the material of the fourth dielectric layer comprises tantalum nitride, and the method of forming the fourth dielectric layer comprises atomic layer deposition (ALD).
  7. The method of manufacturing a memory device according to claim 1, wherein the first etching process comprises one step, two steps or multiple steps.
  8. The method of manufacturing a memory device according to claim 1, wherein a bottom surface of the second opening and a bottom surface of the third opening are coplanar.
  9. The method of manufacturing the memory device of claim 1, wherein the forming the fourth dielectric layer in the second opening and the third opening comprises: conformally forming a fourth dielectric material layer a fourth dielectric material layer is filled in the second opening and the third opening and covers a top surface of the second dielectric layer; and a planarization process is performed to remove a portion of the fourth dielectric The material layer and the second dielectric layer are such that a top surface of the fourth dielectric layer is coplanar with a top surface of the conductor layer.
TW104141456A 2015-12-10 2015-12-10 Method of fabricating memory device TWI576993B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030102515A1 (en) * 1997-08-22 2003-06-05 Luan Tran Memory cell arrays
US20060202340A1 (en) * 2003-01-22 2006-09-14 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20080253160A1 (en) * 2007-04-13 2008-10-16 Qimonda Ag Integrated circuit having a memory cell array and method of forming an integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030102515A1 (en) * 1997-08-22 2003-06-05 Luan Tran Memory cell arrays
US20060202340A1 (en) * 2003-01-22 2006-09-14 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20080253160A1 (en) * 2007-04-13 2008-10-16 Qimonda Ag Integrated circuit having a memory cell array and method of forming an integrated circuit

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