KR100243288B1 - Capacitor manufacturing method of semiconductor device - Google Patents

Abstract

Disclosed is a method of manufacturing a capacitor of a semiconductor device capable of increasing the capacitance while removing the tearing phenomenon. The first spacer layer, the first etch stop layer, and the second spacer layer are sequentially stacked on the semiconductor substrate, and then sequentially etched to form a condact hole that partially exposes the semiconductor substrate. The first conductive layer is formed on the entire surface of the resultant substrate in which the contact hole is formed, and is patterned to form a storage electrode pattern. The first undercut is formed by isotropically etching the second spacer layer exposed between the storage electrode patterns, and the second conductive layer is formed to cover the entire surface of the storage electrode pattern and the first undercut. The second conductive layer is etched back to form conductive spacers on the sidewalls of the storage electrode pattern, and at the same time, fins separated in units of cells are formed in the first undercut. The first etch stop layer exposed by the pins separated by the cell unit is etched to partially expose the first spacing layer, and then isotropically etched to form a second undercut. A dielectric film is formed on the exposed first and second conductive layer surfaces. A third conductive layer is formed on the dielectric film.

Description

Capacitor manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of increasing the capacitance while eliminating the tearing phenomenon.

In the case of a memory device such as a dynamic random access memory (DRAM), in order to increase the memory capacity, the capacitance per unit area of the capacitor must be increased.

In order to increase the capacitance of the capacitor, various methods such as changing the structure of the storage electrode, changing the material constituting the dielectric film, or reducing the thickness of the dielectric film are currently being studied.

1 to 3 are cross-sectional views illustrating a conventional method of manufacturing a capacitor of a semiconductor device according to a process sequence, and illustrate a capacitor over bit-line (COB) structure in which a capacitor is formed on an upper portion of a bit line.

A boron-in-doped silicon glass (BPSG) is deposited on the semiconductor substrate 10 having a transistor (not shown) to a thickness of about 3,000 GPa and then flowed to form the planarization layer 12. The silicon oxynitride (SiON) film 14 is formed on the planarization layer 12 to a thickness of about 160 kPa, and then the high temperature oxide film (HTO) 16 is formed to a thickness of about 1,500 kPa. Subsequently, the above-described material layers stacked on the source (not shown) of the transistor are sequentially etched to form a contact hole 18, and silicon oxy nitride is deposited on the entire surface of the substrate on which the contact hole is formed. After the deposition to a thickness of about to anisotropic etching to form the insulating spacer 20 on the sidewall of the contact hole (18). Thereafter, a polysilicon film 22 doped with impurities is formed on the entire surface of the substrate on which the insulating spacers 20 are formed (FIG. 1).

Thereafter, a photoresist is applied on the polysilicon film 22 and then patterned to form a photoresist pattern 24 for forming a storage electrode, and a polymer spacer 26 is formed on the sidewalls of the photoresist pattern 24. . At this time, the polymer spacer 26 is formed by a polymer generation process (Polymer Generation Process) for generating a polymer by controlling the type of gas supplied to the etching chamber (Etch Chamber) (Fig. 2).

Subsequently, the storage electrode 28 is formed by anisotropically etching the polysilicon film (reference numeral 22 in FIG. 2) using the photoresist pattern 24 and the polymer spacer 26 as a mask (FIG. 3). Thereafter, the photoresist pattern (reference numeral 24 of FIG. 3) and the high temperature oxide film 16 are removed, and a dielectric film and a polysilicon film are sequentially stacked on the storage electrode surface to complete the capacitor.

4 is a photo showing a vertical cross-sectional view of a capacitor of a conventional semiconductor device, wherein a quadrangle at the top of the photo represents a storage electrode and a white line at the middle of the photo represents a bit line.

According to the conventional method of manufacturing a capacitor of a semiconductor device, since the polymer spacer is formed and then anisotropic etching is performed to form the storage electrode, the size of the storage electrode (hereinafter referred to as "CD") can be increased, so that Can increase the capacitance.

However, in the anisotropic etching for forming the storage electrode, not only the polysilicon film but also the polymer spacer (26 in FIG. 2) formed on the sidewalls of the photoresist pattern 24 by the etching gas supplied to etch the polycrystalline silicon film. By the time it is removed little by little to etch a polysilicon film of about 8,000 두께 thickness, all of the above polymer spacers are also removed to tear along the edges of the storage electrode 28 (parts indicated by A in FIG. 3 and indicated by arrows in FIG. 5). Part) occurs.

In the tearing phenomenon, when the dielectric film is continuously transferred after the formation of the storage electrode, the thickness of the dielectric film deposited on the portion where the tearing occurs is unevenly deposited (in the portion where the tearing occurs sharply, the dielectric film is deposited thinner than the portion that is not. As a result, dielectric breakdown of the dielectric film is caused by uneven size of the electric field applied to this portion (the electric field is stronger than the thick portion of the thin dielectric film). Such dielectric breakdown of the dielectric film increases the leakage current of the memory device, resulting in a failure of the memory device.

Therefore, there is a need for a method capable of increasing the size of the storage electrode without the above-described tearing phenomenon.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of removing a tearing phenomenon and increasing capacitance.

1 to 3 are cross-sectional views illustrating a conventional capacitor manufacturing method of a semiconductor device according to a process sequence.

4 is a photograph showing a vertical cross-sectional view of a capacitor of a conventional semiconductor device.

5 is a photograph showing a case in which a tear bit (Mouse Bite) occurs in the storage electrode.

6 to 10 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention by process order.

11 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device according to another embodiment of the present invention.

The first spacer layer, the etch stop layer, and the second spacer layer are sequentially stacked on the semiconductor substrate, and the etching holes are sequentially formed to form contact holes for partially exposing the semiconductor substrate, and then insulating spacers are formed on the contact hole sidewalls. . Subsequently, after the first conductive layer is formed on the entire surface of the resultant substrate, a photosensitive film pattern for forming a storage electrode pattern having a shape separated in units of cells is formed. The polymer spacer is formed on sidewalls of the photoresist pattern. The storage electrode pattern is formed by etching the first conductive layer using the photoresist pattern and the polymer spacer as a mask. Subsequently, the second space layer exposed between the storage electrode patterns is wet-etched to form a first undercut, and the second conductive layer is formed to cover the entire surface of the storage electrode pattern and the first undercut. The second conductive layer is etched back to form conductive spacers on sidewalls of the storage electrode pattern, and fins separated in cell units are formed in the first undercut. Subsequently, the etch stop layer exposed by the fins separated by cell units is etched to partially expose the first spacer layer. This process is performed simultaneously with the step of etching back the second conductive layer without performing a separate etching process. . The second undercut is formed by wet etching the exposed first spacer layer, and then a dielectric layer and a third conductive layer are sequentially formed.

In this case, the storage electrode pattern may be formed by anisotropic etching using only a photoresist pattern as a mask without forming a polymer spacer.

In the present invention, the first spacer layer is formed of a high temperature oxide film (HTO), plasma enhanced tetra ethyl oxy silicon (PE-TEOS) or plasma enhanced oxide film (PE-Oxide) to a thickness of about 500 ~ 1,500Å The anti-etching layer may be formed of silicon nitride (SiN) or silicon oxy nitride (SiON) to a thickness of about 50 kV to 150 kPa, and the second spaced apart layer may be formed of a high temperature oxide film (HTO) and plasma enhanced tetraether oxy silicon ( PE-TEOS), plasma enhanced oxide film (PE-Oxide) or boron-phosphorus-doped silicon glass (BPSG), which is formed to a thickness of about 2,500 Å to 4,000 절연, and the insulating spacer is 250 로 with silicon oxy nitride It is preferable to form in thickness of about -600 Pa.

Hereinafter, a capacitor manufacturing method of a semiconductor device according to the present invention will be described in more detail with reference to the accompanying drawings.

6 to 10 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention by process order.

First, FIG. 6 is a cross-sectional view illustrating a process of forming the first spacer layer 36, the etch stop layer 38, the second spacer layer 40, and the contact hole 42. On the semiconductor substrate 30 on which a transistor (not shown) is formed, for example, a boron-in-doped silicon glass (BPSG) is applied to a thickness of about 3,000 kPa to 5,000 kPa, and then flowed. In the first step of forming the planarization layer 32 having a flat surface, a thickness of, for example, silicon nitride (SiN) or silicon oxynitride (SiON) on the planarization layer 32 is about 50 kPa to 200 kPa, preferably A second step of forming an etch stop layer 34 by applying silicon oxynitride to a thickness of 160 kPa, on the etch stop layer 34, for example, a high temperature oxide film (HTO), plasma enhanced tetra ethyl oxy silicon (PE) -TEOS) or Plasma Enhancement Oxide (PE-Oxide) A third step of forming the first spacer layer 36 by applying a thickness, preferably a high temperature oxide film, to a thickness of 1,000 GPa, on the first spacer layer 36, for example, silicon nitride (SiN) or silicon A fourth step of forming the etch stop layer 38 by applying oxy nitride (SiON) to a thickness of about 50 kPa to 150 kPa, preferably silicon nitride, of about 70 kPa, on the etch stop layer 38, for example High temperature oxide film (HTO), plasma enhanced tetra ethyl oxy silicon (PE-TEOS), plasma enhanced oxide film (PE-Oxide) or boron-phosphorized silicon glass (BPSG) Preferably, the fifth step of forming the second separation layer 40 by applying plasma enhanced tetraethyl oxy silicon to a thickness of 3,500 kPa, the above-described material stacked on a source (not shown) of the transistor Turn the floors A sixth step of forming the contact hole 42 in the shape of exposing the semiconductor substrate on which the source is formed by etching the same, and the entire surface of the substrate on which the contact hole 42 is formed, for example, silicon oxynitride (SiON). ) Is applied to a thickness of about 250 kPa to 600 kPa, preferably 500 kPa, and then anisotropically etched to form the insulating spacer 44 on the sidewall of the contact hole 42.

FIG. 7 is a cross-sectional view for explaining the process of forming the storage electrode pattern 48. This process is performed by applying 7,000 Å of polysilicon doped with impurities to the entire surface of the substrate on which the contact holes 42 are formed. The storage electrode is subjected to a first step of forming a first conductive layer 48 by depositing to a thickness of about a degree, and applying a photoresist film such as a photoresist onto the first conductive layer 48 and then exposing and developing the storage electrode. In the second step of forming the photoresist pattern 46 for pattern formation, the substrate on which the photoresist pattern 46 is formed is placed in an etching chamber, and then a kind of gas supplied thereto is adjusted to generate polymers. A third step of forming a polymer spacer 47 on the sidewalls of the photoresist pattern 46 by performing a polymer generating process, and using the photoresist pattern 46 and the polymer spacer 47 as a mask to form the first conductive layer. Castle by etching proceeds to a fourth step of forming said storage electrode pattern 48 is separated into each cell unit.

In this case, the storage electrode pattern 48 has a size CD that is equal to the size CD of the photoresist pattern and the thickness of the lateral thickness of the polymer spacer. However, on the surface of the storage electrode pattern 48, the tearing phenomenon as mentioned above along the edges of the storage electrode pattern 48 may occur (not shown).

FIG. 8 is a cross-sectional view illustrating a process of forming the first undercut u1 and the second conductive layer 50. The process may include a second spaced layer exposed between the storage electrode patterns 48 (FIG. 7). 40 is removed by, for example, an isotropic process such as wet etching to form the first undercut u1 and to cover the exposed storage electrode pattern 48 surface and the first undercut u1. For example, the method proceeds to the second step of forming the second conductive layer 50 by depositing polysilicon doped with impurities to a thickness of about 1,000 m 3.

FIG. 9 is a cross-sectional view illustrating a process of forming the conductive spacers 51 and the fins 52, wherein the second and first conductive layers are etched on the entire surface of the substrate on which the second conductive layer is formed. The etchback is etched until the second conductive layer formed on the storage electrode pattern 48 is completely removed and the etch stop layer 38 that has been exposed by the first undercut is etched to separate each cell unit. The conductive spacers 51 are formed on the sidewalls of the storage electrode patterns 46, and the fins 52 are formed on the first undercuts.

During the etch back, the etching gas is supplied between the storage electrode pattern 48 and the storage electrode pattern, so that the second conductive layer formed on the storage electrode pattern 48 is removed and exposed between the storage electrode pattern 48. The second conductive layer and the underlying etch stop layer are removed to form the conductive spacer 51 and the fin 52 as mentioned. At this time, even if it is formed on the surface of the storage electrode pattern 48, the tearing phenomenon is removed by the etch back.

In addition, in one embodiment of the present invention, the etch stop layer is etched at the same time as the step of etching back the second conductive layer, although the step of etching back the second conductive layer and the step of etching the etch stop layer separately may be performed. The effects of the invention remain unchanged. However, since the etch stop layer is formed as thin as 50 ~ 100 Å can be easily removed without performing a separate etching process as mentioned.

Referring to FIG. 9, it can be seen that the storage electrode 53 of the capacitor according to the exemplary embodiment of the present invention includes a storage electrode pattern 48, a conductive spacer 51, and a fin 52. In this case, the size CD of the storage electrode 53 is equal to the size of the photoresist pattern (reference numeral 46 of FIG. 7) plus the thickness of the polymer spacer and the thickness of the conductive spacer 51. ) Is more formed, the capacitance is larger than conventional.

FIG. 10 is a cross-sectional view after the second spacing layer (reference numeral 36 in FIG. 9) is removed by, for example, an isotropic process such as wet etching to form a second undercut u2.

Thereafter, a dielectric film (not shown) is formed on the exposed first and second conductive layer surfaces, and a third conductive layer (not shown) is formed on the dielectric film to complete the capacitor.

Therefore, according to the capacitor manufacturing method of the semiconductor device according to an embodiment of the present invention, even if the storage electrode is formed after the polymer spacer is formed by the polymer generating process, defects of the device due to the tearing phenomenon can be eliminated, and the pins are further added. Since it can form, a capacitor with high reliability and a large capacitance can be obtained.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with another embodiment of the present invention. The storage electrode pattern 60 is formed without forming the polymer spacer 47. One case is shown.

Even when the storage electrode pattern is formed without forming the polymer spacer, the conductive spacer (not shown, but the conductive spacer is formed on the sidewall of the storage electrode pattern since the subsequent steps are the same as described with reference to FIGS. 8, 9 and 10). Since the size (CD) of the storage electrode can be increased and pins can be formed, the tearing can be prevented and the capacitance can be increased.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

According to the method of manufacturing a capacitor of a semiconductor device according to the present invention, the damage caused by the tearing phenomenon can be eliminated by the step of etching back the second conductive layer, so that dielectric breakdown of the dielectric film can be eliminated, and the lateral thickness of the second conductive layer can be eliminated. And increase the capacitance of the capacitor by the surface area of the pin.

Claims (7)

A first step of sequentially stacking a first spacer layer, an etch stop layer, and a second spacer layer on the semiconductor substrate; Forming a contact hole for partially exposing the semiconductor substrate by sequentially etching the materials stacked on the semiconductor substrate; A third step of forming a first conductive layer on the entire surface of the resultant substrate in which the contact hole is formed; A fourth process of forming a photoresist pattern for forming a storage electrode pattern having a shape separated in units of cells on the first conductive layer; A fifth process of forming a polymer spacer on sidewalls of the photoresist pattern; A sixth step of forming a storage electrode pattern by patterning the first conductive layer using the photoresist pattern and the polymer spacer as a mask; A seventh process of isotropically etching the second spacer layer exposed between the storage electrode patterns to form a first undercut; An eighth process of forming a second conductive layer covering the entire surface of the storage electrode pattern and the first undercut; A ninth step of forming a conductive spacer on the sidewall of the storage electrode pattern by etching back the second conductive layer, and forming fins separated in units of cells in the first undercut; A tenth step of partially exposing the first spacer layer by etching the etch stop layer exposed by the fins separated by the cell unit; An eleventh process of isotropically etching the exposed first spacer layer to form a second undercut; A twelfth step of forming a dielectric film on the exposed first and second conductive layer surfaces; And And a thirteenth step of forming a third conductive layer on the entire surface of the resultant substrate. The method of claim 1, wherein after the second process, And forming an insulating spacer on the sidewalls of the contact hole. The method of claim 1, The first undercut and the second undercut is a capacitor manufacturing method of a semiconductor device, characterized in that to form a wet etching using the first separation layer and the second separation layer as an etching target, respectively. The method of claim 1, And the eighth step of etching the etch stop layer is performed simultaneously with the seventh step of etching back the second conductive layer. The method of claim 1, wherein before the first step, And a step of forming a planarization layer on the entire surface of the semiconductor substrate and a step of forming an etch stop layer on the planarization layer. The method according to any one of claims 1, 2 and 5, The first spacer layer is formed of any one of a high temperature oxide layer (HTO), plasma enhanced tetra ethyl oxy silicon (PE-TEOS), and plasma enhanced oxide layer (PE-Oxide), and the etch stop layer and the etch stop layer are silicon nitrate. Ride (SiN) and silicon oxynitride (SiON) of any one, the second separation layer is a high temperature oxide (HTO), plasma enhanced tetra ethyl oxy silicon (PE-TEOS), plasma enhanced oxide (PE- Oxide) and boron-phosphorus doped silicon glass (BPSG), and the insulating spacer is made of silicon oxy nitride, and the planarization layer is made of boron-phosphorus doped silicon glass (BPSG). Capacitor manufacturing method of a semiconductor device, characterized in that made. The method of claim 6, The first spacer layer is formed to a thickness of about 500 kPa to about 1,500 kPa, the etch stop layer is formed to a thickness of about 50 kPa to about 150 kPa, and the second spacer layer is formed to a thickness of about 2,500 kPa to about 4,000 kPa. The insulating spacer is formed to a thickness of about 250 kPa to 600 kPa, the planarization layer is formed to a thickness of about 3,000 kPa to 5,000 kPa, and the etch stop layer is formed to a thickness of about 50 kPa to 200 kPa. Capacitor manufacturing method.

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