KR0164080B1 - Storage electrode manufacturing method - Google Patents
Storage electrode manufacturing method Download PDFInfo
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- KR0164080B1 KR0164080B1 KR1019950030006A KR19950030006A KR0164080B1 KR 0164080 B1 KR0164080 B1 KR 0164080B1 KR 1019950030006 A KR1019950030006 A KR 1019950030006A KR 19950030006 A KR19950030006 A KR 19950030006A KR 0164080 B1 KR0164080 B1 KR 0164080B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 반도체기판 상부에 하부절연층과 질화막을 형성하고 저장전극 콘택마스크를 이용하여 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성한 다음, 상기 콘택홀을 통하여 상기 예정된 부분에 접속되는 제1도전층을 형성하고 그 상부에 제1,2,3,4절연막을 순차적으로 형성한 다음, 상기 콘택마스크를 이용하여 상기 제4,3,2,1절연막을 순차적으로 식각하고 상기 제1,3절연막의 식각면을 측면식각하여 홈을 형성한 다음, 전체표면상부에 제2도전층을 형성하고 저장전극마스크를 이용하여 상기 질화막을 식각장벽으로 하여 상기 질화막이 노출되도록 식각한 다음, 상기 제1,2,3,4절연막을 제거함으로써 표면적이 증가된 저장전극을 형성하고 후공정으로 고집적된 반도체소자의 정전용량을 충족시키는 캐패시터를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method of forming a storage electrode of a semiconductor device, wherein a lower insulating layer and a nitride film are formed on a semiconductor substrate, and a contact hole for exposing a predetermined portion of the semiconductor substrate is formed using a storage electrode contact mask. A first conductive layer connected to the predetermined portion is formed through the contact hole, and first, second, third and fourth insulating layers are sequentially formed thereon, and then the fourth, third, second, 1, the insulating layer is sequentially etched, and the etching surfaces of the first and third insulating layers are laterally etched to form grooves, and then a second conductive layer is formed on the entire surface, and the nitride film is etched by using a storage electrode mask. After etching to expose the nitride layer, the first, second, third and fourth insulating layers are removed to form a storage electrode having an increased surface area, and to fill the capacitance of the highly integrated semiconductor device in a later process. By forming the capacitor to improve the characteristics and reliability of the semiconductor device and technique that enables high integration of the semiconductor device thereof.
Description
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체 소자의 저장전극 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 반도체기판 2 : 소자분리절연막1: semiconductor substrate 2: device isolation insulating film
3 : 게이트산화막 4 : 소오스접합3: gate oxide film 4: source junction
5 : 게이트전극 6 : 층간절연막5 gate electrode 6 interlayer insulating film
7 : 하부절연막 8 : 질화막7: lower insulating film 8: nitride film
9 : 제1다결정실리콘막 10 : 제1절연막9: first polycrystalline silicon film 10: first insulating film
11 : 제2절연막 12 : 제3절연막11: second insulating film 12: third insulating film
13 : 제4절연막 14 : 제1감광막패턴13: fourth insulating film 14: first photosensitive film pattern
15 : 제2다결정실리콘막 16 : 제2감광막패턴15: second polycrystalline silicon film 16: second photosensitive film pattern
50 : 콘택홀50: contact hole
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 특히 저장전극의 표면적을 증가시켜 후공정에서 형성되는 캐패시터 정전용량을 향상시키기위하여 표면적이 증가된 저장전극을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a storage electrode of a semiconductor device, and in particular, to form a storage electrode having an increased surface area in order to increase the capacitance of a capacitor formed in a later process by increasing the surface area of the storage electrode. The present invention relates to a technique for improving and thereby enabling high integration of semiconductor devices.
반도체소자가 고집적화되어 셀 크기가 감소되므로, 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기 어려워지고 있다.Since the semiconductor device is highly integrated and the cell size is reduced, it is difficult to sufficiently secure a capacitance proportional to the surface area of the storage electrode.
특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서, 면적을 줄이는 것이 디램 소자의 고접적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, (Eo X Er X A) / T (단, 상기 Eo는 진공유전율, 상기 Er은 유전막의 유전율, 상기 A는 캐패시터의 면적 그리고 상기 T는 유전막의 두께)로 표시되는 캐패시터의 정전용량 C를 증가시키기 위하여, 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막을 얇게 형성하거나 또는 저장전극의 표면적을 증가시키는 등의 방법을 사용하였다.Thus, the capacitance C of the capacitor represented by (Eo X Er XA) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to achieve this, a material having a high dielectric constant is used as the dielectric film, a thin dielectric film is formed, or the surface area of the storage electrode is increased.
그러나, 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, these methods all have their problems.
즉, 높은 유전상수를 갖는 유전물질, 예를들어 Ta2O5, TiO2또는 SrTiO3등은 신뢰도 및 박막특성등이 확실하게 확인되어 있지 않다. 그래서, 실제소자에 적용하기가 어렵다. 그리고, 유전막 두께를 감소시키는 것은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.That is, the dielectric material having a high dielectric constant, such as Ta 2 O 5 , TiO 2 or SrTiO 3 , has not been confirmed with reliability and thin film characteristics. Therefore, it is difficult to apply to the actual device. In addition, reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.
또한, 저장전극의 표면적을 증가시키기위하여 삼차원구조의 저장전극을 많이 형성하였다. 그러나, 반도체소자의 고집적화에 충분히 정전용량을 확보할 수 없어 반도체소자의 고집적화를 어렵게 하는 문제점이 있었다.In addition, in order to increase the surface area of the storage electrode, many storage electrodes having a three-dimensional structure were formed. However, there is a problem that it is difficult to secure a high integration of the semiconductor device because the capacitance is not sufficiently secured for high integration of the semiconductor device.
따라서, 본 발명은 종래기술의 문제점을 해결하기위하여, 식각선택비 차이를 이용하여 표면적이 증가된 저장전극을 형성함으로써 표면적을 극대화시켜 후공정으로 반도체소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the problems of the related art, the present invention provides a storage electrode having an increased surface area by using an etching selectivity difference, thereby maximizing the surface area to form a capacitor having sufficient capacitance for high integration of semiconductor devices in a later process. The purpose of the present invention is to provide a method for forming a storage electrode of a semiconductor device capable of improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.
이상의 목적을 달성하기위한 본 발명인 반도체소자의 저장전극 형성방법의 특징은, 반도체기판 상부에 하부절연층을 형성하는 공정과, 상기 하부절연층 상부에 질화막을 형성하는 공정과, 저장전극 콘택마스크를 이용한 식각공정으로 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 예정된 부분에 접속되는 제1도전층을 형성하는 공정과, 상기 제1도전층 상부에 제1절연막, 제2절연막, 제3절연막 및 제4절연막을 순차적으로 형성하는 공정과, 상기 콘택마스크를 이용한 식각공정으로 상기 제4절연막, 제3절연막, 제2절연막 및 제1절연막을 순차적으로 건식식각하는 공정과, 상기 건식식각으로 인한 상기 제1절연막과 제3절연막의 식각면을 측면식각하여 홈을 형성하는 공정과, 전체표면상부에 제2도전층을 형성하는 공정과, 저장전극마스크를 이용한 식각공정으로 상기 질화막이 노출될때까지 식각하는 공정과, 상기 제1,2,3,4절연막을 제거하는 공정을 포함하는데 있다.Features of the method for forming a storage electrode of a semiconductor device according to the present invention for achieving the above object, the step of forming a lower insulating layer on the semiconductor substrate, the step of forming a nitride film on the lower insulating layer, and a storage electrode contact mask Forming a contact hole exposing a predetermined portion of the semiconductor substrate by an etching process, forming a first conductive layer connected to the predetermined portion through the contact hole, and forming an upper portion of the first conductive layer on the first conductive layer Sequentially forming the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film, and sequentially etching the fourth insulating film, the third insulating film, the second insulating film, and the first insulating film by an etching process using the contact mask. Etching, forming a groove by side etching the etched surfaces of the first and third insulating layers due to the dry etching, and forming a second conductive portion over the entire surface. And forming a layer, etching through a storage electrode mask until the nitride film is exposed, and removing the first, second, third and fourth insulating layers.
여기서, 상기 제1,3절연막은 상기 제2,4절연막보다 식각선택비가 우수한 절연물질로 형성되고, 상기 제1,3절연막은 피.에스.지 (PSG : Phospho Silicate Glass, 이하에서 PSG라 함)로 형성되고, 상기 제2,4절연막은 상기 1,3절연막보다 식각선택비가 낮은 절연물질로 형성되고, 상기 제2,4절연막은 비.에스.지 (BSG : Boro Silicate Glass, 이하에서 BSG라 함)로 형성되고, 상기 콘택마스크를 이용한 식각공정은 상기 제1도전층이 식각장벽으로 사용되고, 상기 저장전극마스크를 이용한 식각공정은 상기 질화막이 식각장벽으로 사용되고, 상기 저장전극 형성방법은 저장전극의 표면적을 증가시키기 위하여 상기 제1,2절연막 적층구조를 다수 적층시켜 실시되는 것이다.The first and third insulating layers may be formed of an insulating material having an etch selectivity higher than that of the second and fourth insulating layers, and the first and third insulating layers may be referred to as PSG (PSG). And the second and fourth insulating layers are formed of an insulating material having an etching selectivity lower than that of the first and third insulating layers, and the second and fourth insulating layers are formed of B. S. paper (BSG). In the etching process using the contact mask, the first conductive layer is used as an etch barrier, the etching process using the storage electrode mask is used as the etching barrier, and the storage electrode forming method is stored. In order to increase the surface area of the electrode, a plurality of first and second insulating film stacking structures are stacked.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 저장전극 형성공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a storage electrode forming process of a semiconductor device according to an exemplary embodiment of the present invention.
제1a도를 참조하면, 반도체기판(1) 상부에 하부절연층(7)을 형성한다. 이때, 상기 하부절연층(7)은 소자분리절연막(2), 게이트산화막(3), 게이트전극(5), 소오스접합(4) 및 중간절연막(6)을 형성하고 그 상부를 절연막으로 평탄화시킨 것이다. 그 다음에, 전체표면상부에 질화막(8)을 형성한다. 그리고, 저장전극 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 소오스접합(4)을 노출시키는 콘택홀(50)을 형성한다. 그리고, 상기 콘택홀(50)을 통하여 상기 소오스접합(4)에 접속되는 제1다결정실리콘막(9)을 형성한다. 그리고, 상기 제1다결정실리콘막(9) 상부에 제1절연막(10), 제2절연막(11), 제3절연막(12) 및 제4절연막(13)을 순차적으로 형성한다. 그리고, 상기 제4절연막(13) 상부에 상기 저장전극 콘택마스크를 이용한 식각공정으로 제1감광막패턴(14)을 형성한다.Referring to FIG. 1A, a lower insulating layer 7 is formed on the semiconductor substrate 1. In this case, the lower insulating layer 7 is formed by forming a device isolation insulating film 2, a gate oxide film 3, a gate electrode 5, a source junction 4, and an intermediate insulating film 6 and planarizing an upper portion thereof with an insulating film. will be. Then, a nitride film 8 is formed over the entire surface. A contact hole 50 exposing the source junction 4 is formed by an etching process using a storage electrode contact mask (not shown). Then, the first polysilicon film 9 is formed to be connected to the source junction 4 through the contact hole 50. A first insulating film 10, a second insulating film 11, a third insulating film 12, and a fourth insulating film 13 are sequentially formed on the first polycrystalline silicon film 9. The first photoresist layer pattern 14 is formed on the fourth insulating layer 13 by an etching process using the storage electrode contact mask.
여기서, 상기 제1,3절연막(10,12)은 PSG로 형성되고, 상기 제2,4절연막(11,13)은 상기 제1,3절연막(10,12)보다 식각이 잘 안되는 BSG로 형성된 것이다. 참고로, 상기 PSG와 BSG의 식각선택비는 20 : 1 이다.Here, the first and third insulating layers 10 and 12 are formed of PSG, and the second and fourth insulating layers 11 and 13 are formed of BSG which is less etched than the first and third insulating layers 10 and 12. will be. For reference, the etching selectivity of the PSG and BSG is 20: 1.
제1b도를 참조하면, 상기 제1감광막패턴(14)을 마스크로 하여 상기 제4,3,2,1절연막(13,12,11,10)을 순차적으로 건식식각한다. 그리고, 상기 제1감광막패턴(14)을 제거한다. 그리고, 식각선택비 차이를 이용한 습식방법으로 상기 제1,3절연막(10,12)을 일정깊이 측면식각한다. 이때, 상기 습식방법은 순수한 물과의 비가 9 : 1 인 BOE 용액을 이용하여 실시한 것이다. 그 다음에, 전체표면상부에 제2다결정실리콘막(15)을 일정두께 형성한다. 그리고, 그 상부에 저장전극마스크(도시안됨)을 이용한 식각공정으로 제2감광패턴(16)을 형성한다.Referring to FIG. 1B, the fourth, third, second, and first insulating layers 13, 12, 11, and 10 are sequentially dry-etched using the first photoresist pattern 14 as a mask. Then, the first photoresist pattern 14 is removed. The first and third insulating layers 10 and 12 are side-etched in a predetermined depth by a wet method using an etching selectivity difference. At this time, the wet method is performed using a BOE solution with a ratio of 9: 1 to pure water. Then, a second polycrystalline silicon film 15 is formed on the entire surface at a constant thickness. In addition, a second photosensitive pattern 16 is formed on the top thereof by an etching process using a storage electrode mask (not shown).
제1c도를 참조하면, 상기 제2감광막패턴(16)을 마스크로 하고 상기 질화막(8)을 식각장벽으로 하여 상기 질화막(8)이 노출될때까지 식각공정을 실시한다.Referring to FIG. 1C, an etching process is performed until the nitride film 8 is exposed using the second photoresist pattern 16 as a mask and the nitride film 8 as an etch barrier.
제1d도를 참조하면, 상기 제2감광막패턴(16)을 제거한다. 그리고, 상기 제1,2,3,4절연막(10,11,12,13)을 제거함으로써 표면적이 증가된 저장전극을 형성한다. 이때, 상기 제거공정은 상기 제1,2다결정실리콘막(9,15)과의 식각선택비 차이를 이용한 습식식각공정으로 실시된 것이다.Referring to FIG. 1D, the second photoresist layer pattern 16 is removed. The first, second, third, and fourth insulating layers 10, 11, 12, and 13 are removed to form storage electrodes having an increased surface area. In this case, the removal process is performed by a wet etching process using a difference in etching selectivity with the first and second polycrystalline silicon films 9 and 15.
후공정에서, 상기 저장전극의 표면에 유전체막(도시안됨)과 플레이트전극(도시안됨)을 순차적으로 형성함으로써 반도체소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성한다.In a later step, a dielectric film (not shown) and a plate electrode (not shown) are sequentially formed on the surface of the storage electrode to form a capacitor having a capacitance sufficient for high integration of the semiconductor device.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, 저장전극의 표면적을 극대화시켜 후공정으로 형성되는 캐패시터의 정전용량을 증가시켜 반도체소자의 고집적화를 가능하게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킨다.As described above, the method of forming the storage electrode of the semiconductor device according to the present invention maximizes the surface area of the storage electrode and increases the capacitance of the capacitor formed in a later process, thereby enabling high integration of the semiconductor device and thereby Improve properties and reliability.
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