KR960013644B1 - Capacitor manufacture method - Google Patents

Abstract

The method of manufacturing capacitor comprises the steps of : forming a contact hole connected to a source region and depositing a first polycrystal silicone film(8) after flattening by forming a poly-layer insulating film(20) on a first flattened insulating film(5); depositing a first insulating film(9) and a second insulating film(10); removing the second and the first insulating film(10,9); forming a second polycrystal silicone film(11); forming a polycrystal silicone spacer(11') by spacer etching of the second polycrystal silicone film(11); removing some of the second, the first insulating film(10,9) and the poly-layer insulating film(20); and forming a plate electrode by depositing a third polycrystal silicone film(13) after forming a dielectric film(12).

Description

Capacitor Manufacturing Method

1 shows the layout of the delapcell,

2 is a view showing a capacitor manufacturing process according to an embodiment of the present invention

Cross section in A-A 'direction.

* Explanation of symbols for main parts of the drawings

1: device isolation oxide film 2: gate oxide film

3: gate electrode 4: word line spacer insulating film

5: fifth insulating film 6: third insulating film

7: fourth insulating film 8: first polycrystalline silicon film

9: first insulating film 10: second insulating film

11 second polycrystalline silicon film 12 dielectric film

13: third polycrystalline silicon film 14: silicon substrate

20: multilayer insulating film 30, 50: photosensitive film pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor during a semiconductor memory device manufacturing process, and more particularly to a method of manufacturing a capacitor having a stacked structure electrode capable of ensuring a sufficient value of capacitance within a given cell size.

As the integration of devices increases and the area of unit cells decreases, the core technology that is indispensable for realizing high density devices (64 mega DRAM or more) is 0.4 micrometer (μm) or less. In addition to the photo etching technology that can be clearly distinguished, it is to secure a sufficient value of charge storage capacity in a small area.

One known method of forming a capacitor includes forming a device isolation oxide film, a gate oxide film, a gate electrode (word line), a source or a drain, a word line spacer insulating film, and a first planarization insulating film on a silicon substrate, and then again polysilicon. A plate electrode is formed by depositing a film.

However, in view of the current process capability, the conventional method has a problem that it is difficult to secure sufficient charge storage capacity which is desperately required as the device is highly integrated, and thus the reliability of the device is deteriorated.

In order to solve the above problems, the present invention has a sufficient value in a small area of less than 0.3 micrometer (μm) of the present invention, which is not easily delineated by the photolithography technique by using an indirect drawing method. An object of the present invention is to provide a method for manufacturing a capacitor that can secure a capacity of.

In order to achieve the above object, the present invention provides a method for manufacturing a capacitor on a structure planarized with a first planarization insulating film after forming a field oxide film, a gate signal, a spacer insulating film on a semiconductor substrate, and forming a MOSFET having an active region. After forming and planarizing a multi-layer insulating film on the first planarization insulating film, forming a contact hole connected to the source region and depositing a first polycrystalline silicon film on the entire surface, the first insulating film having excellent etching selectivity on the structure. And depositing a second insulating layer on top of the second insulating layer, and a third step of removing the second insulating layer and the first insulating layer at an upper portion where the first polycrystalline silicon film is in contact with the source. The second insulating film, the first insulating film, and the first polysilicon yarn are formed in the fourth step, leaving the predetermined portions of the second insulating film and the first insulating film of A fifth step of forming a polycrystalline silicon spacer by etching the spacer and separating the same into individual devices, a sixth step of removing a portion of the second insulating film, the first insulating film, and the multilayer insulating film; and forming a dielectric film on the entire structure. And forming a plate electrode by depositing a third polycrystalline silicon film.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 and 2.

Figure 1 is a layout of the DRAM cell, Figures 2a to 2g is a cross-sectional view in the direction A-A 'of FIG. 1 showing a process for forming a capacitor according to an embodiment of the present invention, one or more bit lines are omitted.

First, in FIG. 2A, a field oxide film 1, a gate insulating film 2, a gate electrode 3, a spacer insulating film 4 are formed on a silicon substrate 14, and then a MOSFET having an active region is formed. It is sectional drawing of the state planarized by the planarization insulating film 5. FIG.

FIG. 2B shows the deposition of the multilayer insulating film 20 of the third insulating film 6 and the fourth insulating film 7 on the entire structure, followed by the deposition of a TEOS film having excellent etching selectivity with the first insulating film 9, After the second insulating film 10 is deposited, the second photosensitive film pattern 30 is formed in a cross-sectional view. In this case, the second insulating film 10 must be a material having a better wet etching selectivity than the first insulating film 9, and mainly a TEOS film or a BPSG film is used. The insulating film and the polycrystalline silicon film can be repeatedly stacked as necessary, and the height of the capacitor changes according to the degree of lamination.

2C illustrates that the second insulating film 10 is dry-etched using the first photoresist film pattern 30, the first photoresist film pattern 30 is removed, and the first insulating film 9 is wet-etched, and then the second photoresist film is wet-etched. It is sectional drawing of the state which formed the pattern 50. FIG.

FIG. 2D illustrates the second photoresist layer 10, the second insulation layer 9, and the first polycrystalline silicon layer 8 are continuously dry-etched using the second photoresist layer pattern 50 to remove a predetermined portion, and then remove the photoresist layer. After removal, the second polycrystalline silicon film 11 is formed on the entire structure.

FIG. 2E is a cross-sectional view of the polycrystalline silicon spacer 11 ′ formed by etching back the second polycrystalline silicon film 11.

FIG. 2F is a cross-sectional view after wet etching the second insulating film 10, the first insulating film 9, and the fourth insulating film 7.

FIG. 2G is a cross-sectional view after completing the capacitor by forming an ONO (oxide film-nitride film-oxide film) dielectric film 12 on the structure, followed by depositing a third polycrystalline silicon film 13 to form a plate electrode.

The present invention made as described above has the effect of increasing the effective area of the capacitor by exposing the circular portion of the charge preserving electrode by using the etching selectivity to secure the phone storage capacity of sufficient size in a small area, thereby improving the reliability of the device. It is expected.

Claims (6)

After the field oxide film 1, the gate insulating film 2, the gate electrode 3, and the spacer insulating film 4 are formed on the semiconductor substrate 14 during the semiconductor memory device manufacturing process, a MOSFET having an active region is formed. In the capacitor manufacturing method on the structure planarized with the first planarization insulating film 5, the multilayer insulating film 20 is formed on the first flattening insulating film 5 and planarized to form a contact hole connected to the source region, In the first step of depositing the first polycrystalline silicon film 8 on the upper surface, the first insulating film 9 having an excellent etch selectivity is deposited on the structure, and the second insulating film 10 is further deposited on the second insulating film 10. Step 3 is a third step of removing the second insulating film 10 and the first insulating film 9 at an upper portion where the source and the first polycrystalline silicon film 8 are in contact with each other. 10 and a first portion of the second insulating film 10 and the first insulating film 9 leaving a predetermined portion of the first insulating film 9. A fourth step of forming a second polycrystalline silicon film 11 on the entire structure by continuously etching the silicon film 8 to remove a predetermined portion, and etching the second polycrystalline silicon film 11 by spacer etching the polycrystalline silicon spacer A fifth step of forming 11 'and separating the same into each device; a sixth step of removing some of the second insulating film 10, the first insulating film 9, and the multilayer insulating film 20; And forming a plate electrode by depositing a third polycrystalline silicon film (13) after the dielectric film (12) is formed on the capacitor. The method of manufacturing a capacitor according to claim 1, wherein the multi-layer insulating film 20 of the first step comprises a third insulating film 6 and a fourth insulating film 7. The method of claim 1, wherein the second insulating film (10) of the second step is a TEOS film or a BPSG film having excellent wet etching selectivity with respect to the first insulating film (9). The method of claim 1, wherein in the third step, the second insulating film 10 is dry-etched using the first photoresist film pattern 30, the first photoresist film pattern 30 is removed, and then the first insulating film 9 is removed. Capacitor manufacturing method characterized in that the wet etching. The method of claim 1, wherein the second step is performed using the second photoresist pattern 50 as an etch mask to continuously connect the second insulating film 10, the first insulating film 9, and the first polycrystalline silicon film 8. Dry etching to remove a predetermined portion, and then removing the photosensitive film, to form a second polycrystalline silicon film (11) on the entire structure. The method of claim 2, wherein in the sixth step, the fourth insulating layer is etched when the multilayer insulating layer is etched.