KR100252542B1 - Method for fabricating a storage node of dram cell - Google Patents

Abstract

PURPOSE: A method for fabricating a storage node of a DRAM cell is provided to assure process margin and maximize the surface area of a storage node to increase the storage capacitance of the storage node by enabling the contact formation in any directions. CONSTITUTION: An insulating layer(12) for smoothing is formed on a semiconductor substrate(10) including an MOS transistor. Then, a storage node contact hole is formed by etching the insulating layer. Then, a first polysilicon(13) and a first sacrifice film pattern are sequentially formed on all structure. A second polysilicon spacer(15) is formed on a sidewall of the first sacrifice film pattern. Then, a second sacrifice spacer(19) is formed on both sidewalls of the second polysilicon spacer after the first sacrifice film pattern is removed. Next, the exposed polysilicon for the first storage node. Then, a third polysilicon spacer is formed on both sidewalls of the first sacrifice spacer and the second sacrifice spacer to form a storage node formed of the first polysilicon and the second/third polysilicon spacers.

Description

DRAM cell manufacturing method

1 is a cross-sectional view of manufacturing a stack capacitor according to the prior art.

2A to 2G are cross-sectional views illustrating a process of manufacturing a DRAM cell storage electrode according to the present invention.

* Explanation of symbols for main parts of the drawings

1,10 semiconductor substrate 2: device isolation film

4 word line 8 capacitor dielectric film

9 plate electrode 10 polysilicon spacer

11 storage electrode 12 insulating film

13: polysilicon for first storage electrode 14: first sacrificial film pattern

15: Polycrystalline Silicon Spacer for Second Storage Electrode

16: second sacrificial film 17: polysilicon for third storage electrode

18: contact hole for the storage electrode 19: the second sacrificial film spacer

20: polysilicon spacer for third storage electrode

30: contact

The present invention relates to a method for manufacturing a highly integrated semiconductor device, and in particular, when forming a storage electrode in the form of a plurality of cylinders, the contact for the storage electrode is not in the center of the storage electrode, and the multiple cylinder form of the storage electrode is used for the storage electrode. It is a technology to form a high storage capacitance electrode by securing a process margin and maximizing the surface area of the storage electrode by allowing contact formation to be connected to each other in the contact to enable contact formation in any direction of the cylinder.

An important factor related to the high integration of DRAM, a semiconductor memory device, is the reduction of cell area and consequently the limitation of capacitor capacity.

A DRAM cell manufactured according to the prior art will be described with reference to FIG. 1.

FIG. 1 illustrates forming a field oxide film 2 on the semiconductor substrate 1, forming a gate insulating film 3 and a word line 4 on the exposed semiconductor substrate 1 and the device isolation layer 2. (4) After forming the oxide film spacer 5 on the sidewall, the source / drain regions 6 are formed on the semiconductor substrate 1 exposed by the impurity ion implantation process, and the planarization insulating film 7 is applied on the entire structure. A capacitor having a stack structure formed of the storage electrode 11, the dielectric film 8, and the plate electrode 9 contacted to the source / drain region 6 is formed.

However, the structure of the DRAM cell according to the related art has a limitation in increasing the capacity of the storage electrode compared to the cell size.

Accordingly, in order to solve the above problem, the present invention provides a contact formation for the storage electrodes such that the contact of the storage electrodes is not at the center of the storage electrodes and the multiple cylinders of the storage electrodes are connected to each other in the storage electrode contacts. By making it possible, the purpose is to secure a process margin and maximize the surface area of the storage electrode to form a storage electrode of high capacitance.

A feature of the present invention for achieving the above object is a step of forming a planarization insulating film on the semiconductor substrate including a MOS transistor, and by using a storage electrode contact mask to etch the insulating film for planarization of the contact region storage electrode contact hole Forming a first polycrystalline silicon layer on the entire structure, forming a first sacrificial film pattern having a predetermined thickness on the first polycrystalline silicon layer, and the first sacrificial film. Forming a second polysilicon layer spacer on a sidewall of the pattern, removing the first sacrificial film pattern, and then forming a second sacrificial film spacer on both sidewalls of the second polysilicon spacer; Removing the polysilicon for the first storage electrode, and forming a third polysilicon layer spacer on both sidewalls of the first sacrificial film spacer, Removal of the first may comprise a polycrystalline silicon layer and the second, the step of forming a storage electrode consisting of the polysilicon layer 3 spacer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2G are cross-sectional views illustrating a manufacturing process of a DRAM cell storage electrode according to the present invention.

2A shows a planarization insulating film 12 deposited on the semiconductor substrate 10 including the MOS transistor, and then a contact hole 18 for a storage electrode is formed on the silicon substrate, and polysilicon for the first storage electrode is formed thereon. It is sectional drawing which shows deposition of (13).

FIG. 2B shows the deposition of the first sacrificial film 14 to a predetermined thickness, coating the photoresist film, and forming the first sacrificial film 14 using the photoresist film as a mask by exposure and development using a mask for storage electrodes. And sectional drawing which removed the photosensitive film | membrane.

Here, the first sacrificial layer 14 is BPS (Boro-Phospho-Silicate-Glass, hereinafter referred to as BPSG), PSG (PSG: Phospho-Silicate-Glass, hereinafter referred to as PSG), USG (USG: Undoped-Silicate-Glass, hereinafter referred to as USG) and TEOS (TEOS: Tetra-Ethyl-Ortho-Silicate, hereinafter referred to as TEOS).

FIG. 2C is a cross-sectional view illustrating the formation of the second storage electrode polysilicon spacer 15 on the sidewall of the first sacrificial layer 14 by depositing and anisotropically etching polycrystalline silicon (not shown) for the second storage electrode. to be.

FIG. 2D is a cross-sectional view showing that the first sacrificial film 14 inside the second storage electrode polysilicon spacer 15 is removed and the second sacrificial film 16 is deposited on the entire structure. Here, the second sacrificial film 16 is formed of BPSG, PSG, USG, TEOS, or the like.

FIG. 2E illustrates anisotropic etching of the second sacrificial film 16 to form a second sacrificial film spacer 19, removes the exposed polycrystalline silicon 13 for the first storage electrode, and then removes the polysilicon for the third storage electrode ( 17 is a cross-sectional view showing the deposition of a certain thickness on the entire upper structure.

FIG. 2F shows anisotropic etching of the third storage electrode polycrystalline silicon 17 to form the third storage electrode polycrystalline silicon spacer 20 on the sidewall of the second sacrificial film spacer 19 and the second sacrificial film spacer 19. It is sectional drawing which removed.

FIG. 2G is a sectional view of FIG. 6 in a plan view. The storage electrode has three layers, and among the three storage electrodes made of polysilicon, the contact 30 is formed in the middle of the storage electrodes.

According to the present invention, by maximizing the area of the storage electrode in the highly integrated DRAM cell to make a storage electrode having a high capacitance, the reliability of the semiconductor device can be improved, thereby making it easy to produce expensive products.

Claims (4)

In the storage electrode manufacturing method of the DRAM cell, Forming a planarization insulating film on the semiconductor substrate including the MOS transistor; Forming a storage electrode contact hole by etching the insulating layer for planarization of the contact region by using the storage electrode contact mask; Forming a first polycrystalline silicon layer on the entire structure; Forming a first sacrificial film pattern having a predetermined thickness on the first polycrystalline silicon layer; Forming a second polysilicon layer spacer on sidewalls of the first sacrificial film pattern; Removing the first sacrificial film pattern, and then forming a second sacrificial film spacer on both side walls of the second polysilicon spacer; Removing polycrystalline silicon for the first storage electrode exposed by the process; Forming a storage electrode including the first polycrystalline silicon layer and the second and third polysilicon layer spacers by forming a third polysilicon layer spacer on both sidewalls of the first sacrificial film spacer and removing the second sacrificial layer spacer. Method for manufacturing a storage electrode of a DRAM cell comprising. The method of claim 1, The method of claim 1, wherein the edge of the first sacrificial layer pattern overlaps the storage electrode contact hole. The method of claim 1, The first and second sacrificial films are BPSG, PSG, USG or TEOS film, characterized in that the storage electrode manufacturing method of the DRAM cell. The method of claim 1, The first sacrificial layer pattern is a storage electrode manufacturing method of the DRAM cell, characterized in that formed a little thicker than the predetermined thickness of the storage electrode.