KR910008123B1 - Semiconductor memory device having stacked capacitor and method of fabricating thereof - Google Patents

Abstract

The semiconductor memory device for increasing the capacitance comprises a MOSFET formed on silicon substrate (1) and double stacked capacitor connected with drain region (6') of MOSFET. The double stacked capacitor is formed by the following steps; forming a first charge storage electrode (8), dielectric layer (9), cell plate electrode (10), dielectric layer (11), and conducting material (12') for a second charge storage electrode in sequence at drain region (6'); forming a contact hole at fixed region from the second charge storage electrode to the first (8); forming a dielectric layer (14) on upper side of the second charge storage electrode and contact hole, followed by forming a conducting material (15).

Description

Semiconductor memory device having double stacked capacitor structure and manufacturing method thereof

1 is a semiconductor memory device having a double stacked capacitor structure manufactured according to a conventional method.

2A to 2G are cross-sectional views showing a manufacturing process of a semiconductor memory device having a double stacked capacitor structure according to the present invention.

3A to 3G are cross-sectional views illustrating a manufacturing process of a semiconductor memory device having a double stacked capacitor structure in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

4 and 4 ': gate electrode and gate electrode line 6 and 6': source and drain region

8: primary charge storage electrode 12 and 16: secondary charge storage electrode

9, 11 and 14: dielectric film 15: conductive material

10 cell plate electrode 18 nitride film

17 oxide film spacer 20 oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device having a double stacked capacitor structure surrounded by charge storage electrodes at the top and bottom of a cell plate electrode, and a method of manufacturing the same. A semiconductor memory device having a double stacked capacitor structure in which a dielectric film is formed to increase a capacitor capacity, and a method of manufacturing the same.

As DRAM semiconductor memory devices have increased in density, capacitor structures have been largely classified into trench and stacked structures, and various structures have been developed so far. However, in the case of the stacked capacitor structure, the area of the unit cell is reduced due to the increase in the degree of integration, thereby reaching a limit in terms of the capacitance of the capacitor. In order to overcome the limitations of the capacitor capacity, the charge storage electrode in a single layer structure was configured with a double stacked capacitor structure surrounding the cell plate electrode up and down to increase the capacitor capacity.

In order to form the structure of the double stacked capacitor, the secondary charge storage electrode must be connected to the primary charge storage electrode through the cell plate electrode. Therefore, the size of the contact for contacting the secondary charge storage electrode and the primary charge storage electrode is excluded from the surface area of the charge storage electrode.

In the conventional method of forming a double stacked capacitor, a contact is formed on a portion of the cell plate electrode on the primary charge storage electrode to connect the secondary charge storage electrode and the primary charge storage electrode, and then the sidewall of the contact (cell plate) is formed. By forming oxide spacers on the sidewalls, the secondary charge storage electrode and the primary charge storage electrode were connected while preventing contact between the cell plate electrode and the charge storage electrode. Therefore, the surface area of the capacitor is reduced by this contact size.

Accordingly, the present invention provides a cell plate on the primary charge storage electrode to connect the primary charge storage electrode to connect the secondary charge storage electrode and the primary charge storage electrode to increase the capacitor capacity at the same area. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device having a double stacked capacitor structure formed by forming a capacitor dielectric film on a sidewall of a contact (cell plate sidewall) after forming a groove in an electrode, and a method of manufacturing the same.

Compared to the conventional method, the present invention can further increase the capacitor capacity by the side wall surface area of the contact.

Hereinafter, described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor memory device having a double stacked capacitor structure manufactured according to a conventional method, in which a device isolation oxide film 2 is formed on a silicon substrate 1, and a gate oxide film 3 and a gate conductive material are formed. Are sequentially formed to form gate electrodes and gate electrode lines 4 and 4 'by a mask pattern process, and then implant impurities into the source and drain regions 6 and 6' by ion implantation, and then the oxide film 7 is formed. A double stacked capacitor is formed over the drain region and formed on the entire region. The primary charge storage electrode 8, the dielectric film 9, the cell plate electrode 10, and the dielectric are formed on the drain region 6 ′. The film 11 and the secondary charge storage electrode 16 are sequentially formed, and a contact (groove) is formed on the cell plate electrode 10, and an oxide spacer 17 is formed on the contact (groove) wall. Next, the secondary charge storage electrode 16 is connected to the primary charge storage electrode 8 Indicates.

The conventional method is configured to be insulated from the cell plate electrode by a thick oxide film spacer 17 on the contact wall surface formed on the primary charge storage electrode, while the present invention to be described later uses a capacitor dielectric film instead of the oxide film spacer 17. It is configured to ultimately increase the capacitor surface area by forming it will be described in detail with reference to FIGS. 2a to 2g.

FIG. 2A shows that the device isolation oxide film 2 is formed on the silicon substrate 1, the gate oxide film 3 and the gate conductive material are formed, and then gate electrodes and gate electrode lines 4 and 4 'are formed, and ion implantation is performed. The source and drain regions 6 and 6 'are formed in the LDD region by the method, and the oxide film spacers 5 are formed on the sidewalls of the gate electrode 4, respectively.

2B shows an oxide film 7 having a predetermined thickness for the purpose of insulating the gate electrode 4 and the charge storage electrode to be formed later, and connecting the primary charge storage electrode 8 and the drain electrode 6 '. For this purpose, a contact is formed on the drain region 6 ', and then the primary charge storage electrode 8 is formed and the primary capacitor dielectric film 9 is formed.

FIG. 2C shows the cell plate electrode 10, the secondary capacitor dielectric film 11, and then the conductive material 12 ′ for the secondary charge storage electrode is deposited, and then the secondary charge storage electrode. In order to connect the conductive material 12 'to the primary charge storage electrode 8, a photoresist 13 for contact masks is disposed on the upper portion of the primary charge storage electrode 8 above the gate electrode line 4'. It is sectional drawing of the state formed.

FIG. 2D is a view showing the photosensitive material 13 as a mask and the conductive material 12 'for the secondary charge preservation electrode on the exposed portion of the gate electrode line 4', the secondary capacitor dielectric film 11, and the cell. The plate electrode 10 and the primary capacitor dielectric film 9 are sequentially etched, the photosensitive material 13 is removed, and the capacitor dielectric film 14 as a whole is formed to form a capacitor dielectric film on the sidewall of the cell plate electrode of the contact portion. Is a cross-sectional view of a state in which a conductive material 15 is deposited to form a capacitor and protect the capacitor dielectric film on the contact side wall.

2E shows that the conductive material 15 is anisotropically etched to form the conductive spacer 15 on the sidewall of the contact portion to protect the capacitor dielectric film 14 formed on the sidewall of the contact portion. The cross-sectional view of the capacitor dielectric film 14 above the conductive material 12 'and the capacitor dielectric film 14 below the contact are removed.

FIG. 2F shows a contact by depositing a conductive material 16 'for the secondary charge preservation electrode as a whole to connect the conductive material 12' for the secondary charge preservation electrode and the primary charge preservation electrode 8 above. It is sectional drawing of the state which connected the primary and secondary charge storage electrodes through.

FIG. 2G is a cross-sectional view of the secondary charge storage electrodes 12 and 16 formed by the mask pattern process.

After this step, an insulating layer is formed, and then a bit line is connected to the source region 6 of the MOSFET to form a protective layer to complete the semiconductor memory device.

Meanwhile, FIGS. 3A through 3G are examples of the method of manufacturing the double stacked capacitor of the present invention. Since the processes of FIGS. 2A and 2B are the same, the descriptions of FIGS. Shall be.

FIG. 3A is a cross-sectional view of the conductive material 10 'for the cell plate electrode deposited in the next process of FIG. 2B.

FIG. 3B shows the cell plate electrode 10 formed by a mask pattern process, and the upper portion of the gate electrode line 4 'to connect the secondary charge storage electrode to be formed in a later process to the primary charge storage electrode 8. A portion of the cell plate electrode 10 is etched on the upper portion of the primary charge storage electrode 8 to form a contact, and after etching the primary capacitor dielectric film 9 under the contact, the secondary capacitor as a whole is formed. It is sectional drawing of the state in which the dielectric film 11 was formed.

3C shows the photosensitive material 19 (or Polymide, or SOG) for conducting an etch back process after depositing the conductive material 12 'for the secondary charge preserving electrode and the nitride film 18 thereon. The cross section of the coated state.

3d illustrates that the etch back of the photosensitive material 19 (or polyimide or SOG) and the nitride film 20 is the same to etch back to leave the nitride film 18 only in the lower portion of the contact, and to the other portion of the nitride film ( 18 is a cross-sectional view of the thermally oxidized oxide film 20 grown on the remaining portion by removing the remaining nitride film 18 as a barrier layer.

FIG. 3E selectively selectively etches only the nitride film 18 under the contact of FIG. 3D and uses the oxide film 20 in the other portion as an etch barrier layer to form the second conductive charge preservation electrode 12 'under the contact. After etching, the cross-sectional view of the oxide film 250 on the remaining conductive material 12 'for the charge storage electrode and the secondary capacitor dielectric film 11 exposed under the contact are removed.

3f shows a state in which a conductive material 16 'for the secondary charge storage electrode is deposited to a predetermined thickness in order to connect the conductive material 12' for the secondary charge storage electrode to the primary charge storage electrode 8; It is a cross section.

3G is a cross-sectional view of the state in which the secondary charge storage electrodes 12 and 16 are formed by a mask pattern process.

The cell plate electrode of the contact portion to connect the secondary charge preservation electrode to the primary charge preservation electrode by forming a double stacked capacitor structure in which the charge preservation electrode is surrounded up and down around the cell plate electrode by the above manufacturing method. A capacitor dielectric film is formed on the sidewalls to increase the capacitor surface area by the surface area of the sidewall of the cell plate electrode, thereby increasing the capacitor capacity per unit area of the cell, thereby further reducing the area of the cell.

Claims (5)

A method of manufacturing a semiconductor memory device, comprising forming a MOSFET on a silicon substrate 1 and forming a double stacked capacitor connected to the drain region 6 'of the MOSFET, wherein the double stacked capacitor is formed. The primary charge storage electrode 8, the dielectric film 9, the cell plate electrode 10, the dielectric film 11, and the conductive material 12 for the secondary charge storage electrode are formed in the drain region 6 ′. Stacking ') and forming a contact groove in a predetermined portion from the conductive material 12' for the secondary charge storage electrode to an upper portion of the primary charge storage electrode 8; And a dielectric film 14 formed on the conductive material 12 ′ for the secondary charge storage electrode and a conductive material 15 formed thereon, and then the conductive material spacer 15 is anisotropically etched into the contact side wall. Forming an upper portion of the conductive material 12 'for the secondary charge preserving electrode and an exposed oil under the contact; The body film 14 is etched again, and the conductive material 16 ′ for the secondary charge preservation electrode is formed in the entire region, so that the secondary charge preservation electrode conductive material 16 ′ is transferred to the primary charge preservation electrode 8. And forming secondary charge storage electrodes (12 and 16) in a mask patterning process, the semiconductor memory device having a double stacked capacitor structure. The method of claim 1, wherein the forming of the double stacked capacitor comprises sequentially forming the primary charge storage electrode 8, the dielectric film 9, and the cell plate electrode 10 on the drain region 6 ′. Stacking and forming a contact on a portion of the cell plate 10 and the dielectric film 9, and then depositing a dielectric film on the cell plate 10 and the exposed first charge preservation electrode 8. 11) and forming a secondary charge preservation electrode conductive material 12 'on the dielectric layer 11 and forming a secondary charge preservation electrode conductive material 12' under the contact; Removing only the dielectric film 11, and again, the conductive material 16 'for the secondary charge storage electrode is placed on the conductive material 12' for the secondary charge storage electrode and the primary charge storage electrode 8; Depositing and connecting to the secondary charge preservation electrodes 12 'and 16' into the secondary charge preservation electrodes 12 and 16 by a mask pattern process. The semiconductor memory device manufacturing method having a two-layered structure of the capacitor comprising the comprising the steps of. 3. The method of claim 2, wherein the removing of the conductive material 12 ′ for the secondary charge preserving electrode and the dielectric layer 11 under the contact is performed on the upper portion of the conductive material 12 ′ for the secondary charge preserving electrode. Forming a nitride film 18 thereon and applying a photosensitive material 19 over the nitride film 18, and leaving only the lower contact nitride film 18 by an etch back process, leaving the conductive material 12 'for the second charge preservation electrode. Removing the upper nitride film 18 and then removing the photosensitive material 19; growing an oxide film 20 on the exposed second conductive material for the second charge storage electrode 12 '; Using the etching barrier layer 20 as the etching barrier layer, the nitride film 18 under the contact and the conductive material 12 'for the secondary charge preserving electrode under the etching are etched to expose the dielectric film 11 under the contact. A double stacked capacitor structure comprising etching the exposed dielectric film 11 and oxide film 20. The semiconductor memory device manufacturing method has. In a semiconductor memory device in which a MOSFET is formed on a silicon substrate and a double stacked capacitor is formed over the MOSFET drain region 6 ', the structure of the double stacked capacitor has a charge storage electrode (8, 12, 16) in the cell plate. Capacitor dielectric films 9 and 11 are formed between the electrodes 10 and up and down, and the charge storage electrodes 12 and 16 are connected to the drain region 6 '. It is connected to the charge preservation electrode 8, and is connected to the primary charge preservation electrode 8 connected to the drain region 6 'through a contact groove formed in a predetermined portion of the cell plate electrode 10, the contact A semiconductor memory device having a double stacked capacitor structure, wherein the dielectric film 14 is formed on the sidewalls to increase the surface area of the capacitor per unit area. 5. The double capacitor structure according to claim 4, wherein the dielectric film 11 on the cell plate electrode 10 and the dielectric film 9 on the bottom are all connected through the dielectric film 14 on the contact side wall. A semiconductor memory device having a.

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