KR910007415B1 - Semiconductor memory device and its manufacturing method with stack capacitor structure - Google Patents

Abstract

The semoconductor memory device having the stacked capacitor structure comprisess: a bit line connected with MOSFET source electrode (8) formed on silicon substrate (1); a charge storage electrode (18) connected with drain electrode (8') contacted with bit line; a capacitor dielectric film (19) and conducting material (20) for cell plate electrode formed on the charge storage electrode. The bit line is formed at lower side than stacked capacitor.

Description

Semiconductor memory device having stacked capacitor structure and manufacturing method thereof

1 is a plan view of a main mask layer required for fabricating a semiconductor memory device according to the prior art.

2 is a plan view of a main mask layer required for fabricating a semiconductor memory device according to the present invention.

3 is a cross-sectional view taken along the line a-a1 'of FIG.

4A to 4F are cross-sectional views taken along the line a-a1 'of FIG. 2 to explain the manufacturing process of the present invention. FIG. 4A is a gate oxide film and a gate conduction after forming a device isolation oxide film on a silicon substrate. Sectional view of the material and interlayer insulators deposited.

4B is a sectional view of a state in which a gate electrode, an LDD region, and a spacer are formed.

FIG. 4C is a cross-sectional view of a state in which a thin oxide film is grown in a source and a drain region, a nitride film and an oxide film as an interlayer insulator are deposited in order, and then a source contact mask is formed.

4D is a cross-sectional view of a state in which a drain contact mask is formed after depositing a bit line conductive material and an interlayer insulator after forming a bit line contact.

4E is a cross sectional view of an oxide spacer formed after removing a material from a drain contact portion;

4F is a sectional view of a state where a charge storage electrode, a dielectric film, and a cell plate electrode are formed.

* Explanation of symbols for main parts of the drawings

A: Active mask B: Gate mask

C: Drain contact mask D: Charge preservation electrode mask

E: cell plate electrode mask, F: bit line contact mask

F1 ': Bit line contact mask (Over-Size contact mask) G: Bit line mask

1: silicon substrate 2: device isolation oxide film

3: gate oxide film 4: gate electrode

5, 11 and 14: oxide film 6, 10 and 15: nitride film

7 oxide film spacer 8 source electrode

81 ': drain electrode 9: thin oxide film

12: photosensitive material 13: conductive material for bit line

16: photosensitive material 17: oxide film spacer

18: charge storage electrode 19: capacitor dielectric film

20: conductive material for cell plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device having a stacked capacitor structure and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a stacked capacitor structure in which a bit line connected to a source electrode of a MOSFET is formed below the stacked capacitor. It is about.

The prior art has formed a semiconductor memory device having a stacked capacitor structure by forming a MOSFET on a silicon substrate, forming a stacked capacitor on the drain electrode, and connecting a bit line formed thereon to the source electrode. However, the conventional technique is to perform a mask pattern process to remove a certain portion of the cell plate electrode on the source electrode, and the charge storage electrode is formed by separating the cell plate electrode so that the cell plate electrode is completely covered with the cell plate electrode and insulated from the bit line. It can be seen that the area of the cell is increased by that amount. The spacing of each cell plate electrode on the source electrode is determined by the size of the bit line contact and the pattern of the cell plate electrode.

Therefore, in order to solve the increase in the area of the unit cell of the prior art, the MOSFET is formed on the silicon substrate, and then the bit line is connected to the source electrode. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which an electrode is formed over a bit line and a contact is formed in the bit line to connect a charge storage electrode to a drain electrode, and to form a dielectric film and a cell plate electrode.

According to the present invention, a process of removing a portion of the cell plate electrode for connecting the bit line on the top of the source electrode is not necessary, and the gap between the two charge storage electrodes on the top of the source electrode can be formed by photolithography. Since the minimum spacing can be achieved, the area of the unit cell can be reduced, thereby increasing the degree of integration of the semiconductor memory device.

Hereinafter, with reference to the accompanying drawings in detail as follows.

The drawing shown here is for the convenience of a multilayer capacitor having a single layer structure, and the technique of the present invention can be applied to a multilayer capacitor having a multilayer structure. 1 is a plan view of a main mask layer superimposed on a semiconductor memory device formed according to the prior art, wherein the active mask A, the gate mask B, the drain contact mask C, and the charge storage electrode mask ( D), the cell plate electrode mask (E), the bit line contact mask (F) and the bit line mask (G) are arranged to overlap each other to indicate the spacing between the masks and the position of the portion where the contact is to be formed.

FIG. 2 is a plan view of a main mask layer for manufacturing a semiconductor memory device formed in accordance with the present invention. The masks A, B, C, D, F ', and G are arranged like FIG. Referring to FIG. 2 compared to FIG. 1, the area of the active mask A is reduced, the cell plate electrode mask (e of FIG. 1) is not used, and the bit line contact mask F ′ is formed of the charge preservation electrode mask D. FIG. And overlapped with each other, and the gap between the charge storage electrode masks D is also reduced, thereby reducing the area of the cell while maintaining the same capacitor capacity.

FIG. 3 is a cross-sectional view of the memory device having a stacked capacitor structure formed in the prior art, showing a cross section along the a-a 'axis of FIG. In this process, the device isolation oxide film 2 is formed on the silicon substrate 1, and the gate oxide film 3 and the gate conductive material are formed on the exposed silicon substrate 1 to form the gate electrode 4 as a mask pattern. To form a MOSFET.

After that, an oxide film 11 is formed as a whole, and a drain contact is formed on the drain electrode 8 ', and then a charge storage electrode conductive material is deposited on the contact and the gate electrode 4 to form a charge storage electrode. (18) is formed, the capacitor dielectric film 19 is formed thereon, and the conductive material for the cell plate electrodes is entirely deposited to form the cell plate electrodes 20 'by a mask pattern process to form a stacked capacitor. .

Next, an oxide film 14 is formed over the entire region, the bit line contact is formed on the source electrode 8, and the bit line conductive material 13 is deposited to form a bit line in a mask pattern. It is shown.

As described above, in order to connect the bit line to the source electrode 8, the charge storage electrode 18 and the cell plate electrode 20 'of the multilayer capacitor apply the design rules of the respective mast processes on the sidewalls of the bit line contacts. The area of the cell is widened by that amount.

Accordingly, the present invention has been made to solve the problem of increasing the area of the cell by changing the manufacturing process of the semiconductor memory device.

4A to 4F are cross-sectional views showing a process manufactured according to the present invention, showing a cross section along the a-a 'axis of FIG. FIG. 4A shows that the device isolation oxide film 2 is formed on the silicon substrate 1, the gate oxide film 3 and the gate conductive material 4 'are sequentially formed, and then the oxide film 5 is deposited as an interlayer insulator. An oxide film deposited on the gate conductive material 41 ′ is a cross-sectional view of the nitride film 6 formed as a etch stopping layer when the oxide film is etched to form the spacer 7 on the gate electrode sidewall. 5) and the nitride film 6 are for use in the self-alignment method when forming the bit line contact. If the self-aligning method is not used, the oxide film 5 and the nitride film 6 are not necessary.

FIG. 4B is a view illustrating a portion of the nitride film 6, the oxide film 5, and the gate conductive material 4 'in order by the mask pattern process to form the gate electrode 4, and then the source and drain electrodes 8 and 8 '), And then the oxide film spacers 7 are formed on the sidewalls of the gate electrodes 4, and the nitride films 6 are removed and the gate electrodes are formed to form the oxide film spacers 7 on the sidewalls of the gate electrodes. After the oxide film is deposited, it is anisotropically etched. At this time, the nitride film 6 is used as an etch stopping layer. The nitride film 6 on the gate electrode 6 may be left after the spacer 7 is formed.

4C shows a nitride film 10 used as an etch stop layer when a thin oxide film 9 is grown in the source and drain regions 8 and 8 ', and a portion of the oxide film 11 is etched to form a bit line contact. After the deposition, the oxidized film 11 is deposited with an interlayer insulator, and then the cross-sectional view of the photosensitive material 12 formed as an over-size contact mask is formed, wherein the nitride film 10 is a bit. It is used to self-align the line contact. When the self-alignment method is not used, the contact mask is not used but the contact mask is exposed only on the source electrode 8 and the photosensitive material 12 is gated. Cover the electrode completely. The self-alignment method here is such that the bit line contact mask F 'is overlapped on the gate electrode and the bit line is connected to the source electrode 8.

4D shows that the oxide film 11 is etched using the photosensitive material (12 in FIG. 4C) as a mask, the nitride film 10 as an etch stop layer, and the nitride film 10 is subsequently etched. The grown thin oxide film 9 is etched to expose the source electrode 8, then the bit line 13 is formed, the oxide film 14 as an interlayer insulator, and the nitride film 15 as an etch-policy layer for the oxide film. It is sectional drawing of the state which formed the photosensitive material 16 of the drain contact mask after depositing as it was.

4E shows a nitride film 15, an oxide film 14, a bit line conductive material 13, an oxide film 11, and a nitride film in a contact portion on the drain electrode 8 'with a photosensitive material (16 in FIG. 4D) as a mask. 10 and the thin oxide film 9 are sequentially etched to form a contact so that the drain electrode 8 'is exposed, and then, the photosensitive material 16 is removed and an oxide film is entirely deposited, and then the nitride film 15 Is an anisotropically etched oxide film using the etch-policy layer as a cross-sectional view of the oxide spacer 17 formed as an insulating layer between the charge storage electrode (18 in FIG. 4F) and the bit line on the sidewall of the drain contact.

4f shows the conductive material for the charge storage electrode on the contact and oxide film 14, the charge storage electrode 18 with the mask pattern, and the capacitor dielectric film 19, and then the conductive material for the cell plate electrode. As a cross-sectional view of the state in which (20) is formed, the capacitor shown here has a single layer structure for convenience, and can form a multilayered structure.

By forming the bit line first before forming the capacitor through the manufacturing process according to the present invention as described above, the interval between neighboring charge storage electrodes with the source electrode interposed therebetween can be at least the interval that can be achieved by photolithography. The required area for forming the semiconductor memory device can be reduced to increase the degree of integration of the semiconductor memory device.

Claims (6)

1. A method of manufacturing a semiconductor memory device having a stacked capacitor structure, comprising: forming a MOSFET on top of a silicon substrate 1, and then first forming a bit line connected to the MOSFET source electrode 8; A contact is formed at 8 'to connect the charge storage electrode 18 to the drain electrode 8', and a capacitor dielectric film 19 and a cell plate electrode conductive material 20 are formed thereon and stacked thereon. A method of manufacturing a semiconductor memory device having a stacked capacitor structure, comprising forming a capacitor. 2. The method of claim 1, wherein forming the bit line connected to the MOSFET source electrode 8 includes forming a nitride film 10 and an oxide film 11 over the MOSFET and gates the bit line contact mask F '. Overlapping the electrode 4 'to a predetermined upper part, etching the exposed oxide film 11 and the nitride film 10 and etching the oxide film 9 again to expose the source electrode 8, and a bit A method of manufacturing a semiconductor memory device having a stacked capacitor structure, comprising depositing a line conducting material (13) to connect a source electrode (8) to form a bit line. The method of claim 1, wherein the forming of the multilayer capacitor comprises forming the oxide film 14 and the nitride film 15 on the formed bit line, and then using the drain contact mask C. Forming a contact (groove) on the electrode 8 ', forming an oxide film as a whole, and then forming an oxide spacer 17 by anisotropic etching, and depositing a conductive material for the charge storage electrode as a whole to drain After connecting to the electrode (8 '), using the charge holding electrode mask (D) to form a charge holding electrode (18), and a capacitor dielectric film 19 formed on the charge holding electrode (18) A method of manufacturing a semiconductor memory device having a stacked capacitor structure, comprising forming a stacked capacitor by depositing a conductive material (20) for a cell plate electrode thereon. The charge preservation electrode as claimed in claim 1 or 3, wherein in the step of forming the charge preservation electrode 18, the space between the charge preservation electrode masks D is arranged at a minimum interval that can be formed by a photolithography technique. A method of manufacturing a semiconductor memory device having a stacked capacitor structure, characterized by forming a. In a semiconductor memory device having a small stacked capacitor structure in which a MOSEFT is formed on a silicon substrate 1, a stacked capacitor is connected to a drain electrode 8 ', and a bit line is connected to a source electrode 8, a silicon substrate ( 1) An oxide film spacer 7 is formed on the side wall of the gate electrode 4 of the MOSFET formed thereon, and the oxide film 5, the bit line conductive material 13, the oxide film 14, are sequentially formed on the gate electrode 4, A bit line conductive material 13 composed of a charge preserving electrode 18, a capacitor dielectric 19, and a conductive material for cell plate electrodes 20 connected through a contact on a source electrode 8 is formed thereon. An oxide film 11 and a conductive material 20 for cell plate electrodes are formed, and on the drain electrode 8 ', a charge storage electrode 18, a capacitor dielectric film 19, and a conductive material for cell plate electrodes are connected via a contact. 20 are sequentially formed, and an oxide film is formed on the contact side wall. Up of a semiconductor memory device (17) is formed having a stacked capacitor structure, characterized in that consisting of a structure formed so as to be insulated a bit-insulating conductive material 13 and the electric charge retention electrode 18. The stack according to claim 5, wherein a nitride film (10) and an oxide film (11) are formed on a portion of the gate electrode (4) between the oxide film (5) and the bit line conductive material (13). A semiconductor memory device having a capacitor structure.

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