KR930002291B1 - Method for manufacturing a dram cell - Google Patents

Abstract

The method for connecting a charge storage electre to a source electrode of a MOSFET by using a self-aligning contact method to reduce the unit cell size and to increase the surface area of the charge storage electrode comprises forming a device isolation film (2), a gate oxide film (3), a gate electrode (4), a gate electrode line (4'), and a first insulation layer on a substrate (1); forming an insulation spacer (6) on the side walls of the gate electrode and electrode line (4,4'); forming source and drain electrodes (7,7'); forming a second insulation layer (8') on to the whole substrate; forming a conduction layer (9) for a first charge storage electrode thereon, etching the layers (8',9) to form a contact groove (20); forming a conduction layer (11) for a second charge storage electrode on the groove (20) and layer (8') to form a charge storage electrode (12) by the photolighography method; and forming a capacitor dielectric film (13) and a plate electrode (14).

Description

DRAM cell manufacturing method

1A to 1D are cross-sectional views illustrating a process of manufacturing a DRAM cell according to the related art.

2a to 2e are cross-sectional views illustrating a process of manufacturing a DRAM cell according to the present invention.

* Explanation of symbols for main parts of the drawings

4 and 4 ': gate electrode and gate electrode line 9: conductive layer for first charge storage electrode

12 charge storage electrode 14 plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM cell, and more particularly, to a method for manufacturing a DRAM cell in which a charge storage electrode is connected to a source electrode of a MOSFET by a self-aligned contact method, thereby reducing the area of a unit cell and increasing the surface area of the charge storage electrode. It is about.

In the prior art, when a gate electrode and a gate electrode line are arranged to manufacture a DRAM cell, a contact region is set between the gate electrode and the gate electrode line, and the gate electrode and the gate electrode are used to form a contact groove using a contact mask. When connecting the charge preservation electrode to the source electrode between the gate electrode lines, the thickness of the insulating layer that insulates the charge preservation electrode and the gate electrode and the gate electrode line and the contact mask misalignment tolerance of the photolithography technique should be taken into consideration. When the thickness of the insulating layer is thin, the charge storage electrode and the gate electrode or the gate electrode line are shorted or a leakage current flows.

It is an object of the present invention to provide a method for fabricating a DRAM cell in which the surface area of the charge storage electrode is increased while maintaining the distance between the gate electrode and the gate electrode line at the minimum distance that can be formed by the photolithography technique.

In the DRAM cell manufacturing method of the present invention for achieving the above object, a device isolation oxide film is formed on a silicon substrate, and a gate oxide film, a conductive layer for a gate electrode and a gate electrode line, and a first insulating layer are defined on the exposed silicon substrate. Forming a gate electrode and a gate electrode line on the gate oxide film and the device isolation oxide film at a minimum line spacing using a photolithography technique and forming an insulating spacer on the sidewalls of the gate electrode and the gate electrode line using a photolithography technique; Forming a source and a rare electrode in a silicon substrate on both sides of the gate electrode, forming a second insulating layer having a predetermined thickness on the entire surface, and conducting a second charge storage electrode on the second insulating layer. Photolithography using a photoresist layer as a mask to form a layer Forming a contact groove by etching a portion of the conductive layer for the first charge preservation electrode and the second insulating layer to an upper portion of the electrode line; and forming a contact groove on the contact groove and the conductive layer for the first charge preservation electrode. Forming a conductive layer for the charge electrode, forming a charge storage electrode by photolithography technique, forming a capacitor dielectric film on the surface of the charge storage electrode, forming a conductive layer for the plate electrode as a whole, and then forming the plate electrode by photolithography technique. Characterized in that it comprises a step of forming.

According to the present invention, a gate having a first insulating layer formed thereon at a narrow interval that can be formed by an optical lithography technique without using the self-aligned contact without considering the insulating layer thickness and the misalignment effective distance of the prior art. An electrode and a gate electrode line are formed, and an insulating spacer is formed on sidewalls of the gate electrode and the gate electrode line.

A second insulating layer is formed on the first insulating layer, the insulating spacer, the source and the drain electrode, and then a conductive layer for the first charge storage electrode is formed. The contact electrode is formed from a predetermined upper portion of the gate electrode to a predetermined upper portion of the gate electrode line. The first charge storage electrode retaining conductive layer is etched. Subsequently, the second insulating layer is etched until the source electrode is exposed, and then the second conductive layer for charge storage electrode is deposited to form a self-aligned charge storage electrode conductive layer.

Therefore, it is not necessary to consider the misalignment effective distance between the conventional gate electrode and the contact mask, and the insulating spacer and the second insulating layer are formed on the side and the first and second insulating layer formed on the gate electrode and the gate electrode line, the contact Even when the second insulating layer is etched when the groove is formed, the first insulating layer and the insulating spacer maintain the insulation between the gate electrode, the gate electrode line, and the charge storage electrode.

On the other hand, as the gap between the gate electrode and the gate electrode line is narrowed, the area of the charge storage electrode decreases, so that the capacitor capacity is also reduced. In order to increase the capacitor capacity, the method of increasing the surface area of the charge storage electrode in the same area Should be provided. For example, when the thickness of the charge storage electrode is increased, the thickness of the side surface increases, thereby increasing the surface area of the entire charge storage electrode. However, when the charge storage electrode is too thick, the planarization phenomenon of the conductive layer for the charge storage electrode occurs in the contact grooves connected to the source electrode, so that even if the thickness of the charge storage electrode becomes thick, the surface area does not actually increase.

Therefore, in order to secure this, in the present invention, the thickness of the conductive layer for the first charge storage electrode is formed to be thick, and the conductive layer for the second charge storage electrode is removed after removing the conductive layer for the first charge storage electrode. By forming at least a thin thickness, the planarization phenomenon was removed from the contact grooves, and the edge of the charge storage electrode was thickened to increase the surface area of the charge storage electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1D are cross-sectional views illustrating a process of manufacturing a DRAM cell according to the prior art, and FIG. 1A illustrates a device isolation oxide film 2 formed on a portion of a silicon substrate 1 and is formed on the silicon substrate 1. After forming the gate oxide film 3 and the conductive layer for a gate electrode (not shown) sequentially, the insulating layer thickness and the contact mask misalignment effective distance for insulating the charge storage electrode to be contacted later between the gate electrode and the gate electrode line are considered. To form the gate electrode 4 and the gate electrode line 4 'by photolithography, and then to form an insulating spacer 6 on the side walls of the gate electrode and the gate electrode line 4 and 4', and to obtain a source by an ion implantation process. It is sectional drawing of the state in which the electrode 7 and the drain electrode 7 'were formed in the exposed silicon substrate 1. As shown in FIG.

FIG. 1B shows the entirety of the insulating layer 8 'and the conductive layer 9 for the first charge preservation electrode having a predetermined thickness on the insulating layer 8' and the photolithography technique, that is, the positive photoresist film 10. Cross-sectional view of the state in which the photosensitive film 10 of the exposed area | region was removed by exposing the said photosensitive film 10 between the said gate electrode and the gate electrode lines 4 and 4 'after apply | coating on the conductive layer 9, and arranging a contact mask. to be.

In FIG. 1C, the conductive layer 9 for the first charge preservation electrode is exposed by removing the photoresist film 10, and the exposed insulating layer 8 ′ is etched to expose the source electrode 7 to expose the contact grooves. (20), the photosensitive film 10 is completely removed, and the second conductive layer for conserving electrode 11 is deposited to electrically transfer the first conductive layer for conserving electrode 9 to the source electrode 7. It is sectional drawing of the state connected. In the case of thickly depositing the conductive layer 11 for the second charge storage electrode, the conductive layer 11 for the second charge storage electrode is completely filled in the contact groove 20 on the source electrode 7 so that the charge storage electrode 30 will reduce the surface area.

FIG. 1D illustrates the first and second charge storage electrode conductive layers 9 and 11 by photolithography to form a charge storage electrode 12 and a capacitor dielectric film 13 on the surface thereof. It is sectional drawing of the state in which the plate electrode 14 was formed by depositing the electroconductive layer for plate electrodes as a whole, and patterning it by the photolithography technique.

As described above, when the contact is formed on the source electrode, the gate electrode and the gate electrode line are arranged in consideration of the misalignment effective distance of the contact mask and the insulating layer thickness, and the first and second charges are increased to increase the surface area of the charge storage electrode. When the conductive layer for the storage electrode is thickened, it is flattened in the contact grooves, resulting in a decrease in surface area.

2A to 2G are cross-sectional views illustrating a process of manufacturing a multilayer capacitor according to the present invention, which solves the problems of the prior art.

2A illustrates a device isolation oxide film 2 formed on a portion of the silicon substrate 1 using a known technique, a gate oxide film 3 formed on the exposed silicon substrate 1, and the gate oxide film 3. And a gate electrode, a conductive layer 4A for gate electrode lines, and a first insulating layer 5 are sequentially formed on the device isolation oxide film 2.

FIG. 2B shows the gate electrode 4 and the gate electrode line 4 'formed by patterning at the minimum intervals that can be formed by the photolithography technique, and then used in a known technique to form an insulating layer for spacer as a whole. To form an insulating spacer 6 only on the sidewalls of the gate electrode 4 and the gate electrode line 4 'and the insulating layer 5 by an etching process, and source and drain electrodes 7 by an ion implantation process to the exposed silicon substrate 1. And 7 ').

FIG. 2C illustrates a second insulating layer having a predetermined thickness on the source and drain electrodes 7 and 7 ', the insulating spacer 6, the first insulating layer 5, and the element isolation oxide film 2 as a technique of the present invention. 8) For example, an oxide film or the like is deposited, and then a conductive layer 9 for the first charge storage electrode is deposited on the second insulating layer 8 to a predetermined thickness thicker than that before, and then a photolithography technique, that is, positive The photosensitive film 10 is coated and exposed using a contact mask, but the photosensitive film 10 is exposed by exposing the photoresist 10 to an upper portion of the source electrode 7 and a predetermined upper portion of the gate electrode line 4 'from a predetermined upper portion of the gate electrode 4. It is sectional drawing of the state remove | eliminated (10).

In FIG. 2D, the contact layer 20 is formed by etching the conductive layer 9 for the first charge storage electrode exposed by the process and subsequently etching the second insulating layer 8 so that the source electrode 7 is exposed. After removing the remaining photoresist film 10, the conductive layer 11 for the first charge preservation electrode, the source electrode 7, and the insulating spacer 6 have a predetermined thickness. (Thinner than conventionally), and deposited and insulated from the gate electrode and the gate electrode lines 4 and 4 'by the insulating spacer 6 and the first insulating layer 5, the conductive layer for the first charge storage electrode 9 Is a cross-sectional view of a state in which the source electrode 7 is electrically connected.

Here, conventionally, when the contact mask is arranged between the gate electrode 4 and the gate electrode line 4 ', an insulating layer thickness and a misalignment effective distance to insulate the conductive layer for the second charge storage electrode formed later are determined. However, in the present invention, the thickness of the insulating layer that can be insulated from the conductive layer 11 for the second charge preservation electrode and the gate electrode and the gate electrode lines 4 and 4 ′ formed later is determined when the contact groove 20 is formed. Even if the insulating layer 8 is etched, the self-aligned insulating state can be maintained by the first insulating layer 5 and the insulating spacer 6 which are already formed, and the contact masks can be gate electrodes and gate electrode lines 4 and 4 '. Since it is arranged on the top, it is not necessary to consider the misalignment effective distance of contact mask.

FIG. 2E shows the charge preservation electrode 12 by patterning the first and second charge preservation electrode conductive layers 9 and 11 by photolithography using a known technique, and then the surface area of the charge preservation electrode 12. A capacitor dielectric film 13 is formed in a predetermined thickness, and a plate electrode conductive layer is deposited as a whole, and then patterned by photolithography to form a plate electrode 14.

As described above, when arranging the gate electrode and the gate electrode line, the photolithography technique can form the minimum spacing and reduce the area of the DRAM cell, and the capacitor capacity reduced by the reduced area is the edge of the charge storage electrode. It can be solved by increasing the surface area of the charge preservation electrode by making the center portion thin and making the thickness thinner, thereby increasing the integration of DRAM cells.

Claims (3)

A method of fabricating a DRAM cell, comprising: forming a device isolation oxide film on a portion of a silicon substrate, and forming a gate oxide film, a conductive layer for a gate electrode, a gate electrode line, and a first insulating layer on an exposed silicon substrate, and forming a predetermined thickness, and an optical lithography technique. Forming a gate electrode and a gate electrode line on the gate oxide film and the device isolation oxide film with a minimum line width, and forming insulating spaces on sidewalls of the gate electrode and the gate electrode line, and a source in the silicon substrate on both sides of the gate electrode. And forming a drain electrode, forming a second insulating layer having a predetermined thickness on the entire surface thereof, forming a second conductive layer for storing a charge on the second insulating layer, and forming a photoresist mask on the gate electrode. And a conductive layer for forming the first charge storage electrode and a second layer arranged on a predetermined portion of the gate electrode line. Etching a portion of the soft layer, wherein the exposed first insulating layer and the insulating spacer are continuously etched to form a contact groove by self-aligned contact, and forming contact grooves for the contact groove and the first charge storage electrode. Forming a conductive layer for a second charge storage electrode on the conductive layer, forming a charge storage electrode by photolithography, forming a capacitor dielectric film on the surface of the charge storage electrode, and forming a conductive layer for a plate electrode as a whole. And forming a plate electrode by a photolithography technique. The method of manufacturing a DRAM cell according to claim 1, wherein the thickness of the conductive layer for the first charge storage electrode is larger than the thickness of the conductive layer for the second charge storage electrode to increase the surface area of the charge storage electrode. The method of claim 1, wherein the second insulating layer is an oxide film.

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