KR960005575B1 - Method for forming a capacitor of semiconductor device - Google Patents
Method for forming a capacitor of semiconductor device Download PDFInfo
- Publication number
- KR960005575B1 KR960005575B1 KR1019920027309A KR920027309A KR960005575B1 KR 960005575 B1 KR960005575 B1 KR 960005575B1 KR 1019920027309 A KR1019920027309 A KR 1019920027309A KR 920027309 A KR920027309 A KR 920027309A KR 960005575 B1 KR960005575 B1 KR 960005575B1
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- South Korea
- Prior art keywords
- oxide layer
- oxide film
- insulating oxide
- dual
- source
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000003990 capacitor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000009977 dual effect Effects 0.000 claims description 13
- 238000004321 preservation Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000003860 storage Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
제 1 도는 종래의 반도체 소자 캐패시터 구조도.1 is a structure diagram of a conventional semiconductor device capacitor.
제 2 도는 본 발명에 따른 반도체 소자 캐패시터 제조 공정도.2 is a process diagram of manufacturing a semiconductor device capacitor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21 : 반도체 기판 12, 22 : 필드 산화막11, 21: semiconductor substrate 12, 22: field oxide film
13, 23 : 게이트 산화막 14, 25 : 게이트 전극13, 23: gate oxide film 14, 25: gate electrode
15, 25 : 소오스/드레인 영역 16, 26 : 스페이서 산화막15, 25: source / drain regions 16, 26: spacer oxide film
17, 27 : 절연산화막 19, 29 : 전하보존용 전도물질17, 27: insulating oxide film 19, 29: conductive material for charge preservation
28 : 이중성 레지스터(dual-tone resist)28: dual-tone resist
본 발명은 반도체 소자의 캐패시터 형성 방법에 관한 것이다.The present invention relates to a method for forming a capacitor of a semiconductor device.
일반적인 반도체 소자의 캐패시터는 적은 면적에도 불구하고 캐패시턴스 용량이 증가되어야 한다. 이러한 상충되는 문제점을 해결하기 위하여 트렌치(trench)형 및 적층형이 사용되어 최대한의 캐패시터용량을 증가시켜 오고 있다.Capacitors in typical semiconductor devices require increased capacitance capacity despite their small area. In order to solve such conflicting problems, trench type and stacked type have been used to increase the maximum capacitor capacity.
종래의 반도체 소자 캐패시터를 제 1 도를 통하여 상세히 설명하면, 도면에서 11은 반도체 기판, 12는 필드 산화막, 13은 게이트 산화막, 14는 게이트 전극, 15는 소오스/드레인 영역, 16은 스페이서 산화막, 17은 절연산화막, 19는 전하보존용 전도물질을 각각 나타낸다.Referring to FIG. 1, a semiconductor substrate, 12 is a field oxide film, 12 is a gate oxide film, 14 is a gate electrode, 15 is a source / drain region, 16 is a spacer oxide film, and FIG. Silver insulating oxide film, 19 represents a charge storage conductive material, respectively.
먼저, 반도체 기판(11) 상에 필드 산화막(12)을 형성하고, 게이트 산화막(13), 게이트 전극(14), 스페이서 산화막(16), 소오스 및 드레인 영역(15)을 형성한 다음에 절연산화막(17)을 증착하여 상기 소오스 및 드레인 영역(15) 상부의 절연산화막(17)을 식각하여 전하보존용 전도물질(19)을 형성한다.First, the field oxide film 12 is formed on the semiconductor substrate 11, the gate oxide film 13, the gate electrode 14, the spacer oxide film 16, the source and drain regions 15 are formed, and then the insulating oxide film is formed. (17) is deposited to etch the insulating oxide film 17 over the source and drain regions 15 to form a charge preservation conductive material 19.
상기 종래와 같은 방법으로 형성되는 전하보존전극은 평면상에 형성되어 고집적화에 따른 단위 셀(cell)의 면적 축소시에는 캐패시턴스 측면으로 한게에 부딪히게 되는 문제점이 있었다.The charge storage electrode formed by the conventional method has a problem in that the charge storage electrode is formed on a flat surface and hits the side toward the capacitance side when the area of the unit cell is reduced due to high integration.
상기 문제점을 해결하기 위하여 안출된 본 발명은 단위 셀의 면적이 축소되어 지는 고집적 소자에 적용할 수 있는 반도체 소자의 캐패시터 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a capacitor of a semiconductor device that can be applied to a high-density device in which the unit cell area is reduced.
상기 목적을 달성하기 위하여 본 발명은, 반도체 기판에 필드 산화막을 형성한 후에 게이트 산화막, 게이트 전극, 상기 게이트 전극의 측벽에 형성되는 스페이서 산호막, 이온 주입에 의한 소오스/드레인 영역을 형성하고 절연 산화막을 증착하는 제 1 단계, 상기 제 1 단계 후에 이중성 레지스트(dual-tone resist)를 도포하여 광대역의 자외선을 노광시켜 현상한 다음 소오스/드레인 영역 상부의 절연 산화막을 식각에 의해 오픈(open) 하는 제 2 단계 후에현상된 상기 이중성 레지스트를 마스크로 하여 오픈된 상기 절연 산화막을 식각하는 제 3 단계, 상기 제 3 단계 후에 상기 이중성 레지스트를 재 노광시켜 산화막의 요철 형성부위를 제외한 상기 이중성 레지스트를 제거하여 절연산화막을 노출시키는 제 4 단계, 상기 제 4 단계 후에 상기 노출된 절연 산화막을 식각하여 소오스/드레인 영역이 드러나도록 한 다음에 잔류된 상기 이중성 레지스트 제거하고 전하보존용 전도물질을 증착하여 패턴하는 제 5 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a gate oxide film, a gate electrode, a spacer coral film formed on the sidewall of the gate electrode, a source / drain region by ion implantation, and an insulating oxide film after the field oxide film is formed on the semiconductor substrate. After the first step of depositing, after the first step to apply a dual-tone resist (dual-tone resist) to expose the ultraviolet rays of the broadband to develop and then to open the insulating oxide film on the source / drain region by etching (open) A third step of etching the insulating oxide film opened using the dual resist developed after the second step as a mask, and after the third step, the dual resist is re-exposed to remove the dual resist except for the uneven portions of the oxide film Exposing the exposed oxide film after the fourth step of exposing the oxide film; And etching to expose the source / drain regions, and then removing the remaining dual resist and depositing and patterning a charge preservation conductive material.
이하, 첨부된 도면 제 2 도를 참조하여 본 발명에 따른 일실시예를 상세히 설명하면, 도면에서 21은 반도체 기판, 22는 필드산화막, 23은 게이트 산화막, 24는 게이트 전극, 25는 소오스/드레인 영역, 26은 스페이서 산화막, 27은 절연산화막, 28은 이중성 레지스트, 29는 전하보존용 전도물질을 각각 나타낸다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 2. In the drawings, 21 is a semiconductor substrate, 22 is a field oxide film, 23 is a gate oxide film, 24 is a gate electrode, and 25 is a source / drain. The region 26 is a spacer oxide film, 27 is an insulating oxide film, 28 is a dual resist, and 29 is a charge storage conductive material.
제 2(a) 도는 반도체 기판(21)에 필드산화막(22), 게이트 산화막(23), 게이트 전극(24), 상기 게이트 전극(24)의 측벽에 형성되는 스페이서 산화막(26), 이온 주입에 의한 소오스/드레인 영역(25)을 형성하고 절연 산화막(27)을 증착한 상태의 단면도이다.The field oxide film 22, the gate oxide film 23, the gate electrode 24, the spacer oxide film 26 formed on the sidewalls of the gate electrode 24, and ion implantation in the second (a) or semiconductor substrate 21 It is sectional drawing of the state which formed the source / drain area | region 25 and the insulating oxide film 27 was deposited.
제 2(b) 도는 이중성 레지스트(28)를 증착한 다음에 광대역의 자외선을 노광시켜 현상하여 소오스/드레인 영역(25) 상부의 절연산화막(27)을 오픈(open)한 상태의 단면도이다.FIG. 2 (b) is a cross-sectional view of the insulating oxide film 27 on the source / drain region 25 opened after the dual resist 28 is deposited and developed by exposing broadband ultraviolet rays.
제 2(c) 도는 현상된 상기 이중성 레지스트(28)를 마스크로 하여 오픈된 상기 절연 산화막(27)을 노출한 상태의 단면도이다.FIG. 2 (c) is a cross-sectional view of the insulating oxide film 27 that is opened by using the developed dual resist 28 as a mask.
제 2(d) 도는 상기 이중성 레지스트(28)를 재 노광시키는 상태의 단면도이다.FIG. 2D is a cross-sectional view of a state in which the dual resist 28 is reexposed.
제 2(e) 도는 상기 이중성 레지스트(28)의 불필요한 부분을 제거하여 절연 산화막(27)을 노출한 상태의 단면도이다.2E is a cross-sectional view of the insulating oxide film 27 exposed by removing unnecessary portions of the dual resist 28.
제 2(f) 도는 상기 노출된 절연산화막(27)을 건식식각하여 소정부위의 소오스/드레인 영역(25)이 드러나도록 한다음에 감광막(28)을 제거하고 전하보존용 전도물질(29)을 증착하여 일정크기로 형성한 상태의 단면도이다.In FIG. 2 (f), the exposed insulating oxide layer 27 is dry etched to expose the source / drain regions 25 at predetermined portions, and then the photoresist layer 28 is removed and a charge preservation conductive material 29 is deposited. It is sectional drawing of the state formed in fixed size.
이때 상기 제 1(c) 도에서 절연산화막(27)이 절반두께가 이미 식각되어 있는 소오스/드레인 영역(25) 상부의 절연산화막(27)은 완전히 식각되어 소오스/드레인 영역(25)을 노출시키게 되고, 나머지 부위는 절반두께 그대로 남아있게 된다.In this case, the insulating oxide layer 27 on the source / drain region 25 in which the insulating oxide layer 27 is etched at half thickness is completely etched to expose the source / drain region 25 in FIG. The remaining part remains half the thickness.
상기와 같이 이루어지는 본 발명은 이중성 레지스터를 사용하여 자기정렬된 요철을 절연 산화막위에 형성시킴으로써 반도체 소자의 캐패시터를 증대시키는 효과가 있다.The present invention made as described above has the effect of increasing the capacitor of the semiconductor element by forming self-aligned irregularities on the insulating oxide film using a dual resistor.
Claims (2)
Priority Applications (1)
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KR1019920027309A KR960005575B1 (en) | 1992-12-31 | 1992-12-31 | Method for forming a capacitor of semiconductor device |
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KR1019920027309A KR960005575B1 (en) | 1992-12-31 | 1992-12-31 | Method for forming a capacitor of semiconductor device |
Publications (2)
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KR940016804A KR940016804A (en) | 1994-07-25 |
KR960005575B1 true KR960005575B1 (en) | 1996-04-26 |
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KR1019920027309A KR960005575B1 (en) | 1992-12-31 | 1992-12-31 | Method for forming a capacitor of semiconductor device |
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KR100328451B1 (en) * | 1995-10-13 | 2002-08-08 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
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