KR960003779B1

KR960003779B1 - Stack capacitor manufacture of semiconductor device

Info

Publication number: KR960003779B1
Application number: KR1019920019031A
Authority: KR
Inventors: 정양희
Original assignee: 금성일렉트론주식회사; 문정환
Priority date: 1992-10-16
Filing date: 1992-10-16
Publication date: 1996-03-22
Also published as: KR940010344A

Abstract

The title method comprises (A) forming a polycide for bit line on the surface of the film after forming field oxide film on silicon substrate, gate and gate side wall, (B) forming bit line between active regions of the gate, and forming nitride film for isolating the node poly to surround the bit line and the gate, (C) forming oxide film on the surface and etching the oxide film selectively by 2 steps, and (D) forming photoresist for node, dielectrics(such as Ta2O5 etc.) and polysilicon for plate by turns.

Description

Manufacturing method of multilayer capacitor of semiconductor device

제 1 도는 종래의 커패시터 공정 단면도.1 is a cross-sectional view of a conventional capacitor process.

제 2 도는 본 발명의 커패시터 공정 단면도.2 is a cross-sectional view of a capacitor process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 게이트 4 : 측벽3: gate 4: side wall

11 : 폴리사이드 12,15,16,17,20 : 포토레지스트11 polyside 12,15,16,17,20 photoresist

13 : 질화막 14 : 산화막13 nitride film 14 oxide film

15a,19 : 폴리실리콘 18 : 유전체15a, 19: polysilicon 18: dielectric

본 발명은 16메가 디램급의 고집적회로에 적당하도록 한 반도체 소자의 적층형 커패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a multilayer capacitor of a semiconductor device, which is suitable for a 16 mega DRAM high integrated circuit.

종래의 적층형 커패시터 제조공정을 제 1 도를 참고로 하여 설명하면 다음과 같다.A conventional multilayer capacitor manufacturing process will be described with reference to FIG. 1 as follows.

먼저(a)와 같이 실리콘 기판(1)에 필드산화막(2)을 형성하여 액티브영역과 필드영역을 한정한후 전면에 게이트용 폴리실리콘을 증착하여 사진각각 공정에 의해, 패터닝(Patterning) 하므로 게이트(13)을 형성한다.First, as shown in (a), the field oxide film 2 is formed on the silicon substrate 1 to define the active region and the field region, and then polysilicon for gate is deposited on the entire surface to be patterned by photolithography. 13).

다음에 (b)와 같이 전면에 절연용 산화막(5)을 형성하고 포토레지스트(6)을 사용하여 (c)와 같이 노드콘택을 형성한다.Next, an insulating oxide film 5 is formed on the entire surface as shown in (b), and a node contact is formed as shown in (c) using the photoresist 6.

이어서 (d)와 같이 전면에 노드용 폴리실리콘(6)을 증착하고 다시 포토레지스트(7)를 사용하여 (e)와 같이 포토레지스트(6)를 선택적 식각하므로 노드를 형성한다.Subsequently, the node polysilicon 6 is deposited on the front surface as shown in (d), and the photoresist 6 is selectively etched as shown in (e) using the photoresist 7 to form a node.

또한, (f)와 같이 산화막-질화막-산화막의 다층구조로 된 유전체(8)를 전면에 형성하고 다시 전면에 플레이트용 포토레지스트(9)를 증착한다.Further, as shown in (f), a dielectric 8 having a multilayer structure of an oxide film-nitride film-oxide film is formed on the entire surface, and the plate photoresist 9 is deposited on the entire surface.

그리고 포토레지스트(10)를 사용하여 폴리실리콘(9)을 선택적으로 식각하므로 (g)같이 커패시터를 완성한다.Since the polysilicon 9 is selectively etched using the photoresist 10, the capacitor is completed as shown in (g).

그러나, 상기와 같은 종래의 커패시터 공정에 있어서는 다음과 같은 몇가지 단점이 있다.However, there are some disadvantages in the conventional capacitor process as described above.

첫째, 유전체(8)로 산화막-질화막-산화막의 다층구조를 사용하고 있으며 면적 증대에 따른 용량증대를 위해 단순 계단형 커패시터를 갖고 있으므로 커패시터 용량증대에 한계가 있다.First, since the multilayer structure of the oxide film-nitride film-oxide film is used as the dielectric 8 and has a simple stepped capacitor to increase the capacity according to the area increase, the capacitor capacity increase is limited.

둘째, 유전체(8)의 산화막-질화막-산화막 형성에 따른 막질내 생성트랩이 증대된다.Second, the generation trap in the film quality due to the formation of the oxide film-nitride film-oxide film of the dielectric 8 is increased.

셋째, 유전체(8)를 이루는 질화막은 핀홀현상 및 트랩밀도의 증대로 커패시터의 용량을 증대하기가 어렵다.Third, the nitride film constituting the dielectric 8 is difficult to increase the capacitance of the capacitor due to the pinhole phenomenon and the increase in trap density.

본 발명은 이와같은 종래의 제반결점을 해결하기 위한 것으로 유전체로 산화막-질화막-산화막을 사용하지 않고 Ta₂O₅를 사용하여 커패시터의 용량을 증대시킬 수 있는 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a manufacturing method capable of increasing the capacity of a capacitor by using Ta ₂ O ₅ without using an oxide film-nitride film-oxide film as a dielectric to solve the above-mentioned general defects.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명의 공정단면도로 (a)와 같이 실리콘기판(1)에 필드산화막(2)을 형성하여 필드영역과 액티브영역을 한정하고 전면에 게이트용 폴리실리콘을 증착하여 사진식각 공정에 의해 패터닝하므로 게이트(3)를 형성한다. 그리고 전면에 산화막을 형성하고 식각하므로 게이트 측벽(4)을 형성한다.2 is a process cross-sectional view of the present invention as shown in (a) to form a field oxide film 2 on a silicon substrate 1 to define a field region and an active region, and to deposit a gate polysilicon on the entire surface by a photolithography process. Patterning forms the gate 3. In addition, an oxide film is formed on the entire surface and etched to form a gate sidewall 4.

다음에 전면에 폴리사이드(11)를 형성하고 포토레지스트(12)를 사용하여 (b)와 같이 폴리사이트(11)를 선택적 식각한후 노드폴리와의 격리를 위한 질화막(13)을 형성하여 패터닝한다.Next, the polyside 11 is formed on the entire surface, and the photoresist 12 is used to selectively etch the polysite 11 as shown in (b), and then the nitride film 13 for isolation from the node poly is formed and patterned. do.

이어서 (c)와 같이 전면에 산화막(14)을 형성하고 포토레지스트(15)를 사용하여 선택적 식각하므로 (d)와 같이 잔존하는 폴리사이드(11)위와 칠드산화막(2)위에만 산화막(14)이 남게한다.Subsequently, the oxide film 14 is formed on the entire surface as shown in (c) and is selectively etched using the photoresist 15, so that the oxide film 14 is disposed only on the remaining polysides 11 and the chilled oxide film 2 as shown in (d). This will leave.

이상태에서 (e)와 같이 다시 포토레지스트(16)를 사용하여 2차로 산화막(14)을 선택적으로 식각하면 (f)와 같은 모양이 된다.In this state, if the oxide film 14 is selectively etched using the photoresist 16 again as shown in (e), the shape becomes as shown in (f).

다음에 (g)와 같이 전면에 노드용 폴리실리콘(15a)을 형성하고 포토레지스트(17)를 사용하여 폴리실리콘(15a)을 선택적으로 식각한다.Next, as shown in (g), the polysilicon 15a for the node is formed on the entire surface, and the polysilicon 15a is selectively etched using the photoresist 17.

또한 (h)와 같이 전면에 유전율이 기존보다 1.7배이상 높은 유전체(예를들어 Ta₂O₅)(18)를 Ta(OC₂H₅)를 이용하여 400±10℃에서 LPCVD로 30∼40Å 증착하고 누설전류 및 전연 특성을 개선시키기 위해 증착된 막질을 열처리한다.In addition, as shown in (h), a dielectric material (for example, Ta ₂ O ₅ ) (18) having a dielectric constant of 1.7 times or more on the front surface is 30 to 40Å by LPCVD at 400 ± 10 ° C. using Ta (OC ₂ H ₅ ). The deposited film is heat treated to improve leakage current and edge properties.

이때의 열처리방법은 자외선 오존으로 300℃에서 3분간 열처리하며 드라이(Dry) O₂를 이용하여 900℃에서 10초의 2단계 열처리를 실시한다.At this time, the heat treatment method is heat-treated at 300 ° C. for 3 minutes with ultraviolet ozone, and performs a two-step heat treatment at 10 ° C. at 900 ° C. using dry O ₂ .

상기 유전체(18)위에 플레이트용 폴리실리콘(19)을 형성한후 포토레지스트(20)를 사용하여 폴리실리콘(19)을 식각하므로 (I)와 같이 커패시터를 완성한다.After the polysilicon 19 for the plate is formed on the dielectric 18, the polysilicon 19 is etched using the photoresist 20 to complete the capacitor as shown in (I).

이상과 같이 제조되는 본 발명은 다음과 같은 효과가 있다.The present invention manufactured as described above has the following effects.

첫째, 유전체(18)로서 유전율이 기존의 질화막보다 1.7배이상 높은 Ta₂O₅를 사용하므로 커패시터의 용량을 증대시킬 수 있다.First, since the dielectric constant 18 using Ta ₂ O _5, which is 1.7 times higher than that of the conventional nitride film, the capacity of the capacitor can be increased.

둘째, 산화막(14)을 이용한 단면적증대의 효과로 기존에 비해 훨씬 큰 커패시터 용량을 확보할 수 있다.Second, due to the effect of increasing the cross-sectional area using the oxide film 14, it is possible to secure a much larger capacitor capacity than conventional.

셋째, 비트라인으로 폴리사이드(11)를 형성하고 그위에 질화막(13)을 증착하기 때문에 산화막(14)을 증착시 두께를 고르게 증착할 수 있고 산화막(14) 식각시 비트라인과 쇼트되는 것을 방지할 수 있다.Third, since the polyside 11 is formed as a bit line and the nitride film 13 is deposited thereon, the thickness of the oxide film 14 can be evenly deposited when the oxide film 14 is deposited, and the short film is prevented from being shorted with the bit line when the oxide film 14 is etched. can do.

Claims

After forming the field oxide film 2 on the silicon substrate 1, forming the gate 3 and the gate sidewall 4, and forming the bit line polyside 11 on the front surface, and the gate 3 of the active region ) Forming a bit line between the layers and forming a nitride film 13 for isolation of the node poly to enclose the bit line and the gate 3, forming an oxide film 14 on the entire surface, and forming the oxide film 14 in two steps. And selectively etching, and forming a capacitor by sequentially forming a photoresist 15a for a node, a dielectric 18, and a polysilicon 19 for a plate on a front surface thereof. Capacitor manufacturing method.

The method of claim 1, wherein Ta ₂ O ₅ is used as the dielectric material.

According to claim 2, The Ta ₂ O _{5 It} is deposited 30 ~ 40Å by LPCVD at 400 ± 10 ℃ using Ta (OC ₂ H ₅ ), heat treatment at 300 ℃ with ultraviolet ozone for 3 minutes and using dry O ₂ 10. A method of manufacturing a multilayer capacitor of a semiconductor device, characterized in that formed by heat treatment at 900 ℃ for 10 seconds.