KR100217920B1 - Fabricating method for bit line in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, wherein a first bit line is formed in a drain region in advance during a capacitor formation process, a photoresist pattern is formed on the first bit line, and then an SOG film is applied to the semiconductor device. After the blanket is etched to expose the top of the photoresist pattern, the photoresist pattern is removed, and the bit line of the present invention is completed by forming a second bit line connected to the first bit line with the portion of the photoresist pattern removed. .

Therefore, the present invention can reduce the depth of the finally formed contact hole by forming the first bit line even when the size of the contact hole is narrow and deep, thereby eliminating defects in the device due to poor shape of the contact hole. The reliability and stabilization of the device can be achieved.

Description

Bit line formation method of semiconductor device

1 (a) to 1 (e) are cross-sectional views of devices shown for explaining the embodiments of the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: field oxide film

3: drain region 3A and 3B: first and second source region

4: gate oxide films 5A and 5B: first and second gate electrodes

6 poly interlayer insulating film 7 first bit line

8A and 8B: first and second charge storage electrodes 9A and 9B: first and second dielectric films

10A and 10B: first and second plate electrodes 11: photoresist pattern

12: SOG film 13: contact hole

70: second bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, by forming a first bit line in a drain region in advance in a process before forming a bit line, thereby reducing the step difference ratio of a contact hole in a subsequent bit line formation. It relates to a bit line forming method.

As semiconductor devices are highly integrated, the size of contact holes becomes smaller and deeper. In the process of forming such a contact hole, a phenomenon in which the contact hole is not completely open (not open contact) occurs. In particular, when the bit line is formed after the transistor and the capacitor are formed in the DRAM device, the depth of the contact hole is deep and the misalignment causes short circuit between the bit line and the gate electrode, thereby degrading the reliability of the device.

Accordingly, an object of the present invention is to provide a method for forming a bit line of a semiconductor device which can solve the above problems by forming the bit line over a second order.

According to an aspect of the present invention, there is provided a method of forming a poly interlayer insulating film on a silicon substrate on which a transistor including a gate, a source, and a drain is formed, and the source and drain regions of the transistor are respectively opened. Etching a portion, forming a first bit line connected to the drain region, forming a capacitor connected to the source region, forming a photoresist pattern on the first bit line; Applying an SOG film over the entire structure including the photoresist pattern and the capacitor, and then etching the entire SOG film until the upper portion of the photoresist pattern is exposed; and removing the exposed photoresist pattern to remove the first photoresist pattern. Forming a contact hole having a bottom of the bit line; And forming a second bit line connected to the first bit line by a polysilicon deposition and patterning process on the partially etched SOG film including the second bit line. do.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (e) are cross-sectional views of the elements shown for explaining the embodiments of the present invention.

The device illustrated to describe an embodiment of the present invention is a device having a dual gate structure in DRAM and a structure in which a capacitor is disposed under the bit line.

Referring to FIG. 1 (a), the field oxide film 2 is formed in the selected region of the silicon substrate 1, the active region is determined, and the first and second transistors are formed on the silicon substrate 1 in the active region. do. The first transistor is composed of a first gate electrode 5A and source and drain regions 3A and 3, and a gate oxide film 4 is formed between the first gate electrode 5A and the silicon substrate 1. The second transistor is composed of a second gate electrode 5B and source and drain regions 3B and 3, and a gate oxide film 4 is formed between the second gate electrode 5B and the silicon substrate 1. In general, the drain region 3 is commonly used in the double gate structure. A poly interlayer insulating film 6 is formed on the silicon substrate 1 including the first and second transistors, and a portion of the drain region 3 and the first and second source regions 3A and 3B are respectively formed through a contact mask process. After being exposed, a first bit line 7 is formed which is connected to the drain region 3. After the first bit line 7 is formed, first and second capacitors connected to the first and second source regions 3A and 3B, respectively, are formed by a general process. The first capacitor is composed of a first charge storage electrode 8A, a first dielectric film 9A, and a plate electrode 10A connected to the first source region 3A. The second capacitor includes a second charge storage electrode 8B, a second dielectric film 9B, and a second plate electrode 10B connected to the second source region 3B0. After the photoresist is applied over the entire structure including one and two capacitors, the photoresist pattern 11 is formed on the first bit line 7 by a lithography process using a bit line contact mask.

FIG. 1B is a cross-sectional view of the SOG film 12 coated on the entire structure including the photoresist pattern 11 and the first and second capacitors.

FIG. 1C is a cross-sectional view of the SOG film 12 being etched by a blanket plasma method until the upper portion of the photoresist pattern 11 is exposed.

FIG. 1D is a cross-sectional view of the contact hole 13 forming the bottom surface of the first bit line 7 by removing the exposed photoresist pattern 11.

FIG. 1E is a cross-sectional view of the second bit line 70 connected to the first bit line 7 by polysilicon deposition and patterning on the entire structure including the contact hole 13. This completes the bit line of the present invention with the first and second bit lines 7 and 70.

In the above-described embodiment of the present invention, the bit line is described as an embodiment, but a similar process may be applied, for example, to the metal hole forming hole having a deep contact hole.

In DRAM, a double gate structure, and a contact hole formed to connect a bit line to a drain region in a device having a capacitor under the bit line, have a deep depth, and thus, a contact during a contact hole forming process. There is a high possibility that the profile of the hole will be poor, and also a short circuit with the gate electrode upon misalignment. In order to solve this problem, in the present invention, during the capacitor formation process, the first bit line is formed in the drain region in advance, the photoresist pattern is formed on the first bit line, and then the SOG film is applied, and the top of the photoresist pattern is exposed. The bit line is completed by removing the photoresist pattern after the blanket etching as much as possible, and forming a second bit line connected to the first bit line with the portion where the photoresist pattern is removed.

Therefore, the present invention can reduce the depth of the finally formed contact hole by forming the first bit line even when the size of the contact hole is narrow and deep, thereby eliminating defect factors of the device due to poor shape of the contact hole. The reliability and stabilization of the device can be achieved.

Claims (3)

Forming a poly interlayer insulating film on the silicon substrate on which a transistor including a gate, a source, and a drain is formed; etching a portion of the poly interlayer insulating film to open the source and drain regions of the transistor; Forming a first bit line to be connected, forming a capacitor connected to the source region, forming a photoresist pattern on the first bit line, and an overall structure including the photoresist pattern and the capacitor After the SOG film is coated on the top, the SOG film is etched until the top of the photoresist pattern is exposed, and the contact hole is formed to remove the exposed photoresist pattern to form a bottom surface of the first bit line. And poles on the partially etched SOG film including the contact holes. Forming a second bit line connected to the first bit line by a silicon deposition and patterning process to complete a bit line formed of the first and second bit lines. . The method of claim 1, wherein the photoresist pattern is formed by a lithography process using a bit line contact mask. The method of claim 1, wherein the etching of the SOG film to expose the upper portion of the photoresist pattern is performed by a blanket plasma method.