KR100198637B1 - Fabricating method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that simultaneously forms a bit line contact in a memory cell region and a peripheral region in forming a bit line of a memory.

A method for fabricating a semiconductor device according to the present invention comprises the steps of: forming a field region and an active region on a semiconductor substrate by simultaneously forming a cell region and a peripheral region, Forming a gate insulating film on the gate insulating film; Forming a plurality of gate electrodes having a first conductive layer, a caprate first and a second insulating layer in the active region; Forming an impurity region on the substrate using the gate electrode as a mask; Forming a third insulating film and side walls on the side surfaces of the gate electrode; Selectively removing a third insulating film on the side surfaces of the cap gate second insulating film and the cap gate second insulating film in the peripheral region; Depositing a fourth insulating film on the entire surface and masking the upper portion of the impurity region of the cell region and the upper side of the gate electrode of the peripheral region to be exposed; Forming a contact hole such that a gate electrode of an impurity region and a peripheral region of the cell region are exposed; And depositing a second conductive layer on the entire surface.

Description

Method of manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that simultaneously forms a bit line contact in a memory cell region and a peripheral region in forming a bit line of a memory.

As the cell size is reduced due to the high integration of semiconductor devices, the yield is reduced due to misalignment in the formation of the contact holes.

Therefore, in order to solve such a problem, a method of manufacturing a semiconductor device which increases the contact margin by using an insulating material having different etching selection ratios is widely used.

That is, in the DRAM semiconductor device manufacturing process, a gate electrode and a source / drain impurity region are formed on a substrate, an insulating film is deposited on the entire surface, and a bit line contact hole is formed in the impurity region.

At this time, in order to improve the contact hole margin, the cap gate insulating film and the gate side insulating film of the gate electrode are formed of a nitride film and an oxide film is deposited on the entire surface. Then, the oxide film of the impurity region is selectively removed by a photo- .

Even if the contact hole is formed using the insulating material having different selectivity and the impurity region is not accurately aligned due to misalignment in the photolithography process, since the nitride film functions as an etch stopper, The gate electrode is not short-circuited.

A conventional method of manufacturing a semiconductor device using such a technique will be described as follows

Figures 1a-1 are process cross-sectional views illustrating a conventional bit line method.

As shown in FIG. 1A, a first nitride film 12 and a first photoresist film 13 are sequentially deposited on a semiconductor substrate 11.

The first photoresist layer 13 is selectively exposed and developed in the cell region 14 and the peripheral region 15 so as to be removed in the field region.

The first nitride layer 12 is selectively etched using the selectively exposed and developed first photoresist layer 13 as a mask, and then the first photoresist layer 13 is removed.

Then, the field oxide film 16 is grown by a thermal oxidation process using the first nitride film 12 as a mask, and then the first nitride film 12 is removed.

As shown in FIG. 1B, a gate oxide film 17 is grown on the semiconductor substrate 11 including the field oxide film 16 by a thermal oxidation process, and then the first polycrystalline silicon film, An oxide film and a second nitride film are sequentially deposited.

The gate electrode 20 is formed to selectively etch the first polycrystalline silicon, the oxide film, and the second nitride film, and to laminate the cap gate insulation film having the oxide film 18 and the second nitride film 19 double structure.

As shown in FIG. 1C, the first impurity region 21 is formed by ion-implanting a low-concentration impurity using the gate electrodes 20 as a mask.

The third nitride film 22 is deposited on the gate oxide film 17 including the gate electrodes 20 and etched back to form the gate electrode 20 and the oxide film 18 and the second nitride film 19 Side walls are formed on both sides.

As shown in FIG. 1d, a second impurity region 23 is formed by ion implanting a high concentration impurity using the gate electrodes 20 including the sidewalls as a mask, and a gate oxide film 17 including the gate electrodes 20 is formed. An interlayer dielectric (ILD) layer 24 formed of an oxide film and a second photoresist layer 25 are formed in this order.

Then, the second photoresist layer 25 is selectively exposed and developed so that only one impurity region of the cell region 14 is removed.

The ILD layer 24 and the gate oxide film 17 are sequentially etched using the selectively exposed and developed second photoresist film 25 as a mask.

The second photoresist layer 25 is removed and the third photoresist layer 25 is coated on the semiconductor substrate 11 including the ILD layer 24 as shown in FIG.

Then, the third photoresist layer 25 is selectively exposed and developed so as to be removed only on the predetermined gate electrode 20 of the peripheral region 15.

Then, the second nitride film 19 and the oxide film 18 are sequentially etched using the selectively exposed and developed third photoresist film 25 as a mask.

The reason why the contact hole of the cell region 14 and the contact hole of the peripheral region 14 can not be simultaneously performed by one etching process is as follows.

For example, the second photoresist film J4 is deposited, and the upper portion of the impurity region of the cell region 14 and the upper portion of the gate electrode of the peripheral region 15 are exposed. Then, the ILD layer 23 is removed by an etching process, The region 14 is removed to the gate insulating film 17 to expose the impurity region.

However, the gate electrode of the peripheral region 15 is not exposed because it is surrounded by the nitride film. Therefore, the nitride film on the upper side of the gate electrode of the peripheral region 15 must be removed.

At this time, if the nitride film on the upper side of the gate electrode of the peripheral region 15 is removed, the gate electrode side wall and the cap gate nitride film of the cell region 14 are also removed, so that the gate electrode is exposed in the cell region 14, The bit line and the gate electrode of the cell region are short-circuited.

The third photoresist layer 25 is removed and a second polycrystalline silicon layer 26 and a tungsten silicide layer 26 are formed on the semiconductor substrate 11 including the ILD layer 23 and the exposed gate electrode 20, (Tungsten silicide) 27 are sequentially deposited.

Then, a fourth photosensitive film (not shown in the figure) is coated on the tungsten silicide 27, and selectively exposed and developed so that only a part of the film is removed.

Then, the tungsten silicide layer 27 and the second polycrystalline silicon layer 26 are selectively etched using the selectively exposed and developed fourth photoresist layer as a mask. The bit line is formed by removing the fourth photosensitive film.

In the conventional method of manufacturing a semiconductor device, since the bit line contact hole is formed twice by dividing the bit line contact hole into a cell area and a peripheral area, there is less margin for over lap or misalignment between the bit line contact hole and the bit line There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device which eliminates a nitride film on a peripheral area gate before forming a bit line contact hole and simultaneously forms a bit line contact hole, And it is an object of the present invention to provide a manufacturing method of a semiconductor device which increases the margin.

Figures 1a-1f are process cross-sectional views illustrating a conventional bit line method;

Figures 2a through 2f are process cross-sectional views illustrating a bit line method in accordance with an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

31: semiconductor substrate 34: cell region

35: surrounding area 36: field oxide film

37: gate oxide film 38: oxide film

39: second nitride film 40: gate electrode

41: first impurity region 42: third nitride film

43: second impurity region 45: ILD

A method for fabricating a semiconductor device according to the present invention includes the steps of: forming a field oxide layer on a semiconductor substrate by defining a field region and an active region on a semiconductor substrate; Forming a plurality of gate electrodes each having a first conductive layer, a cap gate first and a second insulating film in the active region, forming an impurity region on the substrate using the gate electrode as a mask, A step of forming a side wall of a third insulating film on the side surface of the gate electrode, a step of selectively removing the third insulating film on the side of the cap gate second insulating film and the cap gate second insulating film in the peripheral region, Depositing a fourth insulating film and masking the upper portion of the impurity region of the cell region and the upper side of the gate electrode of the peripheral region to be exposed; Forming a contact hole such that a gate electrode of an impurity region and a peripheral region of the cell region are exposed; and depositing a second conductive layer on the entire surface.

FIG. 2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention; FIG.

Figures 2a through 2f are process cross-sectional views illustrating a bit line method in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the first nitride film 32 and the first photoresist film 33 are sequentially deposited on the semiconductor substrate 31.

The first photoresist layer 33 is selectively exposed and developed in the cell region 34 and the peripheral region 35 so as to be removed in the field region.

Then, the first nitride film 32 is selectively etched using the selectively exposed and developed first photoresist film 33 as a mask, and then the first photoresist film 33 is removed.

The field oxide film 36 is grown by a thermal oxidation process using the first nitride film 32 as a mask, and then the first nitride film 32 is removed.

As shown in FIG. 2b, a gate oxide film 37 is grown on the semiconductor substrate 31 including the field oxide film 36 by a thermal oxidation process, and then the first polycrystalline silicon, An oxide film and a second nitride film are sequentially deposited.

The gate electrode 40 is formed by selectively etching the first polycrystalline silicon, the oxide film, and the second nitride film to form a cap gate insulating film having a structure of an oxide film 38 and a second nitride film 39.

As shown in FIG. 2C, the first impurity region 41 is formed by ion-implanting a low-concentration impurity using the gate electrodes 40 as a mask.

The third nitride film 42 is deposited on the gate oxide film 37 including the gate electrodes 40 and etched back to form the gate electrode 40, the oxide film 38, and the second nitride film 39 Side walls are formed on both sides.

As shown in FIG. 2d, the second impurity region 43 is formed by implanting high-concentration impurity ions using the gate electrodes 40 including the sidewalls as a mask.

Then, the second photoresist layer 44 is coated on the gate oxide layer 37 including the gate electrodes 40.

Then, the second photoresist layer 44 is selectively exposed and developed so as to remain only in the cell region 34.

The second and third nitride films 39 and 42 on the oxide film 38 in the peripheral region gate electrode 40 are subjected to reactive ion etching (RIE) using the selectively exposed and developed second photoresist film 44 as a mask, Etch using the method.

2E, the second photoresist layer 44 is removed and an ILD layer 45 and a third photoresist layer 46 are sequentially formed on the gate oxide layer 37 including the gate electrodes 40, do.

The third photoresist layer 46 is formed to be removed only in one impurity region of the cell region 34 and in the gate electrode 49 on which the second and third nitride films 39 and 42 of the peripheral region 35 are etched. Selectively exposed and developed.

The ILD layer 45 and the gate oxide film 37 and the oxide film 38 are selectively etched using the selectively exposed and developed third photoresist film 46 as a mask.

2f, the third photoresist layer 46 is removed and a second polycrystalline silicon layer 47 and a tungsten silicide layer (not shown) are formed on the semiconductor substrate 31 including the ILD layer 45 and the exposed gate electrode 40, (48) are sequentially deposited.

A fourth photoresist layer (not shown) is coated on the tungsten silicide layer 48 and selectively exposed and developed to remove only a portion of the photoresist layer.

Then, the tungsten silicide layer 48 and the second polycrystalline silicon layer 47 are selectively etched using the selectively exposed and developed fourth photoresist layer as a mask.

The bit line is formed by removing the fourth photosensitive film.

The method of manufacturing a semiconductor device of the present invention has an effect of greatly improving the yield of devices by increasing the margin of overlap or mis-alignment between bit line contact holes and bit lines.

Claims (3)

A method of manufacturing a semiconductor device, comprising: forming a field oxide film on a field region and a gate insulating film on an active region by defining a field region and an active region on a semiconductor substrate; Forming a plurality of gate electrodes having a first conductive layer, a caprate first and a second insulating layer in the active region; Forming an impurity region on the substrate using the gate electrode as a mask; Forming a third insulating film and side walls on the side surfaces of the gate electrode; Selectively removing a third insulating film on the side surfaces of the cap gate second insulating film and the cap gate second insulating film in the peripheral region; Depositing a fourth insulating film on the entire surface and masking the upper portion of the impurity region of the cell region and the upper side of the gate electrode of the peripheral region to be exposed; Forming a contact hole such that a gate electrode of an impurity region and a peripheral region of the cell region are exposed; And depositing a second conductive layer over the entire surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film and the third insulating film have the same properties and use an insulating film having a larger etching selectivity ratio than the fourth insulating film and the first insulating film. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film, the first insulating film, and the fourth insulating film are formed as an oxide film and the second and third insulating films are formed as a nitride film.