KR970011758B1 - A method for fabricating dram cells - Google Patents

Abstract

The present invention relates to a method of forming a conductive film of semiconductor integrated circuit which prevents pattern degradation. This method includes the steps of forming a field oxide film (2) and a gate insulating film (3) on a semiconductor substrate (1), and forming a conductive film all over the surface, and selectively etching the same to form a preliminary gate electrode and word line (4F); implanting relatively low density impurities; forming a space insulating film (5) by deposition and anisotropic etching, and implanting relatively high density impurities, thus forming an LDD active region (6'); planarizing with an insulating film (7) and selectively etching the insulating film (7) and preliminary gate electrode and word line (4F) and forming a gate electrode and word line (4') at the same time.

Description

Method for forming conductive film in semiconductor integrated circuit

1 is a plan view of a mask for forming a DRAM according to a conventional method,

2 is a cross-sectional view of the process using the mask of FIG.

3 is a plan view of a mask for forming a DRAM of an embodiment according to the present invention,

4 is a cross-sectional view of the process using the mask of FIG.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2: Field oxide film

3: gate oxide films 4, 4 ', 4F: gate electrode and word line

5, 19: spacer insulating film 6, 6 ': LDD active region

7, 13: insulating film 8, 14: mask polysilicon film

9, 15: spacer polysilicon film 10: charge preservation electrode

11 dielectric film 12 plate electrode

16 bit line electrode 17, 17 ', 18: photosensitive film

a, a ': isolation region mask b: gate electrode and word line mask

b ': first gate electrode and word line mask c: contact hole mask

c ': second gate electrode and word line and contact hole mask

d, d ': second conductive film mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for forming a conductive film of a semiconductor integrated circuit which prevents a pattern defect when forming a conductive film.

As semiconductor integrated circuits are increasingly integrated, gaps between devices and devices, conductive films, and conductive films are reduced, and accordingly, steps are relatively increased. Such step and step spacing cause more difficulties and problems in the manufacturing process as the semiconductor is highly integrated.

For example, in order to form a plurality of transistors essential for a semiconductor integrated circuit, a region must be separated by a field oxide film or the like, and a gate electrode pattern must be formed to separate the electrode from the electrode. This becomes difficult or impossible.

Prior to describing the technology of the present invention, the prior art and its problems will be briefly described with reference to FIGS. 1 and 2.

1 is a mask diagram for forming a DRAM, which is a memory device, wherein a is a separation region mask, b is a gate electrode and a word line mask, c is a charge storage contact hole, and d is a charge storage electrode. Mask, e is a plate electrode mask, f is a bit line contact hole mask, g is a bit line electrode mask, and FIG. 2A and 2B show the process cross section in the AA 'direction of FIG.

First, as shown in FIG. 2A, the field oxide film 2 is formed on the semiconductor substrate 1, the gate oxide film 3 is grown, the conductive film 4 for the gate electrode is deposited, and the photosensitive film 17 The gate electrode is patterned through an exposure process and an etching process using At this time, the incident light during the exposure process causes diffuse reflection and damages the photosensitive film (17 '), and when the etching process is performed using this, it causes the notching of the electrode to deteriorate the transistor characteristics. Or in severe cases, the electrode may be shorted.

Subsequently, the gate electrode and word line 4 patterns are formed in FIG. 2B, and then lightly doped drain (LDD) using a spacer oxide film 5 to improve the electrical characteristics of the MOSFET due to the high integration. MOSFET formation process having active regions 6 and 6 'having a structure, followed by first forming an insulating film 7 of constant thickness, followed by a mask polysilicon film 8 and a spacer polysilicon film 9 Charge storage contact hole is formed on the active region 6 by selective etching, and a charge storage electrode polysilicon film in which impurities are implanted is deposited on the contact hole and connected to the active region 6, and a predetermined mask is used. After the charge storage electrode 10 is formed to a size of, the dielectric film 11 having a nitride film-oxide film (NO) or oxide film-nitride film-oxide film (ONO) composite structure is grown, and a polysilicon film implanted with impurities is formed thereon. At the size of After patterning, the plate electrode 12 is formed, the insulating film 13 is formed secondary, and then selectively etched on the active region 6 'using the mask polysilicon film 14 and the spacer polysilicon film 15. The DRAM cell process is completed by forming a bit line contact hole, depositing a bit line conductive film, and forming the bit line electrode 16 to a predetermined size.

However, as mentioned above, when the light coming in during the exposure process causes diffuse reflection to damage the photoresist film, and the etching process is performed using this, a conductive film is formed as shown by the dotted line of FIG. 2B to notch the electrode. This results in deterioration of transistor characteristics or, in severe cases, short circuit of the electrodes.

The present invention devised to solve the above problems is to provide a method for forming a conductive film of a semiconductor integrated circuit that can prevent a short circuit or kneading relatively easily when patterning an electrode or a connecting line.

In order to achieve the above object, the present invention comprises the steps of forming a field oxide film and a gate insulating film on a semiconductor substrate, and then forming a conductive film on the entire structure and selectively etching to a predetermined size to form a preliminary gate electrode and a word line pattern; Forming a spacer insulating film by performing a relatively low concentration ion implantation process, performing deposition and anisotropic etching on a predetermined thickness of an insulating film, and then performing a relatively high concentration ion implantation process to form an active region of an LDD structure; And planarizing the insulating film, and then selectively etching the insulating film, the preliminary gate electrode, and the word line pattern to form contact holes, the gate electrode, and the word line at the same time.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a mask diagram for fabricating a DRAM cell according to the present invention, wherein a is an isolation region mask, b is a first gate electrode and a word line mask, c is a charge storage contact and a second gate electrode and a word line mask, d A denotes a charge storage electrode mask, e denotes a plate electrode mask, f denotes a bit line contact hole mask, g denotes a bit line electrode mask, and A- to fabricate a DRAM cell using the mask of FIGS. 4A to 4D or 3. Process cross section in the A 'direction.

First, the field oxide film 2 is grown on the semiconductor substrate 1 having the P-well (or N-well) formed thereon using the isolation region mask a in a LOCOS method, and then the gate oxide film ( 3) and a polysilicon film for a gate electrode and a word line are deposited without time delay, and then an impurity implantation process is performed on the polysilicon film, and the photoresist film 17 and the polysilicon are formed using the first gate electrode and the word line mask b '. Is a cross-sectional view of etching a predetermined size to form a preliminary gate electrode and a word line 4F pattern.

3B shows that the photoresist film 17 is removed, a relatively low concentration ion implantation process is performed, an insulating film having a predetermined thickness is deposited and anisotropically etched to form a first spacer insulating film 5, and a relatively high concentration ion implantation is performed. By performing the step, the active region 6 'of the first LDD structure is formed, then the first insulating film 7 is deposited and planarized, the photosensitive film 18 is applied, and then the second gate electrode and the word line and contact are made. The photosensitive film 18 is exposed and developed using a mask c ', and the first insulating film 7, the preliminary gate electrode and the word line polysilicon film are sequentially etched using the mask c' as an obstacle to sequentially contact the contact hole, the gate electrode and the word line. It is sectional drawing of the state which formed 4 'simultaneously. As shown in the figure, even if there is a step of the field oxide film, the photo process is performed on the planarization insulating film, so that the photoresist film can be developed without nerving due to diffuse reflection or the like to form a gate electrode and a word line of a desired size.

In the state of FIG. 3C or 3B, a relatively low concentration ion implantation process is performed, the photosensitive film 18 is removed, an insulating film having a predetermined thickness is deposited, anisotropic etching is performed to form the second spacer insulating film 19, and the relative By performing a high concentration ion implantation process, the active region 6 of the second LDD structure is formed, and then the charge preservation electrode 10 is formed to a predetermined size by using the charge preservation electrode mask d implanted with impurities. The dielectric film 11 is grown along its surface, and the polysilicon film into which impurities are implanted is patterned to a predetermined size using the plate electrode mask e to form the plate electrode 12. to be.

After forming the second insulating film 13 on the 3D or the entire structure, the mask polysilicon film 14 is deposited, and the mask polysilicon film 14 and the first layer are formed using the bit line contact hole mask f. 2 A portion of the insulating film 13 is selectively etched, and then a polysilicon film having a predetermined thickness is deposited, and anisotropically etched to form a spacer polysilicon film 15 to form a mask polysilicon film 14 and a spacer polysilicon. Using the film 15 as an obstacle, the remaining second insulating film is selectively etched to form a bit line contact hole on the active region 6 ', and then a bit line conductive film is deposited, and the bit line electrode mask g is used. It is sectional drawing which completed the process of the DRAM cell using the method of this invention by forming the bit line electrode 16 by a predetermined magnitude | size.

According to the present invention as described above, when forming an electrode or a connection line, a desired pattern is formed while preventing shorting or notching relatively easily, thereby preventing deterioration of characteristics such as transistors or connection lines, thereby making it possible to produce highly reliable products. Do.

In addition, by forming a contact and an electrode at the same time, the area of the cell can be reduced compared to the conventional case, and the number of basic chips can be increased on the same wafer, contributing to high integration.

Claims (4)

In the method for forming a conductive film of a semiconductor integrated circuit, a field oxide film 2 and a gate insulating film 3 are formed on a semiconductor substrate 1, and then a conductive film is formed over an entire structure and selectively etched to a predetermined size to provide a preliminary gate electrode and Forming a word line 4F pattern; A relatively low concentration ion implantation process is performed, and a spacer insulation film 5 is formed by performing deposition and anisotropic etching on a constant thickness insulating film, and then performing a relatively high concentration ion implantation process, thereby forming an active region of the LDD structure (6). Forming a '); And planarizing the insulating film 7, and then sequentially etching the insulating film 7, the preliminary gate electrode, and the word line 4F pattern to form contact holes, the gate electrode, and the word line 4 ′ at the same time. And a conductive film forming method of a semiconductor integrated circuit. The method of claim 1, wherein the contact hole, the gate electrode, and the word line 4 'are simultaneously formed, and then a relatively low concentration ion implantation process is performed, an insulating film having a predetermined thickness is deposited, and anisotropic etching is performed. By forming the spacer insulating film 19 and performing a relatively high concentration ion implantation process, the active region 6 of the LDD structure is formed, and then connected to the charge storage electrode conductive film active region 6, and the conductive film is selected. And forming a charge preservation electrode (10) by etching the conductive film forming method of the semiconductor integrated circuit. The method of claim 2, further comprising: forming a dielectric layer (11) on the surface of the charge storage electrode (10) and forming a plate electrode (12) after the formation of the charge storage electrode (10); After the insulating film 13 is formed over the entire structure, the mask polysilicon film 14 is formed, and the mask polysilicon film 14 and a part of the insulating film 13 are selectively etched, and then polysilicon having a predetermined thickness is formed. After the film is deposited and anisotropically etched to form the spacer polysilicon film 15, the insulating film 13 is selectively etched to form bit line contact holes on the active region 6 ', and then bit line conduction. And forming a film and selectively etching the film to a predetermined size to form a bit line electrode (16). 2. The conduction of the semiconductor integrated circuit according to claim 1, wherein a high concentration ion implantation process is omitted during the formation of the active region, and impurities are diffused by using a polysilicon film into which the impurities are implanted in the charge storage electrode and the bit line electrode. Film formation method.